`

    #Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010
    #install: \\dm6\partner_tool\Synplicity\release_installs\synplify_D200912A
    #OS: Windows XP 5.1
    #Hostname: WXP-ALIMS

    #Implementation: synthesis

    #Wed Feb 10 09:42:25 2010

    $ Start of Compile
    #Wed Feb 10 09:42:25 2010

    Synopsys VHDL Compiler, version comp475rc, Build 060R, built Jan 15 2010
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    Top entity isn't set yet!
    @W:CD645 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(5) | Ignoring undefined library smartfusion
    @W:CD643 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(6) | Ignoring use clause - smartfusion not found ...
    @W:CD645 : my_mss.vhd(5) | Ignoring undefined library smartfusion
    @W:CD643 : my_mss.vhd(6) | Ignoring use clause - smartfusion not found ...
    @W:CD645 : Top.vhd(5) | Ignoring undefined library smartfusion
    @W:CD643 : Top.vhd(6) | Ignoring use clause - smartfusion not found ...
    VHDL syntax check successful!
    File D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_cnt\component\Actel\DirectCore\CoreAPB3\2.1.101\rtl\vhdl\o\MuxPtoB3.vhd changed - recompiling
    File D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_cnt\hdl\Count32.vhd changed - recompiling
    File \\dm6\partner_tool\Synplicity\release_installs\synplify_D200912A\lib\vhd\arith.vhd changed - recompiling
    File \\dm6\partner_tool\Synplicity\release_installs\synplify_D200912A\lib\vhd\unsigned.vhd changed - recompiling
    File D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_cnt\component\Actel\SmartFusionMSS\MSS\1.0.101\mss_comps.vhd changed - recompiling
    File D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_cnt\component\Actel\DirectCore\CoreAPB3\2.1.101\rtl\vhdl\o\CoreAPB3.vhd changed - recompiling
    File D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_cnt\hdl\APB_cnt.vhd changed - recompiling
    File D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_cnt\component\work\my_mss\MSS_CCC_0\my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd changed - recompiling
    File D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_cnt\component\work\my_mss\my_mss.vhd changed - recompiling
    File D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_cnt\component\work\Top\Top.vhd changed - recompiling
    @N:CD630 : Top.vhd(8) | Synthesizing work.top.def_arch
    @W:CD280 : Top.vhd(112) | Unbound component VCC mapped to black box
    @W:CD280 : Top.vhd(133) | Unbound component GND mapped to black box
    @N:CD630 : Top.vhd(133) | Synthesizing work.gnd.syn_black_box
    Post processing for work.gnd.syn_black_box
    @N:CD630 : my_mss.vhd(8) | Synthesizing work.my_mss.def_arch
    @N:CD630 : mss_comps.vhd(421) | Synthesizing work.mss_apb.def_arch
    Post processing for work.mss_apb.def_arch
    @N:CD630 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(8) | Synthesizing work.my_mss_tmp_mss_ccc_0_mss_ccc.def_arch
    @W:CD280 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(77) | Unbound component RCOSC mapped to black box
    @W:CD280 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(82) | Unbound component INV mapped to black box
    @N:CD630 : Top.vhd(112) | Synthesizing work.vcc.syn_black_box
    Post processing for work.vcc.syn_black_box
    @N:CD630 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(82) | Synthesizing work.inv.syn_black_box
    Post processing for work.inv.syn_black_box
    @N:CD630 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(77) | Synthesizing work.rcosc.syn_black_box
    Post processing for work.rcosc.syn_black_box
    @N:CD630 : mss_comps.vhd(926) | Synthesizing work.mss_ccc.def_arch
    Post processing for work.mss_ccc.def_arch
    Post processing for work.my_mss_tmp_mss_ccc_0_mss_ccc.def_arch
    @N:CD630 : mss_comps.vhd(4) | Synthesizing work.inbuf_mss.def_arch
    Post processing for work.inbuf_mss.def_arch
    Post processing for work.my_mss.def_arch
    @N:CD630 : APB_cnt.vhd(24) | Synthesizing work.apb_cnt.synth
    @N:CD630 : Count32.vhd(6) | Synthesizing work.count32.behavioral
    Post processing for work.count32.behavioral
    Post processing for work.apb_cnt.synth
    @N:CD630 : CoreAPB3.vhd(3) | Synthesizing work.coreapb3.coreapb3_o
    @W:CD604 : CoreAPB3.vhd(401) | OTHERS clause is not synthesized
    @N:CD630 : MuxPtoB3.vhd(3) | Synthesizing work.coreapb3_l.coreapb3_i0ll
    @W:CD604 : MuxPtoB3.vhd(178) | OTHERS clause is not synthesized
    @W:CD604 : MuxPtoB3.vhd(222) | OTHERS clause is not synthesized
    @W:CD604 : MuxPtoB3.vhd(266) | OTHERS clause is not synthesized
    Post processing for work.coreapb3_l.coreapb3_i0ll
    Post processing for work.coreapb3.coreapb3_o
    Post processing for work.top.def_arch
    @W:CL159 : CoreAPB3.vhd(76) | Input PSLVERRS12 is unused
    @W:CL159 : CoreAPB3.vhd(77) | Input PSLVERRS13 is unused
    @W:CL159 : CoreAPB3.vhd(78) | Input PSLVERRS14 is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(10) | Input CLKA is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(11) | Input CLKA_PAD is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(12) | Input CLKA_PADP is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(13) | Input CLKA_PADN is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(14) | Input MAINXIN is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(15) | Input CLKC is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(16) | Input CLKC_PAD is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(17) | Input CLKC_PADP is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(18) | Input CLKC_PADN is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(19) | Input FB_CLK is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(20) | Input MAC_CLK is unused
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Feb 10 09:42:26 2010

    ###########################################################]
    Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
    Product Version D-2009.12A
    @N:MF249 :  | Running in 32-bit mode.
    @N:MF258 :  | Gated clock conversion disabled

    Automatic dissolve at startup in view:work.my_mss(def_arch) of MSS_CCC_0(my_mss_tmp_MSS_CCC_0_MSS_CCC)
    Automatic dissolve at startup in view:work.Top(def_arch) of my_mss_0(my_mss)
    Automatic dissolve at startup in view:work.Top(def_arch) of CoreAPB3_0(CoreAPB3)

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

    @N:MO106 : coreapb3.vhd(368) | Found ROM, 'CoreAPB3_0.COREAPB3_il0_17[15:0]', 16 words by 16 bits
    @N: : count32.vhd(25) | Found counter in view:work.Count32(behavioral) inst Qaux[31:0]
    Auto Dissolve of CoreAPB3_0.COREAPB3_l0ll (inst of view:work.COReAPB3_l(coreapb3_i0ll))
    Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB)

    Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB)

    Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB)

    Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB)

    Finished Early Timing Optimization (Time elapsed 0h:00m:04s; Memory used current: 59MB peak: 59MB)

    Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:04s; Memory used current: 59MB peak: 59MB)

    Finished preparing to map (Time elapsed 0h:00m:04s; Memory used current: 60MB peak: 60MB)

    High Fanout Net Report
    **********************

    Driver Instance / Pin Name                    Fanout, notes
    ----------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST / M2FRESETn           98 : 98 asynchronous set/reset
    APB_cnt_0.p_data_out.un18_pwrite_0_a2 / Y     32
    APB_cnt_0.un1_loaden_cntzero_m3_i / Y         31
    APB_cnt_0.p_data_out.un22_pwrite_0_a2 / Y     31
    APB_cnt_0.DataOut_sn_m2 / Y                   33
    APB_cnt_0.my_counter.Qauxlde_m4_i / Y         32
    APB_cnt_0.p_reg_seq.un12_pwrite_0_a2 / Y      32
    CoreAPB3_0.COREAPB3_il0_0_a2_1[0] / Y         34
    CoreAPB3_0.COREAPB3_il0_0_a2_2[0] / Y         34
    ============================================================================

    Replicating Combinational Instance CoreAPB3_0.COREAPB3_il0_0_a2_2[0], fanout 34 segments 2
    Replicating Combinational Instance CoreAPB3_0.COREAPB3_il0_0_a2_1[0], fanout 34 segments 2
    Replicating Combinational Instance APB_cnt_0.p_reg_seq.un12_pwrite_0_a2, fanout 32 segments 2
    Replicating Combinational Instance APB_cnt_0.my_counter.Qauxlde_m4_i, fanout 32 segments 2
    Replicating Combinational Instance APB_cnt_0.DataOut_sn_m2, fanout 33 segments 2
    Replicating Combinational Instance APB_cnt_0.p_data_out.un22_pwrite_0_a2, fanout 32 segments 2
    Replicating Combinational Instance APB_cnt_0.un1_loaden_cntzero_m3_i, fanout 31 segments 2
    Replicating Combinational Instance APB_cnt_0.p_data_out.un18_pwrite_0_a2, fanout 32 segments 2
    Buffering my_mss_0_FAB_CLK, fanout 99 segments 5
    Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 60MB peak: 60MB)

    Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 60MB peak: 60MB)

    Added 4 Buffers
    Added 8 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 8 Combinational Cells via replication
    Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 60MB peak: 60MB)

    Writing Analyst data base D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_cnt\synthesis\Top.srm
    Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 59MB peak: 60MB)

    Writing EDIF Netlist and constraint files
    D-2009.12A
    Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 59MB peak: 60MB)

    @W:MT420 :  | Found inferred clock Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:my_mss_0_FAB_CLK"

    @W:MT246 : my_mss.vhd(340) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed Feb 10 09:42:32 2010
    #

    Top view:               Top
    Library name:           smartfusion
    Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Wire load model:        smartfusion
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing..

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock..

    Performance Summary
    *******************

    Worst slack in design: -6.165

                                                               Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                                             Frequency     Frequency     Period        Period        Slack      Type         Group
    --------------------------------------------------------------------------------------------------------------------------------------------------------------
    Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     100.0 MHz     61.9 MHz      10.000        16.165        -6.165     inferred     Inferred_clkgroup_0
    System                                                     100.0 MHz     171.5 MHz     10.000        5.831         4.169      system       default_clkgroup
    ==============================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                                Ending                                                  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock  Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock  |  10.000      -6.165  |  No paths    -      |  No paths    -      |  No paths    -
    =======================================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    		No IO constraint found

    ====================================
    Detailed Report for Clock: Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                      Starting                                                                                      Arrival
    Instance                          Reference                                                  Type         Pin     Net           Time        Slack
                                      Clock
    --------------------------------------------------------------------------------------------------------------------------------------------------
    APB_cnt_0.my_counter.Qaux[0]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       Count[0]      0.737       -6.165
    APB_cnt_0.my_counter.Qaux[2]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       Count[2]      0.737       -5.713
    APB_cnt_0.my_counter.Qaux[1]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       Count[1]      0.737       -5.553
    APB_cnt_0.my_counter.Qaux[3]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       Count[3]      0.737       -5.196
    APB_cnt_0.my_counter.Qaux[4]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       Count[4]      0.737       -4.965
    APB_cnt_0.my_counter.Qaux[6]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       Count[6]      0.737       -4.826
    APB_cnt_0.my_counter.Qaux[5]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       Count[5]      0.737       -4.687
    APB_cnt_0.my_counter.Qaux[7]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       Count[7]      0.737       -4.449
    APB_cnt_0.my_counter.Qaux[12]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       Count[12]     0.737       -4.267
    APB_cnt_0.my_counter.Qaux[13]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       Count[13]     0.737       -4.032
    ==================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                      Starting                                                                                                 Required
    Instance                          Reference                                                  Type         Pin     Net                      Time         Slack
                                      Clock
    --------------------------------------------------------------------------------------------------------------------------------------------------------------
    APB_cnt_0.my_counter.Qaux[31]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       Qaux_n31_0_N_9_i_i_0     9.461        -6.165
    APB_cnt_0.my_counter.Qaux[1]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       Qaux_n1                  9.461        -5.355
    APB_cnt_0.my_counter.Qaux[3]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       Qaux_n3                  9.461        -5.355
    APB_cnt_0.my_counter.Qaux[4]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       Qaux_n4                  9.461        -5.355
    APB_cnt_0.my_counter.Qaux[10]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       N_38_0                   9.461        -5.355
    APB_cnt_0.my_counter.Qaux[16]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       N_105                    9.461        -5.355
    APB_cnt_0.my_counter.Qaux[17]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       N_107                    9.461        -5.355
    APB_cnt_0.my_counter.Qaux[21]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       Qaux_n21                 9.461        -5.355
    APB_cnt_0.my_counter.Qaux[22]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       Qaux_n22                 9.461        -5.355
    APB_cnt_0.my_counter.Qaux[23]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       Qaux_n23                 9.461        -5.355
    ==============================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      15.626
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -6.165

        Number of logic level(s):                8
        Starting point:                          APB_cnt_0.my_counter.Qaux[0] / Q
        Ending point:                            APB_cnt_0.my_counter.Qaux[31] / D
        The start point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                       Type         Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    APB_cnt_0.my_counter.Qaux[0]               DFN1E1C0     Q        Out     0.737     0.737       -
    Count[0]                                   Net          -        -       1.279     -           5
    APB_cnt_0.my_counter.Qaux_RNIPF03[1]       OR2          B        In      -         2.016       -
    APB_cnt_0.my_counter.Qaux_RNIPF03[1]       OR2          Y        Out     0.646     2.663       -
    countiszero_1                              Net          -        -       1.526     -           7
    APB_cnt_0.my_counter.Qaux_RNIMF16[3]       OR2A         B        In      -         4.189       -
    APB_cnt_0.my_counter.Qaux_RNIMF16[3]       OR2A         Y        Out     0.646     4.835       -
    countiszero_17                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNISV4C[3]       NOR2         B        In      -         6.019       -
    APB_cnt_0.my_counter.Qaux_RNISV4C[3]       NOR2         Y        Out     0.646     6.665       -
    countiszero_25                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNIAO5E1[15]     OR2B         B        In      -         7.849       -
    APB_cnt_0.my_counter.Qaux_RNIAO5E1[15]     OR2B         Y        Out     0.516     8.365       -
    countiszero_29                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNIG8O04[26]     NOR2         A        In      -         9.549       -
    APB_cnt_0.my_counter.Qaux_RNIG8O04[26]     NOR2         Y        Out     0.507     10.056      -
    TIMINT_c                                   Net          -        -       1.423     -           6
    APB_cnt_0.LoadEnReg_RNIRLM34               OR2          A        In      -         11.479      -
    APB_cnt_0.LoadEnReg_RNIRLM34               OR2          Y        Out     0.363     11.842      -
    un1_loaden_cntzero_0                       Net          -        -       2.172     -           16
    APB_cnt_0.my_counter.Qaux_RNO_1[31]        MX2C         S        In      -         14.015      -
    APB_cnt_0.my_counter.Qaux_RNO_1[31]        MX2C         Y        Out     0.480     14.495      -
    Qaux_n31_0_N_8                             Net          -        -       0.322     -           1
    APB_cnt_0.my_counter.Qaux_RNO[31]          AX1A         C        In      -         14.816      -
    APB_cnt_0.my_counter.Qaux_RNO[31]          AX1A         Y        Out     0.488     15.304      -
    Qaux_n31_0_N_9_i_i_0                       Net          -        -       0.322     -           1
    APB_cnt_0.my_counter.Qaux[31]              DFN1E1C0     D        In      -         15.626      -
    =========================================================================================================
    Total path delay (propagation time + setup) of 16.165 is 5.570(34.5%) logic and 10.595(65.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      15.174
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -5.713

        Number of logic level(s):                8
        Starting point:                          APB_cnt_0.my_counter.Qaux[2] / Q
        Ending point:                            APB_cnt_0.my_counter.Qaux[31] / D
        The start point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                       Type         Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    APB_cnt_0.my_counter.Qaux[2]               DFN1E1C0     Q        Out     0.737     0.737       -
    Count[2]                                   Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNITV03[3]       NOR2         B        In      -         1.921       -
    APB_cnt_0.my_counter.Qaux_RNITV03[3]       NOR2         Y        Out     0.646     2.567       -
    countiszero_17_0                           Net          -        -       1.279     -           5
    APB_cnt_0.my_counter.Qaux_RNIMF16[3]       OR2A         A        In      -         3.846       -
    APB_cnt_0.my_counter.Qaux_RNIMF16[3]       OR2A         Y        Out     0.537     4.383       -
    countiszero_17                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNISV4C[3]       NOR2         B        In      -         5.567       -
    APB_cnt_0.my_counter.Qaux_RNISV4C[3]       NOR2         Y        Out     0.646     6.213       -
    countiszero_25                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNIAO5E1[15]     OR2B         B        In      -         7.397       -
    APB_cnt_0.my_counter.Qaux_RNIAO5E1[15]     OR2B         Y        Out     0.516     7.913       -
    countiszero_29                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNIG8O04[26]     NOR2         A        In      -         9.097       -
    APB_cnt_0.my_counter.Qaux_RNIG8O04[26]     NOR2         Y        Out     0.507     9.604       -
    TIMINT_c                                   Net          -        -       1.423     -           6
    APB_cnt_0.LoadEnReg_RNIRLM34               OR2          A        In      -         11.027      -
    APB_cnt_0.LoadEnReg_RNIRLM34               OR2          Y        Out     0.363     11.391      -
    un1_loaden_cntzero_0                       Net          -        -       2.172     -           16
    APB_cnt_0.my_counter.Qaux_RNO_1[31]        MX2C         S        In      -         13.563      -
    APB_cnt_0.my_counter.Qaux_RNO_1[31]        MX2C         Y        Out     0.480     14.043      -
    Qaux_n31_0_N_8                             Net          -        -       0.322     -           1
    APB_cnt_0.my_counter.Qaux_RNO[31]          AX1A         C        In      -         14.364      -
    APB_cnt_0.my_counter.Qaux_RNO[31]          AX1A         Y        Out     0.488     14.852      -
    Qaux_n31_0_N_9_i_i_0                       Net          -        -       0.322     -           1
    APB_cnt_0.my_counter.Qaux[31]              DFN1E1C0     D        In      -         15.174      -
    =========================================================================================================
    Total path delay (propagation time + setup) of 15.713 is 5.460(34.8%) logic and 10.253(65.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      15.014
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -5.553

        Number of logic level(s):                8
        Starting point:                          APB_cnt_0.my_counter.Qaux[1] / Q
        Ending point:                            APB_cnt_0.my_counter.Qaux[31] / D
        The start point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                       Type         Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    APB_cnt_0.my_counter.Qaux[1]               DFN1E1C0     Q        Out     0.737     0.737       -
    Count[1]                                   Net          -        -       0.806     -           3
    APB_cnt_0.my_counter.Qaux_RNIPF03[1]       OR2          A        In      -         1.543       -
    APB_cnt_0.my_counter.Qaux_RNIPF03[1]       OR2          Y        Out     0.507     2.051       -
    countiszero_1                              Net          -        -       1.526     -           7
    APB_cnt_0.my_counter.Qaux_RNIMF16[3]       OR2A         B        In      -         3.577       -
    APB_cnt_0.my_counter.Qaux_RNIMF16[3]       OR2A         Y        Out     0.646     4.223       -
    countiszero_17                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNISV4C[3]       NOR2         B        In      -         5.407       -
    APB_cnt_0.my_counter.Qaux_RNISV4C[3]       NOR2         Y        Out     0.646     6.053       -
    countiszero_25                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNIAO5E1[15]     OR2B         B        In      -         7.237       -
    APB_cnt_0.my_counter.Qaux_RNIAO5E1[15]     OR2B         Y        Out     0.516     7.753       -
    countiszero_29                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNIG8O04[26]     NOR2         A        In      -         8.937       -
    APB_cnt_0.my_counter.Qaux_RNIG8O04[26]     NOR2         Y        Out     0.507     9.444       -
    TIMINT_c                                   Net          -        -       1.423     -           6
    APB_cnt_0.LoadEnReg_RNIRLM34               OR2          A        In      -         10.867      -
    APB_cnt_0.LoadEnReg_RNIRLM34               OR2          Y        Out     0.363     11.231      -
    un1_loaden_cntzero_0                       Net          -        -       2.172     -           16
    APB_cnt_0.my_counter.Qaux_RNO_1[31]        MX2C         S        In      -         13.403      -
    APB_cnt_0.my_counter.Qaux_RNO_1[31]        MX2C         Y        Out     0.480     13.883      -
    Qaux_n31_0_N_8                             Net          -        -       0.322     -           1
    APB_cnt_0.my_counter.Qaux_RNO[31]          AX1A         C        In      -         14.204      -
    APB_cnt_0.my_counter.Qaux_RNO[31]          AX1A         Y        Out     0.488     14.693      -
    Qaux_n31_0_N_9_i_i_0                       Net          -        -       0.322     -           1
    APB_cnt_0.my_counter.Qaux[31]              DFN1E1C0     D        In      -         15.014      -
    =========================================================================================================
    Total path delay (propagation time + setup) of 15.553 is 5.431(34.9%) logic and 10.122(65.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      14.816
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -5.355

        Number of logic level(s):                7
        Starting point:                          APB_cnt_0.my_counter.Qaux[0] / Q
        Ending point:                            APB_cnt_0.my_counter.Qaux[25] / D
        The start point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                       Type         Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    APB_cnt_0.my_counter.Qaux[0]               DFN1E1C0     Q        Out     0.737     0.737       -
    Count[0]                                   Net          -        -       1.279     -           5
    APB_cnt_0.my_counter.Qaux_RNIPF03[1]       OR2          B        In      -         2.016       -
    APB_cnt_0.my_counter.Qaux_RNIPF03[1]       OR2          Y        Out     0.646     2.663       -
    countiszero_1                              Net          -        -       1.526     -           7
    APB_cnt_0.my_counter.Qaux_RNIMF16[3]       OR2A         B        In      -         4.189       -
    APB_cnt_0.my_counter.Qaux_RNIMF16[3]       OR2A         Y        Out     0.646     4.835       -
    countiszero_17                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNISV4C[3]       NOR2         B        In      -         6.019       -
    APB_cnt_0.my_counter.Qaux_RNISV4C[3]       NOR2         Y        Out     0.646     6.665       -
    countiszero_25                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNIAO5E1[15]     OR2B         B        In      -         7.849       -
    APB_cnt_0.my_counter.Qaux_RNIAO5E1[15]     OR2B         Y        Out     0.516     8.365       -
    countiszero_29                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNIG8O04[26]     NOR2         A        In      -         9.549       -
    APB_cnt_0.my_counter.Qaux_RNIG8O04[26]     NOR2         Y        Out     0.507     10.056      -
    TIMINT_c                                   Net          -        -       1.423     -           6
    APB_cnt_0.LoadEnReg_RNIRLM34               OR2          A        In      -         11.479      -
    APB_cnt_0.LoadEnReg_RNIRLM34               OR2          Y        Out     0.363     11.842      -
    un1_loaden_cntzero_0                       Net          -        -       2.172     -           16
    APB_cnt_0.my_counter.Qaux_RNO[25]          MX2          S        In      -         14.015      -
    APB_cnt_0.my_counter.Qaux_RNO[25]          MX2          Y        Out     0.480     14.495      -
    Qaux_n25                                   Net          -        -       0.322     -           1
    APB_cnt_0.my_counter.Qaux[25]              DFN1E1C0     D        In      -         14.816      -
    =========================================================================================================
    Total path delay (propagation time + setup) of 15.355 is 5.081(33.1%) logic and 10.273(66.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      14.816
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -5.355

        Number of logic level(s):                7
        Starting point:                          APB_cnt_0.my_counter.Qaux[0] / Q
        Ending point:                            APB_cnt_0.my_counter.Qaux[28] / D
        The start point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                       Type         Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    APB_cnt_0.my_counter.Qaux[0]               DFN1E1C0     Q        Out     0.737     0.737       -
    Count[0]                                   Net          -        -       1.279     -           5
    APB_cnt_0.my_counter.Qaux_RNIPF03[1]       OR2          B        In      -         2.016       -
    APB_cnt_0.my_counter.Qaux_RNIPF03[1]       OR2          Y        Out     0.646     2.663       -
    countiszero_1                              Net          -        -       1.526     -           7
    APB_cnt_0.my_counter.Qaux_RNIMF16[3]       OR2A         B        In      -         4.189       -
    APB_cnt_0.my_counter.Qaux_RNIMF16[3]       OR2A         Y        Out     0.646     4.835       -
    countiszero_17                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNISV4C[3]       NOR2         B        In      -         6.019       -
    APB_cnt_0.my_counter.Qaux_RNISV4C[3]       NOR2         Y        Out     0.646     6.665       -
    countiszero_25                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNIAO5E1[15]     OR2B         B        In      -         7.849       -
    APB_cnt_0.my_counter.Qaux_RNIAO5E1[15]     OR2B         Y        Out     0.516     8.365       -
    countiszero_29                             Net          -        -       1.184     -           4
    APB_cnt_0.my_counter.Qaux_RNIG8O04[26]     NOR2         A        In      -         9.549       -
    APB_cnt_0.my_counter.Qaux_RNIG8O04[26]     NOR2         Y        Out     0.507     10.056      -
    TIMINT_c                                   Net          -        -       1.423     -           6
    APB_cnt_0.LoadEnReg_RNIRLM34               OR2          A        In      -         11.479      -
    APB_cnt_0.LoadEnReg_RNIRLM34               OR2          Y        Out     0.363     11.842      -
    un1_loaden_cntzero_0                       Net          -        -       2.172     -           16
    APB_cnt_0.my_counter.Qaux_RNO[28]          MX2          S        In      -         14.015      -
    APB_cnt_0.my_counter.Qaux_RNO[28]          MX2          Y        Out     0.480     14.495      -
    Qaux_n28                                   Net          -        -       0.322     -           1
    APB_cnt_0.my_counter.Qaux[28]              DFN1E1C0     D        In      -         14.816      -
    =========================================================================================================
    Total path delay (propagation time + setup) of 15.355 is 5.081(33.1%) logic and 10.273(66.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                Starting                                                                             Arrival
    Instance                    Reference     Type        Pin              Net                                       Time        Slack
                                Clock
    ----------------------------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[3]      Z\\CoreAPB3_0_APBmslave0_PADDR_\[3\]\\    0.000       0.575
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[4]      Z\\CoreAPB3_0_APBmslave0_PADDR_\[4\]\\    0.000       1.031
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[0]      Z\\CoreAPB3_0_APBmslave0_PADDR_\[0\]\\    0.000       1.072
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[2]      Z\\CoreAPB3_0_APBmslave0_PADDR_\[2\]\\    0.000       1.105
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[1]      Z\\CoreAPB3_0_APBmslave0_PADDR_\[1\]\\    0.000       1.354
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[8]      Z\\my_mss_0_MSS_MASTER_APB_PADDR_\[8\]\\  0.000       1.955
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPSEL          my_mss_0_MSS_MASTER_APB_PSELx             0.000       1.955
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[11]     Z\\my_mss_0_MSS_MASTER_APB_PADDR_\[11\]\\ 0.000       2.188
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[9]      Z\\my_mss_0_MSS_MASTER_APB_PADDR_\[9\]\\  0.000       2.237
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[10]     Z\\my_mss_0_MSS_MASTER_APB_PADDR_\[10\]\\ 0.000       2.327
    ==================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                  Starting                                           Required
    Instance                      Reference     Type         Pin     Net             Time         Slack
                                  Clock
    ---------------------------------------------------------------------------------------------------
    APB_cnt_0.DataOut_int[6]      System        DFN1E1C0     D       DataOut[6]      9.461        0.575
    APB_cnt_0.DataOut_int[9]      System        DFN1E1C0     D       DataOut[9]      9.461        0.575
    APB_cnt_0.DataOut_int[12]     System        DFN1E1C0     D       DataOut[12]     9.461        0.575
    APB_cnt_0.DataOut_int[14]     System        DFN1E1C0     D       DataOut[14]     9.461        0.575
    APB_cnt_0.DataOut_int[15]     System        DFN1E1C0     D       DataOut[15]     9.461        0.575
    APB_cnt_0.DataOut_int[16]     System        DFN1E1C0     D       DataOut[16]     9.461        0.575
    APB_cnt_0.DataOut_int[17]     System        DFN1E1C0     D       DataOut[17]     9.461        0.575
    APB_cnt_0.DataOut_int[18]     System        DFN1E1C0     D       DataOut[18]     9.461        0.575
    APB_cnt_0.DataOut_int[19]     System        DFN1E1C0     D       DataOut[19]     9.461        0.575
    APB_cnt_0.DataOut_int[21]     System        DFN1E1C0     D       DataOut[21]     9.461        0.575
    ===================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      8.886
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 0.575

        Number of logic level(s):                4
        Starting point:                          my_mss_0.MSS_ADLIB_INST / MSSPADDR[3]
        Ending point:                            APB_cnt_0.DataOut_int[6] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                             Pin             Pin               Arrival     No. of
    Name                                          Type         Name            Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST                       MSS_APB      MSSPADDR[3]     Out     0.000     0.000       -
    Z\\CoreAPB3_0_APBmslave0_PADDR_\[3\]\\        Net          -               -       0.806     -           3
    APB_cnt_0.p_data_out\.un22_pwrite_0_a2_1_0    OR2A         B               In      -         0.806       -
    APB_cnt_0.p_data_out\.un22_pwrite_0_a2_1_0    OR2A         Y               Out     0.646     1.453       -
    un22_pwrite_1                                 Net          -               -       1.184     -           4
    APB_cnt_0.p_data_out\.un22_pwrite_0_a2_0_0    NOR2         A               In      -         2.636       -
    APB_cnt_0.p_data_out\.un22_pwrite_0_a2_0_0    NOR2         Y               Out     0.507     3.144       -
    un22_pwrite_0                                 Net          -               -       2.172     -           16
    APB_cnt_0.DataOut_sn_m2_0                     OR2          B               In      -         5.316       -
    APB_cnt_0.DataOut_sn_m2_0                     OR2          Y               Out     0.514     5.831       -
    N_37_0                                        Net          -               -       2.218     -           17
    APB_cnt_0.DataOut_int_RNO[6]                  NOR2A        A               In      -         8.049       -
    APB_cnt_0.DataOut_int_RNO[6]                  NOR2A        Y               Out     0.516     8.565       -
    DataOut[6]                                    Net          -               -       0.322     -           1
    APB_cnt_0.DataOut_int[6]                      DFN1E1C0     D               In      -         8.886       -
    ===================================================================================================================
    Total path delay (propagation time + setup) of 9.425 is 2.723(28.9%) logic and 6.702(71.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    --------------------------------------------------------------------------------
    Target Part: A2F200M3F_FBGA256_Std
    Report for cell Top.def_arch
      Core Cell usage:
                  cell count     area count*area
                   AX1     2      1.0        2.0
                  AX1A     1      1.0        1.0
                  AX1B     9      1.0        9.0
                  AX1C     3      1.0        3.0
                  BUFF     4      1.0        4.0
                   GND     7      0.0        0.0
               MSS_APB     1      0.0        0.0
               MSS_CCC     1      0.0        0.0
                   MX2    30      1.0       30.0
                  MX2B     1      1.0        1.0
                  MX2C    35      1.0       35.0
                  NOR2    21      1.0       21.0
                 NOR2A    33      1.0       33.0
                 NOR2B     1      1.0        1.0
                  NOR3     5      1.0        5.0
                 NOR3A    11      1.0       11.0
                 NOR3B     8      1.0        8.0
                 NOR3C    40      1.0       40.0
                   OR2    12      1.0       12.0
                  OR2A     5      1.0        5.0
                  OR2B     3      1.0        3.0
                   OR3     3      1.0        3.0
                  OR3B     1      1.0        1.0
                  OR3C     2      1.0        2.0
                 RCOSC     1      0.0        0.0
                   VCC     7      0.0        0.0
                 XNOR2    14      1.0       14.0
                   XO1     1      1.0        1.0
                  XOR2     3      1.0        3.0

              DFN1E1C0    98      1.0       98.0
                       -----          ----------
                 TOTAL   363               346.0

      IO Cell usage:
                  cell count
             INBUF_MSS     1
                OUTBUF     2
                       -----
                 TOTAL     3

    Core Cells         : 346 of 4608 (8%)
    IO Cells           : 3 of 66 (5%)

      RAM/ROM Usage Summary
    Block Rams : 0 of 8 (0%)

    Mapper successful!
    Process took 0h:00m:04s realtime, 0h:00m:04s cputime
    # Wed Feb 10 09:42:32 2010

    ###########################################################]

`