`

    #Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010
    #install: D:\Software\Libero\Libero_v90\Libero_v9.0\Synopsys\synplify_D200912A
    #OS: Windows XP 5.1
    #Hostname: WXP-ALIMS

    #Implementation: synthesis

    #Wed Mar 10 11:50:35 2010

    $ Start of Compile
    #Wed Mar 10 11:50:35 2010

    Synopsys Verilog Compiler, version comp475rc, Build 060R, built Jan 15 2010
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

    @I::"D:\Software\Libero\Libero_v90\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\smartfusion.v"
    @I::"D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_mem_nw\component\Actel\DirectCore\CoreAPB3\2.1.101\rtl\verilog\o\MuxPtoB3.v"
    @I::"D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_mem_nw\component\Actel\DirectCore\CoreAPB3\2.1.101\rtl\verilog\o\CoreAPB3.v"
    @I::"D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_mem_nw\component\Actel\SmartFusionMSS\MSS\1.0.101\mss_comps.v"
    @I::"D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_mem_nw\component\work\my_mss\MSS_CCC_0\my_mss_tmp_MSS_CCC_0_MSS_CCC.v"
    @I::"D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_mem_nw\component\work\my_mss\my_mss.v"
    @I::"D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_mem_nw\hdl\reg32x8.v"
    @I::"D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_mem_nw\hdl\reg_apb_wrp.v"
    @I::"D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_mem_nw\component\work\Top\Top.v"
    Verilog syntax check successful!
    Options changed - recompiling
    Selecting top level module Top
    @N:CG364 : MuxPtoB3.v(3) | Synthesizing module CoreAPB3_ll0

    @N:CG364 : CoreAPB3.v(3) | Synthesizing module CoreAPB3

    	ApbSlot0Enable=32'b00000000000000000000000000000001
    	ApbSlot1Enable=32'b00000000000000000000000000000001
    	ApbSlot2Enable=32'b00000000000000000000000000000001
    	ApbSlot3Enable=32'b00000000000000000000000000000001
    	ApbSlot4Enable=32'b00000000000000000000000000000001
    	ApbSlot5Enable=32'b00000000000000000000000000000001
    	ApbSlot6Enable=32'b00000000000000000000000000000001
    	ApbSlot7Enable=32'b00000000000000000000000000000001
    	ApbSlot8Enable=32'b00000000000000000000000000000001
    	ApbSlot9Enable=32'b00000000000000000000000000000001
    	ApbSlot10Enable=32'b00000000000000000000000000000001
    	ApbSlot11Enable=32'b00000000000000000000000000000001
    	ApbSlot12Enable=32'b00000000000000000000000000000001
    	ApbSlot13Enable=32'b00000000000000000000000000000001
    	ApbSlot14Enable=32'b00000000000000000000000000000001
    	ApbSlot15Enable=32'b00000000000000000000000000000001
    	RangeSize=32'b00000000000000000000000100000000
       Generated name = CoreAPB3_Z1

    @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC

    @N:CG364 : mss_comps.v(12) | Synthesizing module INBUF_MSS

    @N:CG364 : mss_comps.v(26) | Synthesizing module OUTBUF_MSS

    @N:CG364 : mss_comps.v(139) | Synthesizing module MSS_CCC

    @N:CG364 : smartfusion.v(2566) | Synthesizing module RCOSC

    @N:CG364 : smartfusion.v(1133) | Synthesizing module GND

    @N:CG364 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module my_mss_tmp_MSS_CCC_0_MSS_CCC

    @N:CG364 : mss_comps.v(668) | Synthesizing module MSS_APB

    @N:CG364 : my_mss.v(5) | Synthesizing module my_mss

    @N:CG364 : reg32x8.v(4) | Synthesizing module reg16x8

    @A:CL106 : reg32x8.v(35) | Register mem_0_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_1_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_2_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_3_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_4_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_5_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_6_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_7_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_8_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_9_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_10_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_11_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_12_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_13_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_14_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg32x8.v(35) | Register mem_15_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @N:CG364 : reg_apb_wrp.v(21) | Synthesizing module reg_apb_wrp

    @N:CG364 : Top.v(5) | Synthesizing module Top

    @W:CL246 : reg_apb_wrp.v(35) | Input port bits 7 to 6 of PADDR[7:0] are unused

    @W:CL246 : reg_apb_wrp.v(35) | Input port bits 1 to 0 of PADDR[7:0] are unused

    @W:CL157 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(38) | *Output FAB_LOCK has undriven bits - a simulation mismatch is possible
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(25) | Input CLKA is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(26) | Input CLKA_PAD is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(27) | Input CLKA_PADP is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(28) | Input CLKA_PADN is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(29) | Input MAINXIN is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(30) | Input CLKC is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(31) | Input CLKC_PAD is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(32) | Input CLKC_PADP is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(33) | Input CLKC_PADN is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(34) | Input FB_CLK is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(35) | Input MAC_CLK is unused
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Mar 10 11:50:38 2010

    ###########################################################]
    Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
    Product Version D-2009.12A
    @N:MF249 :  | Running in 32-bit mode.
    @N:MF258 :  | Gated clock conversion disabled

    @W:MO111 : my_mss_tmp_mss_ccc_0_mss_ccc.v(38) | tristate driver FAB_LOCK on net FAB_LOCK has its enable tied to GND (module my_mss_tmp_MSS_CCC_0_MSS_CCC)
    Automatic dissolve at startup in view:work.my_mss(verilog) of MSS_CCC_0(my_mss_tmp_MSS_CCC_0_MSS_CCC)
    Automatic dissolve at startup in view:work.Top(verilog) of my_mss_0(my_mss)
    Automatic dissolve at startup in view:work.Top(verilog) of CoreAPB3_0(CoreAPB3_Z1)

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB)

    @N:MO106 : coreapb3.v(1393) | Found ROM, 'CoreAPB3_0.CoreAPB3_OI0_2[15:0]', 16 words by 16 bits
    Automatic dissolve during optimization of view:work.Top(verilog) of reg_apb_wrp_0(reg_apb_wrp)
    Auto Dissolve of CoreAPB3_0.CoreAPB3_O00 (inst of view:work.CoreAPB3_ll0(verilog))
    Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 60MB)

    Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 60MB)

    Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB)

    Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB)

    Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 60MB)

    Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 60MB)

    Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 60MB)

    High Fanout Net Report
    **********************

    Driver Instance / Pin Name                Fanout, notes
    ------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST / M2FRESETn       264 : 8 asynchronous set/reset
    my_mss_0.MSS_ADLIB_INST / MSSPADDR[4]     48
    my_mss_0.MSS_ADLIB_INST / MSSPADDR[5]     80
    ========================================================================

    Buffering my_mss_0_FAB_CLK, fanout 137 segments 6
    Buffering my_mss_0_FAB_CLK, fanout 27 segments 2
    Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB)

    Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB)

    Added 6 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication
    Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB)

    Writing Analyst data base D:\Appsnotes\2010\Custom_APB\Design\Cap_15_design\APB_slv_mem_nw\synthesis\Top.srm
    Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 62MB)

    Writing EDIF Netlist and constraint files
    D-2009.12A
    Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB)

    @W:MT420 :  | Found inferred clock Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:my_mss_0_FAB_CLK"

    @W:MT246 : my_mss.v(53) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed Mar 10 11:50:48 2010
    #

    Top view:               Top
    Library name:           smartfusion
    Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Wire load model:        smartfusion
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing..

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock..

    Performance Summary
    *******************

    Worst slack in design: -2.957

                                                               Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock                                             Frequency     Frequency     Period        Period        Slack     Type         Group
    -------------------------------------------------------------------------------------------------------------------------------------------------------------
    Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     100.0 MHz     142.5 MHz     10.000        7.019         2.981     inferred     Inferred_clkgroup_0
    System                                                     100.0 MHz     181.5 MHz     10.000        5.509         4.491     system       default_clkgroup
    =============================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                                          |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                                Ending                                                  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock  Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock  |  10.000      2.981  |  No paths    -      |  No paths    -      |  No paths    -
    ======================================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    		No IO constraint found

    ====================================
    Detailed Report for Clock: Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                           Starting                                                                                       Arrival
    Instance                               Reference                                                  Type         Pin     Net            Time        Slack
                                           Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------
    reg_apb_wrp_0.reg16x8_0.mem_5_[0]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[0]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[1]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[1]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[2]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[2]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[3]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[3]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[4]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[4]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[5]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[5]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[6]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[6]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[7]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[7]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_10_[0]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_10_[0]     1.677       2.986
    reg_apb_wrp_0.reg16x8_0.mem_10_[1]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_10_[1]     1.677       2.986
    =======================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                            Starting                                                                                          Required
    Instance                                Reference                                                  Type         Pin     Net               Time         Slack
                                            Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------
    reg_apb_wrp_0.reg16x8_0.data_out[0]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       data_out_2[0]     9.496        2.981
    reg_apb_wrp_0.reg16x8_0.data_out[1]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       data_out_2[1]     9.496        2.981
    reg_apb_wrp_0.reg16x8_0.data_out[2]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       data_out_2[2]     9.496        2.981
    reg_apb_wrp_0.reg16x8_0.data_out[3]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       data_out_2[3]     9.496        2.981
    reg_apb_wrp_0.reg16x8_0.data_out[4]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       data_out_2[4]     9.496        2.981
    reg_apb_wrp_0.reg16x8_0.data_out[5]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       data_out_2[5]     9.496        2.981
    reg_apb_wrp_0.reg16x8_0.data_out[6]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       data_out_2[6]     9.496        2.981
    reg_apb_wrp_0.reg16x8_0.data_out[7]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     D       data_out_2[7]     9.496        2.981
    reg_apb_wrp_0.reg16x8_0.mem_0_[0]       Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     D       mem_0__4[0]       7.301        3.533
    reg_apb_wrp_0.reg16x8_0.mem_0_[1]       Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     D       mem_0__4[1]       7.301        3.533
    ============================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.504
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.496

        - Propagation time:                      6.516
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 2.981

        Number of logic level(s):                4
        Starting point:                          reg_apb_wrp_0.reg16x8_0.mem_5_[0] / Q
        Ending point:                            reg_apb_wrp_0.reg16x8_0.data_out[0] / D
        The start point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                              Pin      Pin               Arrival     No. of
    Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------
    reg_apb_wrp_0.reg16x8_0.mem_5_[0]              DFN1P1C1     Q        Out     1.717     1.717       -
    mem_5_[0]                                      Net          -        -       1.184     -           4
    reg_apb_wrp_0.reg16x8_0.data_out_RNO_11[0]     MX2C         A        In      -         2.901       -
    reg_apb_wrp_0.reg16x8_0.data_out_RNO_11[0]     MX2C         Y        Out     0.579     3.479       -
    N_9                                            Net          -        -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.data_out_RNO_4[0]      MX2C         B        In      -         3.801       -
    reg_apb_wrp_0.reg16x8_0.data_out_RNO_4[0]      MX2C         Y        Out     0.586     4.387       -
    N_10                                           Net          -        -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.data_out_RNO_1[0]      MX2C         A        In      -         4.708       -
    reg_apb_wrp_0.reg16x8_0.data_out_RNO_1[0]      MX2C         Y        Out     0.579     5.287       -
    N_14                                           Net          -        -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.data_out_RNO[0]        MX2C         B        In      -         5.608       -
    reg_apb_wrp_0.reg16x8_0.data_out_RNO[0]        MX2C         Y        Out     0.586     6.194       -
    data_out_2[0]                                  Net          -        -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.data_out[0]            DFN1E1C0     D        In      -         6.516       -
    =============================================================================================================
    Total path delay (propagation time + setup) of 7.019 is 4.550(64.8%) logic and 2.470(35.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                Starting                                                                          Arrival
    Instance                    Reference     Type        Pin              Net                                    Time        Slack
                                Clock
    --------------------------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[3]      my_mss_0_MSS_MASTER_APB_PADDR_\[3\]    0.000       -2.957
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[2]      my_mss_0_MSS_MASTER_APB_PADDR_\[2\]    0.000       -2.597
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[5]      my_mss_0_MSS_MASTER_APB_PADDR_\[5\]    0.000       -2.317
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[4]      my_mss_0_MSS_MASTER_APB_PADDR_\[4\]    0.000       -1.832
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[8]      my_mss_0_MSS_MASTER_APB_PADDR_\[8\]    0.000       -1.305
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPSEL          my_mss_0_MSS_MASTER_APB_PSELx          0.000       -1.253
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[11]     my_mss_0_MSS_MASTER_APB_PADDR_\[11\]   0.000       -1.137
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[9]      my_mss_0_MSS_MASTER_APB_PADDR_\[9\]    0.000       -1.078
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[10]     my_mss_0_MSS_MASTER_APB_PADDR_\[10\]   0.000       -0.998
    my_mss_0.MSS_ADLIB_INST     System        MSS_APB     MSSPENABLE       CoreAPB3_0_APBmslave0_PENABLE          0.000       1.077
    ================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                          Starting                                           Required
    Instance                              Reference     Type         Pin     Net             Time         Slack
                                          Clock
    ------------------------------------------------------------------------------------------------------------
    reg_apb_wrp_0.reg16x8_0.mem_1_[0]     System        DFN1P1C1     D       mem_1__4[0]     7.301        -2.957
    reg_apb_wrp_0.reg16x8_0.mem_1_[1]     System        DFN1P1C1     D       mem_1__4[1]     7.301        -2.957
    reg_apb_wrp_0.reg16x8_0.mem_1_[2]     System        DFN1P1C1     D       mem_1__4[2]     7.301        -2.957
    reg_apb_wrp_0.reg16x8_0.mem_1_[3]     System        DFN1P1C1     D       mem_1__4[3]     7.301        -2.957
    reg_apb_wrp_0.reg16x8_0.mem_1_[4]     System        DFN1P1C1     D       mem_1__4[4]     7.301        -2.957
    reg_apb_wrp_0.reg16x8_0.mem_1_[5]     System        DFN1P1C1     D       mem_1__4[5]     7.301        -2.957
    reg_apb_wrp_0.reg16x8_0.mem_1_[6]     System        DFN1P1C1     D       mem_1__4[6]     7.301        -2.957
    reg_apb_wrp_0.reg16x8_0.mem_1_[7]     System        DFN1P1C1     D       mem_1__4[7]     7.301        -2.957
    reg_apb_wrp_0.reg16x8_0.mem_5_[0]     System        DFN1P1C1     D       mem_5__4[0]     7.301        -2.922
    reg_apb_wrp_0.reg16x8_0.mem_5_[1]     System        DFN1P1C1     D       mem_5__4[1]     7.301        -2.922
    ============================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            2.699
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         7.301

        - Propagation time:                      10.258
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -2.957

        Number of logic level(s):                4
        Starting point:                          my_mss_0.MSS_ADLIB_INST / MSSPADDR[3]
        Ending point:                            reg_apb_wrp_0.reg16x8_0.mem_1_[0] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                           Pin             Pin               Arrival     No. of
    Name                                        Type         Name            Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST                     MSS_APB      MSSPADDR[3]     Out     0.000     0.000       -
    my_mss_0_MSS_MASTER_APB_PADDR_\[3\]         Net          -               -       2.353     -           20
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0_1      OR2A         B               In      -         2.353       -
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0_1      OR2A         Y               Out     0.646     3.000       -
    un1_addr_1[9]                               Net          -               -       1.184     -           4
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0        NOR3         C               In      -         4.183       -
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0        NOR3         Y               Out     0.751     4.934       -
    un1_addr[1]                                 Net          -               -       2.218     -           17
    reg_apb_wrp_0.reg16x8_0.mem_1__1_sqmuxa     OR3C         C               In      -         7.152       -
    reg_apb_wrp_0.reg16x8_0.mem_1__1_sqmuxa     OR3C         Y               Out     0.666     7.817       -
    mem_1__1_sqmuxa                             Net          -               -       1.639     -           8
    reg_apb_wrp_0.reg16x8_0.mem_1__RNO_0[0]     MX2          S               In      -         9.456       -
    reg_apb_wrp_0.reg16x8_0.mem_1__RNO_0[0]     MX2          Y               Out     0.480     9.936       -
    mem_1__4[0]                                 Net          -               -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.mem_1_[0]           DFN1P1C1     D               In      -         10.258      -
    =================================================================================================================
    Total path delay (propagation time + setup) of 12.957 is 5.242(40.5%) logic and 7.715(59.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      10.000
        - Setup time:                            2.699
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         7.301

        - Propagation time:                      10.258
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -2.957

        Number of logic level(s):                4
        Starting point:                          my_mss_0.MSS_ADLIB_INST / MSSPADDR[3]
        Ending point:                            reg_apb_wrp_0.reg16x8_0.mem_1_[1] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                           Pin             Pin               Arrival     No. of
    Name                                        Type         Name            Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST                     MSS_APB      MSSPADDR[3]     Out     0.000     0.000       -
    my_mss_0_MSS_MASTER_APB_PADDR_\[3\]         Net          -               -       2.353     -           20
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0_1      OR2A         B               In      -         2.353       -
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0_1      OR2A         Y               Out     0.646     3.000       -
    un1_addr_1[9]                               Net          -               -       1.184     -           4
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0        NOR3         C               In      -         4.183       -
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0        NOR3         Y               Out     0.751     4.934       -
    un1_addr[1]                                 Net          -               -       2.218     -           17
    reg_apb_wrp_0.reg16x8_0.mem_1__1_sqmuxa     OR3C         C               In      -         7.152       -
    reg_apb_wrp_0.reg16x8_0.mem_1__1_sqmuxa     OR3C         Y               Out     0.666     7.817       -
    mem_1__1_sqmuxa                             Net          -               -       1.639     -           8
    reg_apb_wrp_0.reg16x8_0.mem_1__RNO_0[1]     MX2          S               In      -         9.456       -
    reg_apb_wrp_0.reg16x8_0.mem_1__RNO_0[1]     MX2          Y               Out     0.480     9.936       -
    mem_1__4[1]                                 Net          -               -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.mem_1_[1]           DFN1P1C1     D               In      -         10.258      -
    =================================================================================================================
    Total path delay (propagation time + setup) of 12.957 is 5.242(40.5%) logic and 7.715(59.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      10.000
        - Setup time:                            2.699
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         7.301

        - Propagation time:                      10.258
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -2.957

        Number of logic level(s):                4
        Starting point:                          my_mss_0.MSS_ADLIB_INST / MSSPADDR[3]
        Ending point:                            reg_apb_wrp_0.reg16x8_0.mem_1_[2] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                           Pin             Pin               Arrival     No. of
    Name                                        Type         Name            Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST                     MSS_APB      MSSPADDR[3]     Out     0.000     0.000       -
    my_mss_0_MSS_MASTER_APB_PADDR_\[3\]         Net          -               -       2.353     -           20
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0_1      OR2A         B               In      -         2.353       -
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0_1      OR2A         Y               Out     0.646     3.000       -
    un1_addr_1[9]                               Net          -               -       1.184     -           4
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0        NOR3         C               In      -         4.183       -
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0        NOR3         Y               Out     0.751     4.934       -
    un1_addr[1]                                 Net          -               -       2.218     -           17
    reg_apb_wrp_0.reg16x8_0.mem_1__1_sqmuxa     OR3C         C               In      -         7.152       -
    reg_apb_wrp_0.reg16x8_0.mem_1__1_sqmuxa     OR3C         Y               Out     0.666     7.817       -
    mem_1__1_sqmuxa                             Net          -               -       1.639     -           8
    reg_apb_wrp_0.reg16x8_0.mem_1__RNO_0[2]     MX2          S               In      -         9.456       -
    reg_apb_wrp_0.reg16x8_0.mem_1__RNO_0[2]     MX2          Y               Out     0.480     9.936       -
    mem_1__4[2]                                 Net          -               -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.mem_1_[2]           DFN1P1C1     D               In      -         10.258      -
    =================================================================================================================
    Total path delay (propagation time + setup) of 12.957 is 5.242(40.5%) logic and 7.715(59.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      10.000
        - Setup time:                            2.699
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         7.301

        - Propagation time:                      10.258
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -2.957

        Number of logic level(s):                4
        Starting point:                          my_mss_0.MSS_ADLIB_INST / MSSPADDR[3]
        Ending point:                            reg_apb_wrp_0.reg16x8_0.mem_1_[3] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                           Pin             Pin               Arrival     No. of
    Name                                        Type         Name            Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST                     MSS_APB      MSSPADDR[3]     Out     0.000     0.000       -
    my_mss_0_MSS_MASTER_APB_PADDR_\[3\]         Net          -               -       2.353     -           20
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0_1      OR2A         B               In      -         2.353       -
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0_1      OR2A         Y               Out     0.646     3.000       -
    un1_addr_1[9]                               Net          -               -       1.184     -           4
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0        NOR3         C               In      -         4.183       -
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0        NOR3         Y               Out     0.751     4.934       -
    un1_addr[1]                                 Net          -               -       2.218     -           17
    reg_apb_wrp_0.reg16x8_0.mem_1__1_sqmuxa     OR3C         C               In      -         7.152       -
    reg_apb_wrp_0.reg16x8_0.mem_1__1_sqmuxa     OR3C         Y               Out     0.666     7.817       -
    mem_1__1_sqmuxa                             Net          -               -       1.639     -           8
    reg_apb_wrp_0.reg16x8_0.mem_1__RNO_0[3]     MX2          S               In      -         9.456       -
    reg_apb_wrp_0.reg16x8_0.mem_1__RNO_0[3]     MX2          Y               Out     0.480     9.936       -
    mem_1__4[3]                                 Net          -               -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.mem_1_[3]           DFN1P1C1     D               In      -         10.258      -
    =================================================================================================================
    Total path delay (propagation time + setup) of 12.957 is 5.242(40.5%) logic and 7.715(59.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      10.000
        - Setup time:                            2.699
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         7.301

        - Propagation time:                      10.258
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -2.957

        Number of logic level(s):                4
        Starting point:                          my_mss_0.MSS_ADLIB_INST / MSSPADDR[3]
        Ending point:                            reg_apb_wrp_0.reg16x8_0.mem_1_[4] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                           Pin             Pin               Arrival     No. of
    Name                                        Type         Name            Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST                     MSS_APB      MSSPADDR[3]     Out     0.000     0.000       -
    my_mss_0_MSS_MASTER_APB_PADDR_\[3\]         Net          -               -       2.353     -           20
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0_1      OR2A         B               In      -         2.353       -
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0_1      OR2A         Y               Out     0.646     3.000       -
    un1_addr_1[9]                               Net          -               -       1.184     -           4
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0        NOR3         C               In      -         4.183       -
    reg_apb_wrp_0.reg16x8_0.un1_addr_1_0        NOR3         Y               Out     0.751     4.934       -
    un1_addr[1]                                 Net          -               -       2.218     -           17
    reg_apb_wrp_0.reg16x8_0.mem_1__1_sqmuxa     OR3C         C               In      -         7.152       -
    reg_apb_wrp_0.reg16x8_0.mem_1__1_sqmuxa     OR3C         Y               Out     0.666     7.817       -
    mem_1__1_sqmuxa                             Net          -               -       1.639     -           8
    reg_apb_wrp_0.reg16x8_0.mem_1__RNO_0[4]     MX2          S               In      -         9.456       -
    reg_apb_wrp_0.reg16x8_0.mem_1__RNO_0[4]     MX2          Y               Out     0.480     9.936       -
    mem_1__4[4]                                 Net          -               -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.mem_1_[4]           DFN1P1C1     D               In      -         10.258      -
    =================================================================================================================
    Total path delay (propagation time + setup) of 12.957 is 5.242(40.5%) logic and 7.715(59.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    --------------------------------------------------------------------------------
    Target Part: A2F200M3F_FBGA256_Std
    Report for cell Top.verilog
      Core Cell usage:
                  cell count     area count*area
                  BUFF     6      1.0        6.0
                   GND     7      0.0        0.0
               MSS_APB     1      0.0        0.0
               MSS_CCC     1      0.0        0.0
                   MX2   128      1.0      128.0
                  MX2C   120      1.0      120.0
                  NOR2     1      1.0        1.0
                  NOR3     4      1.0        4.0
                 NOR3A   137      1.0      137.0
                 NOR3B     5      1.0        5.0
                 NOR3C     9      1.0        9.0
                  OA1C   128      1.0      128.0
                   OR2     1      1.0        1.0
                  OR2A     2      1.0        2.0
                  OR2B     1      1.0        1.0
                  OR3C    16      1.0       16.0
                 RCOSC     1      0.0        0.0
                   VCC     7      0.0        0.0

              DFN1E1C0     8      1.0        8.0
              DFN1P1C1   128      1.0      128.0
                       -----          ----------
                 TOTAL   711               694.0

      IO Cell usage:
                  cell count
             INBUF_MSS     2
            OUTBUF_MSS     1
                       -----
                 TOTAL     3

    Core Cells         : 694 of 4608 (15%)
    IO Cells           : 3 of 66 (5%)

      RAM/ROM Usage Summary
    Block Rams : 0 of 8 (0%)

    Mapper successful!
    Process took 0h:00m:03s realtime, 0h:00m:01s cputime
    # Wed Mar 10 11:50:48 2010

    ###########################################################]

`