#-- Synopsys, Inc.
#-- Version D-2009.12A
#-- Project file D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\synthesis\run_options.txt
#-- Written on Wed Mar 03 16:46:44 2010


#project files
add_file -verilog "D:/Appsnotes/2010/User_Logic_to_MSS/design_files/User_Logic_MSS_DF_new/apb_with_wait/component/Actel/DirectCore/CoreAPB3/2.1.101/rtl/verilog/o/MuxPtoB3.v"
add_file -verilog "D:/Appsnotes/2010/User_Logic_to_MSS/design_files/User_Logic_MSS_DF_new/apb_with_wait/component/Actel/DirectCore/CoreAPB3/2.1.101/rtl/verilog/o/CoreAPB3.v"
add_file -verilog "D:/Appsnotes/2010/User_Logic_to_MSS/design_files/User_Logic_MSS_DF_new/apb_with_wait/component/Actel/SmartFusionMSS/MSS/1.0.101/mss_comps.v"
add_file -verilog "D:/Appsnotes/2010/User_Logic_to_MSS/design_files/User_Logic_MSS_DF_new/apb_with_wait/component/work/my_mss/MSS_CCC_0/my_mss_tmp_MSS_CCC_0_MSS_CCC.v"
add_file -verilog "D:/Appsnotes/2010/User_Logic_to_MSS/design_files/User_Logic_MSS_DF_new/apb_with_wait/component/work/my_mss/my_mss.v"
add_file -verilog "D:/Appsnotes/2010/User_Logic_to_MSS/design_files/User_Logic_MSS_DF_new/apb_with_wait/hdl/reg16x8.v"
add_file -verilog "D:/Appsnotes/2010/User_Logic_to_MSS/design_files/User_Logic_MSS_DF_new/apb_with_wait/hdl/reg_apb_wrp.v"
add_file -verilog "D:/Appsnotes/2010/User_Logic_to_MSS/design_files/User_Logic_MSS_DF_new/apb_with_wait/component/work/Top/Top.v"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion
set_option -part A2F200M3F
set_option -package FBGA256
set_option -speed_grade Std
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "Top"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0

# Actel 500K
set_option -run_prop_extract 1
set_option -maxfan 24
set_option -maxfan_hard3 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 0
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0

# Actel 500K
set_option -globalthreshold 50

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./Top.edn"
impl -active "synthesis"
