`

    #Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010
    #install: D:\Software\Libero\Libero_v90\Libero_v9.0\Synopsys\synplify_D200912A
    #OS: Windows XP 5.1
    #Hostname: WXP-ALIMS

    #Implementation: synthesis

    #Wed Mar 03 16:46:44 2010

    $ Start of Compile
    #Wed Mar 03 16:46:44 2010

    Synopsys Verilog Compiler, version comp475rc, Build 060R, built Jan 15 2010
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

    @I::"D:\Software\Libero\Libero_v90\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\smartfusion.v"
    @I::"D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\component\Actel\DirectCore\CoreAPB3\2.1.101\rtl\verilog\o\MuxPtoB3.v"
    @I::"D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\component\Actel\DirectCore\CoreAPB3\2.1.101\rtl\verilog\o\CoreAPB3.v"
    @I::"D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\component\Actel\SmartFusionMSS\MSS\1.0.101\mss_comps.v"
    @I::"D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\component\work\my_mss\MSS_CCC_0\my_mss_tmp_MSS_CCC_0_MSS_CCC.v"
    @I::"D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\component\work\my_mss\my_mss.v"
    @I::"D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\hdl\reg16x8.v"
    @I::"D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\hdl\reg_apb_wrp.v"
    @I::"D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\component\work\Top\Top.v"
    Verilog syntax check successful!
    File D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\component\Actel\DirectCore\CoreAPB3\2.1.101\rtl\verilog\o\MuxPtoB3.v changed - recompiling
    File D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\component\Actel\DirectCore\CoreAPB3\2.1.101\rtl\verilog\o\CoreAPB3.v changed - recompiling
    File D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\component\Actel\SmartFusionMSS\MSS\1.0.101\mss_comps.v changed - recompiling
    File D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\component\work\my_mss\MSS_CCC_0\my_mss_tmp_MSS_CCC_0_MSS_CCC.v changed - recompiling
    File D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\component\work\my_mss\my_mss.v changed - recompiling
    File D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\hdl\reg_apb_wrp.v changed - recompiling
    File D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\component\work\Top\Top.v changed - recompiling
    Selecting top level module Top
    @N:CG364 : MuxPtoB3.v(3) | Synthesizing module CoreAPB3_ll0

    @N:CG364 : CoreAPB3.v(3) | Synthesizing module CoreAPB3

    	ApbSlot0Enable=32'b00000000000000000000000000000001
    	ApbSlot1Enable=32'b00000000000000000000000000000001
    	ApbSlot2Enable=32'b00000000000000000000000000000001
    	ApbSlot3Enable=32'b00000000000000000000000000000001
    	ApbSlot4Enable=32'b00000000000000000000000000000001
    	ApbSlot5Enable=32'b00000000000000000000000000000001
    	ApbSlot6Enable=32'b00000000000000000000000000000001
    	ApbSlot7Enable=32'b00000000000000000000000000000001
    	ApbSlot8Enable=32'b00000000000000000000000000000001
    	ApbSlot9Enable=32'b00000000000000000000000000000001
    	ApbSlot10Enable=32'b00000000000000000000000000000001
    	ApbSlot11Enable=32'b00000000000000000000000000000001
    	ApbSlot12Enable=32'b00000000000000000000000000000001
    	ApbSlot13Enable=32'b00000000000000000000000000000001
    	ApbSlot14Enable=32'b00000000000000000000000000000001
    	ApbSlot15Enable=32'b00000000000000000000000000000001
    	RangeSize=32'b00000000000000000000000100000000
       Generated name = CoreAPB3_Z1

    @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC

    @N:CG364 : mss_comps.v(12) | Synthesizing module INBUF_MSS

    @N:CG364 : mss_comps.v(26) | Synthesizing module OUTBUF_MSS

    @N:CG364 : mss_comps.v(139) | Synthesizing module MSS_CCC

    @N:CG364 : smartfusion.v(2566) | Synthesizing module RCOSC

    @N:CG364 : smartfusion.v(1133) | Synthesizing module GND

    @N:CG364 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module my_mss_tmp_MSS_CCC_0_MSS_CCC

    @N:CG364 : mss_comps.v(668) | Synthesizing module MSS_APB

    @N:CG364 : my_mss.v(5) | Synthesizing module my_mss

    @N:CG364 : reg16x8.v(4) | Synthesizing module reg16x8

    @A:CL106 : reg16x8.v(26) | Register mem_0_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_1_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_2_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_3_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_4_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_5_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_6_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_7_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_8_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_9_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_10_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_11_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_12_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_13_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_14_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @A:CL106 : reg16x8.v(26) | Register mem_15_ with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible.
    @N:CG364 : reg_apb_wrp.v(20) | Synthesizing module reg_apb_wrp

    @W:CS149 : reg_apb_wrp.v(112) | Port width mismatch for port addr.  Formal has width 4, Actual 8
    @N:CG364 : Top.v(5) | Synthesizing module Top

    @N:CL201 : reg_apb_wrp.v(46) | Trying to extract state machine for register fsm
    Extracted state machine for register fsm
    State machine has 4 reachable states with original encodings of:
       00
       01
       10
       11
    @W:CL246 : reg_apb_wrp.v(34) | Input port bits 7 to 4 of PADDR[7:0] are unused

    @W:CL159 : reg_apb_wrp.v(33) | Input PENABLE is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(25) | Input CLKA is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(26) | Input CLKA_PAD is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(27) | Input CLKA_PADP is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(28) | Input CLKA_PADN is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(29) | Input MAINXIN is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(30) | Input CLKC is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(31) | Input CLKC_PAD is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(32) | Input CLKC_PADP is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(33) | Input CLKC_PADN is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(34) | Input FB_CLK is unused
    @W:CL159 : my_mss_tmp_MSS_CCC_0_MSS_CCC.v(35) | Input MAC_CLK is unused
    @END
    Process took 0h:00m:02s realtime, 0h:00m:01s cputime
    # Wed Mar 03 16:46:47 2010

    ###########################################################]
    Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
    Product Version D-2009.12A
    @N:MF249 :  | Running in 32-bit mode.
    @N:MF258 :  | Gated clock conversion disabled

    Automatic dissolve at startup in view:work.my_mss(verilog) of MSS_CCC_0(my_mss_tmp_MSS_CCC_0_MSS_CCC)
    Automatic dissolve at startup in view:work.Top(verilog) of my_mss_0(my_mss)
    Automatic dissolve at startup in view:work.Top(verilog) of CoreAPB3_0(CoreAPB3_Z1)

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB)

    @N:MO106 : coreapb3.v(1393) | Found ROM, 'CoreAPB3_0.CoreAPB3_OI0_2[15:0]', 16 words by 16 bits
    Encoding state machine work.reg_apb_wrp(verilog)-fsm[3:0]
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11
    Automatic dissolve during optimization of view:work.Top(verilog) of reg_apb_wrp_0(reg_apb_wrp)
    Auto Dissolve of CoreAPB3_0.CoreAPB3_O00 (inst of view:work.CoreAPB3_ll0(verilog))
    Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 60MB)

    Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 60MB)

    Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 60MB)

    Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 60MB)

    Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 60MB)

    Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 60MB)

    Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 60MB)

    High Fanout Net Report
    **********************

    Driver Instance / Pin Name                Fanout, notes
    -------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST / M2FRESETn       269 : 13 asynchronous set/reset
    my_mss_0.MSS_ADLIB_INST / MSSPADDR[2]     36
    my_mss_0.MSS_ADLIB_INST / MSSPADDR[3]     68
    =========================================================================

    Buffering my_mss_0_FAB_CLK, fanout 150 segments 7
    Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 62MB peak: 63MB)

    Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 62MB peak: 63MB)

    Added 6 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication
    Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 62MB peak: 63MB)

    Writing Analyst data base D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\apb_with_wait\synthesis\Top.srm
    Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 63MB)

    Writing EDIF Netlist and constraint files
    D-2009.12A
    Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 62MB peak: 63MB)

    @W:MT420 :  | Found inferred clock Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:my_mss_0_FAB_CLK"

    @W:MT246 : my_mss.v(53) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed Mar 03 16:46:55 2010
    #

    Top view:               Top
    Library name:           smartfusion
    Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Wire load model:        smartfusion
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing..

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock..

    Performance Summary
    *******************

    Worst slack in design: -3.640

                                                               Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock                                             Frequency     Frequency     Period        Period        Slack     Type         Group
    -------------------------------------------------------------------------------------------------------------------------------------------------------------
    Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     100.0 MHz     116.8 MHz     10.000        8.563         1.437     inferred     Inferred_clkgroup_0
    System                                                     100.0 MHz     171.5 MHz     10.000        5.831         4.169     system       default_clkgroup
    =============================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                                          |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                                Ending                                                  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock  Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock  |  10.000      1.437  |  No paths    -      |  No paths    -      |  No paths    -
    ======================================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    		No IO constraint found

    ====================================
    Detailed Report for Clock: Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                           Starting                                                                                       Arrival
    Instance                               Reference                                                  Type         Pin     Net            Time        Slack
                                           Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------
    reg_apb_wrp_0.wr_enable                Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       wr_enable      0.737       1.437
    reg_apb_wrp_0.reg16x8_0.mem_5_[0]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[0]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[1]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[1]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[2]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[2]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[3]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[3]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[4]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[4]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[5]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[5]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[6]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[6]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_5_[7]      Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_5_[7]      1.717       2.981
    reg_apb_wrp_0.reg16x8_0.mem_10_[0]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     Q       mem_10_[0]     1.677       2.986
    =======================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                          Starting                                                                                        Required
    Instance                              Reference                                                  Type         Pin     Net             Time         Slack
                                          Clock
    --------------------------------------------------------------------------------------------------------------------------------------------------------
    reg_apb_wrp_0.reg16x8_0.mem_0_[0]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     D       mem_0__4[0]     7.301        1.437
    reg_apb_wrp_0.reg16x8_0.mem_0_[1]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     D       mem_0__4[1]     7.301        1.437
    reg_apb_wrp_0.reg16x8_0.mem_0_[2]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     D       mem_0__4[2]     7.301        1.437
    reg_apb_wrp_0.reg16x8_0.mem_0_[3]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     D       mem_0__4[3]     7.301        1.437
    reg_apb_wrp_0.reg16x8_0.mem_0_[4]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     D       mem_0__4[4]     7.301        1.437
    reg_apb_wrp_0.reg16x8_0.mem_0_[5]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     D       mem_0__4[5]     7.301        1.437
    reg_apb_wrp_0.reg16x8_0.mem_0_[6]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     D       mem_0__4[6]     7.301        1.437
    reg_apb_wrp_0.reg16x8_0.mem_0_[7]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     D       mem_0__4[7]     7.301        1.437
    reg_apb_wrp_0.reg16x8_0.mem_1_[0]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     D       mem_1__4[0]     7.301        1.437
    reg_apb_wrp_0.reg16x8_0.mem_1_[1]     Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock     DFN1P1C1     D       mem_1__4[1]     7.301        1.437
    ========================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            2.699
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         7.301

        - Propagation time:                      5.864
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 1.437

        Number of logic level(s):                2
        Starting point:                          reg_apb_wrp_0.wr_enable / Q
        Ending point:                            reg_apb_wrp_0.reg16x8_0.mem_0_[0] / D
        The start point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                           Pin      Pin               Arrival     No. of
    Name                                        Type         Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------
    reg_apb_wrp_0.wr_enable                     DFN1E1C0     Q        Out     0.737     0.737       -
    wr_enable                                   Net          -        -       2.172     -           16
    reg_apb_wrp_0.reg16x8_0.mem_0__1_sqmuxa     OR2B         A        In      -         2.909       -
    reg_apb_wrp_0.reg16x8_0.mem_0__1_sqmuxa     OR2B         Y        Out     0.514     3.424       -
    mem_0__1_sqmuxa                             Net          -        -       1.639     -           8
    reg_apb_wrp_0.reg16x8_0.mem_0__RNO_0[0]     MX2          S        In      -         5.063       -
    reg_apb_wrp_0.reg16x8_0.mem_0__RNO_0[0]     MX2          Y        Out     0.480     5.542       -
    mem_0__4[0]                                 Net          -        -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.mem_0_[0]           DFN1P1C1     D        In      -         5.864       -
    ==========================================================================================================
    Total path delay (propagation time + setup) of 8.563 is 4.430(51.7%) logic and 4.133(48.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                   Starting                                                                         Arrival
    Instance                       Reference     Type        Pin              Net                                   Time        Slack
                                   Clock
    ----------------------------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST        System        MSS_APB     MSSPADDR[3]      my_mss_0_MSS_MASTER_APB_PADDR_\[3\]   0.000       -3.640
    my_mss_0.MSS_ADLIB_INST        System        MSS_APB     MSSPADDR[2]      my_mss_0_MSS_MASTER_APB_PADDR_\[2\]   0.000       -3.015
    my_mss_0.MSS_ADLIB_INST        System        MSS_APB     MSSPADDR[1]      my_mss_0_MSS_MASTER_APB_PADDR_\[1\]   0.000       -2.703
    my_mss_0.MSS_ADLIB_INST        System        MSS_APB     MSSPADDR[0]      my_mss_0_MSS_MASTER_APB_PADDR_\[0\]   0.000       -2.343
    my_mss_0.MSS_CCC_0.I_RCOSC     System        RCOSC       CLKOUT           N_I_RCOSC_CLKOUT                      0.000       4.169
    my_mss_0.MSS_ADLIB_INST        System        MSS_APB     MSSPWDATA[0]     MSSPWDATA[0]                          0.000       4.239
    my_mss_0.MSS_ADLIB_INST        System        MSS_APB     MSSPWDATA[1]     MSSPWDATA[1]                          0.000       4.239
    my_mss_0.MSS_ADLIB_INST        System        MSS_APB     MSSPWDATA[2]     MSSPWDATA[2]                          0.000       4.239
    my_mss_0.MSS_ADLIB_INST        System        MSS_APB     MSSPWDATA[3]     MSSPWDATA[3]                          0.000       4.239
    my_mss_0.MSS_ADLIB_INST        System        MSS_APB     MSSPWDATA[4]     MSSPWDATA[4]                          0.000       4.239
    ==================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                          Starting                                           Required
    Instance                              Reference     Type         Pin     Net             Time         Slack
                                          Clock
    ------------------------------------------------------------------------------------------------------------
    reg_apb_wrp_0.reg16x8_0.mem_4_[0]     System        DFN1P1C1     D       mem_4__4[0]     7.301        -3.640
    reg_apb_wrp_0.reg16x8_0.mem_4_[1]     System        DFN1P1C1     D       mem_4__4[1]     7.301        -3.640
    reg_apb_wrp_0.reg16x8_0.mem_4_[2]     System        DFN1P1C1     D       mem_4__4[2]     7.301        -3.640
    reg_apb_wrp_0.reg16x8_0.mem_4_[3]     System        DFN1P1C1     D       mem_4__4[3]     7.301        -3.640
    reg_apb_wrp_0.reg16x8_0.mem_4_[4]     System        DFN1P1C1     D       mem_4__4[4]     7.301        -3.640
    reg_apb_wrp_0.reg16x8_0.mem_4_[5]     System        DFN1P1C1     D       mem_4__4[5]     7.301        -3.640
    reg_apb_wrp_0.reg16x8_0.mem_4_[6]     System        DFN1P1C1     D       mem_4__4[6]     7.301        -3.640
    reg_apb_wrp_0.reg16x8_0.mem_4_[7]     System        DFN1P1C1     D       mem_4__4[7]     7.301        -3.640
    reg_apb_wrp_0.reg16x8_0.mem_5_[0]     System        DFN1P1C1     D       mem_5__4[0]     7.301        -3.640
    reg_apb_wrp_0.reg16x8_0.mem_5_[1]     System        DFN1P1C1     D       mem_5__4[1]     7.301        -3.640
    ============================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            2.699
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         7.301

        - Propagation time:                      10.940
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -3.640

        Number of logic level(s):                4
        Starting point:                          my_mss_0.MSS_ADLIB_INST / MSSPADDR[3]
        Ending point:                            reg_apb_wrp_0.reg16x8_0.mem_4_[0] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                                   Pin             Pin               Arrival     No. of
    Name                                                Type         Name            Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST                             MSS_APB      MSSPADDR[3]     Out     0.000     0.000       -
    my_mss_0_MSS_MASTER_APB_PADDR_\[3\]                 Net          -               -       3.429     -           68
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0_2    OR2A         B               In      -         3.429       -
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0_2    OR2A         Y               Out     0.646     4.076       -
    un1_mem_2[7]                                        Net          -               -       1.184     -           4
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0      NOR2         A               In      -         5.259       -
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0      NOR2         Y               Out     0.507     5.767       -
    un1_mem[4]                                          Net          -               -       2.218     -           17
    reg_apb_wrp_0.reg16x8_0.mem_4__1_sqmuxa             OR2B         B               In      -         7.984       -
    reg_apb_wrp_0.reg16x8_0.mem_4__1_sqmuxa             OR2B         Y               Out     0.516     8.500       -
    mem_4__1_sqmuxa                                     Net          -               -       1.639     -           8
    reg_apb_wrp_0.reg16x8_0.mem_4__RNO_0[0]             MX2          S               In      -         10.139      -
    reg_apb_wrp_0.reg16x8_0.mem_4__RNO_0[0]             MX2          Y               Out     0.480     10.619      -
    mem_4__4[0]                                         Net          -               -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.mem_4_[0]                   DFN1P1C1     D               In      -         10.940      -
    =========================================================================================================================
    Total path delay (propagation time + setup) of 13.640 is 4.849(35.5%) logic and 8.791(64.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      10.000
        - Setup time:                            2.699
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         7.301

        - Propagation time:                      10.940
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -3.640

        Number of logic level(s):                4
        Starting point:                          my_mss_0.MSS_ADLIB_INST / MSSPADDR[3]
        Ending point:                            reg_apb_wrp_0.reg16x8_0.mem_7_[0] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                                   Pin             Pin               Arrival     No. of
    Name                                                Type         Name            Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST                             MSS_APB      MSSPADDR[3]     Out     0.000     0.000       -
    my_mss_0_MSS_MASTER_APB_PADDR_\[3\]                 Net          -               -       3.429     -           68
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0_2    OR2A         B               In      -         3.429       -
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0_2    OR2A         Y               Out     0.646     4.076       -
    un1_mem_2[7]                                        Net          -               -       1.184     -           4
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_7        NOR2         A               In      -         5.259       -
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_7        NOR2         Y               Out     0.507     5.767       -
    un1_mem[7]                                          Net          -               -       2.218     -           17
    reg_apb_wrp_0.reg16x8_0.mem_7__1_sqmuxa             OR2B         B               In      -         7.984       -
    reg_apb_wrp_0.reg16x8_0.mem_7__1_sqmuxa             OR2B         Y               Out     0.516     8.500       -
    mem_7__1_sqmuxa                                     Net          -               -       1.639     -           8
    reg_apb_wrp_0.reg16x8_0.mem_7__RNO_0[0]             MX2          S               In      -         10.139      -
    reg_apb_wrp_0.reg16x8_0.mem_7__RNO_0[0]             MX2          Y               Out     0.480     10.619      -
    mem_7__4[0]                                         Net          -               -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.mem_7_[0]                   DFN1P1C1     D               In      -         10.940      -
    =========================================================================================================================
    Total path delay (propagation time + setup) of 13.640 is 4.849(35.5%) logic and 8.791(64.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      10.000
        - Setup time:                            2.699
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         7.301

        - Propagation time:                      10.940
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -3.640

        Number of logic level(s):                4
        Starting point:                          my_mss_0.MSS_ADLIB_INST / MSSPADDR[3]
        Ending point:                            reg_apb_wrp_0.reg16x8_0.mem_6_[0] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                                   Pin             Pin               Arrival     No. of
    Name                                                Type         Name            Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST                             MSS_APB      MSSPADDR[3]     Out     0.000     0.000       -
    my_mss_0_MSS_MASTER_APB_PADDR_\[3\]                 Net          -               -       3.429     -           68
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0_2    OR2A         B               In      -         3.429       -
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0_2    OR2A         Y               Out     0.646     4.076       -
    un1_mem_2[7]                                        Net          -               -       1.184     -           4
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_6        NOR2         A               In      -         5.259       -
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_6        NOR2         Y               Out     0.507     5.767       -
    un1_mem[6]                                          Net          -               -       2.218     -           17
    reg_apb_wrp_0.reg16x8_0.mem_6__1_sqmuxa             OR2B         B               In      -         7.984       -
    reg_apb_wrp_0.reg16x8_0.mem_6__1_sqmuxa             OR2B         Y               Out     0.516     8.500       -
    mem_6__1_sqmuxa                                     Net          -               -       1.639     -           8
    reg_apb_wrp_0.reg16x8_0.mem_6__RNO_0[0]             MX2          S               In      -         10.139      -
    reg_apb_wrp_0.reg16x8_0.mem_6__RNO_0[0]             MX2          Y               Out     0.480     10.619      -
    mem_6__4[0]                                         Net          -               -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.mem_6_[0]                   DFN1P1C1     D               In      -         10.940      -
    =========================================================================================================================
    Total path delay (propagation time + setup) of 13.640 is 4.849(35.5%) logic and 8.791(64.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      10.000
        - Setup time:                            2.699
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         7.301

        - Propagation time:                      10.940
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -3.640

        Number of logic level(s):                4
        Starting point:                          my_mss_0.MSS_ADLIB_INST / MSSPADDR[3]
        Ending point:                            reg_apb_wrp_0.reg16x8_0.mem_5_[0] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                                   Pin             Pin               Arrival     No. of
    Name                                                Type         Name            Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST                             MSS_APB      MSSPADDR[3]     Out     0.000     0.000       -
    my_mss_0_MSS_MASTER_APB_PADDR_\[3\]                 Net          -               -       3.429     -           68
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0_2    OR2A         B               In      -         3.429       -
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0_2    OR2A         Y               Out     0.646     4.076       -
    un1_mem_2[7]                                        Net          -               -       1.184     -           4
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_5        NOR2         A               In      -         5.259       -
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_5        NOR2         Y               Out     0.507     5.767       -
    un1_mem[5]                                          Net          -               -       2.218     -           17
    reg_apb_wrp_0.reg16x8_0.mem_5__1_sqmuxa             OR2B         B               In      -         7.984       -
    reg_apb_wrp_0.reg16x8_0.mem_5__1_sqmuxa             OR2B         Y               Out     0.516     8.500       -
    mem_5__1_sqmuxa                                     Net          -               -       1.639     -           8
    reg_apb_wrp_0.reg16x8_0.mem_5__RNO_0[0]             MX2          S               In      -         10.139      -
    reg_apb_wrp_0.reg16x8_0.mem_5__RNO_0[0]             MX2          Y               Out     0.480     10.619      -
    mem_5__4[0]                                         Net          -               -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.mem_5_[0]                   DFN1P1C1     D               In      -         10.940      -
    =========================================================================================================================
    Total path delay (propagation time + setup) of 13.640 is 4.849(35.5%) logic and 8.791(64.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      10.000
        - Setup time:                            2.699
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         7.301

        - Propagation time:                      10.940
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -3.640

        Number of logic level(s):                4
        Starting point:                          my_mss_0.MSS_ADLIB_INST / MSSPADDR[3]
        Ending point:                            reg_apb_wrp_0.reg16x8_0.mem_4_[1] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|my_mss_0.MSS_CCC_0.my_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                                   Pin             Pin               Arrival     No. of
    Name                                                Type         Name            Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------
    my_mss_0.MSS_ADLIB_INST                             MSS_APB      MSSPADDR[3]     Out     0.000     0.000       -
    my_mss_0_MSS_MASTER_APB_PADDR_\[3\]                 Net          -               -       3.429     -           68
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0_2    OR2A         B               In      -         3.429       -
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0_2    OR2A         Y               Out     0.646     4.076       -
    un1_mem_2[7]                                        Net          -               -       1.184     -           4
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0      NOR2         A               In      -         5.259       -
    reg_apb_wrp_0.reg16x8_0.WRITE_GEN\.un1_mem_4_0      NOR2         Y               Out     0.507     5.767       -
    un1_mem[4]                                          Net          -               -       2.218     -           17
    reg_apb_wrp_0.reg16x8_0.mem_4__1_sqmuxa             OR2B         B               In      -         7.984       -
    reg_apb_wrp_0.reg16x8_0.mem_4__1_sqmuxa             OR2B         Y               Out     0.516     8.500       -
    mem_4__1_sqmuxa                                     Net          -               -       1.639     -           8
    reg_apb_wrp_0.reg16x8_0.mem_4__RNO_0[1]             MX2          S               In      -         10.139      -
    reg_apb_wrp_0.reg16x8_0.mem_4__RNO_0[1]             MX2          Y               Out     0.480     10.619      -
    mem_4__4[1]                                         Net          -               -       0.322     -           1
    reg_apb_wrp_0.reg16x8_0.mem_4_[1]                   DFN1P1C1     D               In      -         10.940      -
    =========================================================================================================================
    Total path delay (propagation time + setup) of 13.640 is 4.849(35.5%) logic and 8.791(64.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    --------------------------------------------------------------------------------
    Target Part: A2F200M3F_FBGA256_Std
    Report for cell Top.verilog
      Core Cell usage:
                  cell count     area count*area
                  AXO7     1      1.0        1.0
                 AXOI4     1      1.0        1.0
                  BUFF     6      1.0        6.0
                   GND     7      0.0        0.0
               MSS_APB     1      0.0        0.0
               MSS_CCC     1      0.0        0.0
                   MX2   128      1.0      128.0
                  MX2C   120      1.0      120.0
                  NOR2    18      1.0       18.0
                 NOR2A     9      1.0        9.0
                 NOR3A   129      1.0      129.0
                  OA1C   130      1.0      130.0
                   OR2     4      1.0        4.0
                  OR2A     4      1.0        4.0
                  OR2B    19      1.0       19.0
                 RCOSC     1      0.0        0.0
                   VCC     7      0.0        0.0

                  DFN1     8      1.0        8.0
                DFN1C0     2      1.0        2.0
              DFN1E1C0    10      1.0       10.0
              DFN1E1P0     1      1.0        1.0
              DFN1P1C1   128      1.0      128.0
                       -----          ----------
                 TOTAL   735               718.0

      IO Cell usage:
                  cell count
             INBUF_MSS     2
            OUTBUF_MSS     1
                       -----
                 TOTAL     3

    Core Cells         : 718 of 4608 (16%)
    IO Cells           : 3 of 66 (5%)

      RAM/ROM Usage Summary
    Block Rams : 0 of 8 (0%)

    Mapper successful!
    Process took 0h:00m:05s realtime, 0h:00m:01s cputime
    # Wed Mar 03 16:46:55 2010

    ###########################################################]

`