 ** Message System Log
 ** Database: 
 ** Date:   Mon Nov 28 11:23:44 2005


****************
Macro Parameters
****************

Name                            : PLL_100_10
Family                          : Fusion
Output Format                   : VHDL
Type                            : Static PLL
Input Freq(Mhz)                 : 100.000
CLKA Source                     : Hardwired I/O
Feedback Delay Value Index      : 1
Feedback Mux Select             : 1
XDLY Mux Select                 : No
Primary Freq(Mhz)               : 10.000
Primary PhaseShift              : 0
Primary Delay Value Index       : 1
Primary Mux Select              : 4
Secondary1 Freq(Mhz)            : 0.000000
Use GLB                         : NO
Use YB                          : NO
GLB Delay Value Index           : 32
YB Delay Value Index            : 32
Secondary1 PhaseShift           : 0
Secondary1 Mux Select           : 0
Secondary2 Freq(Mhz)            : 0.000000
Use GLC                         : NO
Use YC                          : NO
GLC Delay Value Index           : 32
YC Delay Value Index            : 32
Secondary2 PhaseShift           : 0
Secondary2 Mux Select           : 0

Configuration Bits:
FINDIV     0010010
FBDIV      0010010
OADIV      01001
OADIVHALF 0
OBDIV      00000
OCDIV      00000
OAMUX      100
OBMUX      000
OCMUX      000
FBSEL      01
FBDLY      00000
XDLYSEL    0
DLYGLA     00000
DLYGLB     00000
DLYGLC     00000
DLYYB      00000
DLYYC      00000
VCOSEL     100

Primary Clock Freqeuncy 10.000
Primary Clock Phase Shift 0.000
Primary Clock Output Delay from CLKA 1.780


Written VHDL netlist to
D:/backup/Projects/G3SOC/StarterKit/PwrM/smartgen\PLL_100_10\PLL_100_10.vhd.

 ** Log Ended:   Mon Nov 28 11:23:44 2005

