#-- Synplicity, Inc.
#-- Version Synplify 8.5B
#-- Project file D:\RTC_Demo\synthesis\RTC_demo_syn.prj
#-- Written on Thu Jun 22 15:29:17 2006


#add_file options
add_file -vhdl -lib work "$LIB/proasic/fusion.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/RCO/RCO.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/PLL_100_10/PLL_100_10.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/VR_mon/VR_mon.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/Shift8_reg/Shift8_reg.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/equal0/equal0.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/hdl/RIP_COUNT32.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/hdl/RTC_calendar.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/hdl/clockdiv.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/hdl/my_clk_divider.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/hdl/Data_to_LCD.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/hdl/LCD_DIS.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/XTAL_RTC/XTAL_RTC.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/common/vhdl/initcfg_xa.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/common/vhdl/initcfg_xb.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/common/vhdl/initcfg_xc.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/common/vhdl/initcfg_xd.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/common/vhdl/initcfg_xe.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/common/vhdl/initcfg_xf.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/common/vhdl/initcfg.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/NVM_analog/NVM_analog_init_wrapper.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/NVM_analog/NVM_analog.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/common/vhdl/assc.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/Analog_RTC/Analog_RTC_assc_wrapper.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/common/vhdl/smtr.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/Analog_RTC/Analog_RTC_smtr_wrapper.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/Analog_RTC/Analog_RTC_smtr_ram.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/common/vhdl/smev.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/Analog_RTC/Analog_RTC_smev_wrapper.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/Analog_RTC/Analog_RTC_smev_ram.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/Analog_RTC/Analog_RTC_assc_ram.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/smartgen/Analog_RTC/Analog_RTC.vhd"
add_file -vhdl -lib work "D:/RTC_Demo/hdl/RTC_demo.vhd"


#implementation: "synthesis"
impl -add synthesis -type fpga

#device options
set_option -technology Fusion
set_option -part AFS600

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 1.000
set_option -run_prop_extract 0
set_option -fanout_limit 16
set_option -globalthreshold 50
set_option -maxfan_hard 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_format "edif"
project -result_file "./RTC_demo.edn"
impl -active "synthesis"
