@TM:1141926099
@W: BN153 :"":0:0:0:-1|View "prim", Cell "NGMUX", Port "CLK0": remove clock marking
@W: BN153 :"":0:0:0:-1|View "prim", Cell "NGMUX", Port "CLK1": remove clock marking
@W: BN154 :"":0:0:0:-1|View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed
@TM:1149884665
@W: BN227 :"":0:0:0:-1|This data was produced by a restricted version of Synplicity software. The results contain Synplicity IP and are not licensed to be used for production design work or design services
@TM:1141926099
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1149884665
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@N: CD630 :"d:\libero71\synplify\synplify_85b\lib\proasic\fusion.vhd":4892:10:4892:12|M
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@TM:1150316930
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@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
@W:  :"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|M
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@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":109:4:109:18|M
@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":149:4:149:18|M
@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":169:4:169:19|M
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@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":317:4:317:19|M
@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":336:4:336:19|M
@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":344:4:344:19|M
@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":360:4:360:19|M
@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":400:4:400:19|M
@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":443:4:443:19|M
@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":451:4:451:18|M
@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":455:4:455:18|M
@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":467:4:467:18|M
@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":471:4:471:19|M
@W:  :"d:\rtc_demo\hdl\rip_count32.vhd":495:4:495:19|M
@N: CD630 :"d:\rtc_demo\hdl\rtc_calendar.vhd":11:7:11:18|M
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@W: MO129 :"d:\rtc_demo\hdl\rtc_calendar.vhd":350:1:350:2|M
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@N: MF238 :"d:\rtc_demo\hdl\rtc_calendar.vhd":497:33:497:59|M
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@W: CD434 :"d:\rtc_demo\hdl\rtc_demo.vhd":393:33:393:43|M
@W: CL170 :"d:\rtc_demo\hdl\rtc_demo.vhd":408:2:408:3|M
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@W: CD639 :"d:\rtc_demo\smartgen\analog_rtc\analog_rtc.vhd":243:11:243:29|M
@W: CD639 :"d:\rtc_demo\smartgen\analog_rtc\analog_rtc.vhd":249:11:249:27|M
@W: CD639 :"d:\rtc_demo\smartgen\analog_rtc\analog_rtc.vhd":255:11:255:22|M
@W: CD639 :"d:\rtc_demo\smartgen\analog_rtc\analog_rtc.vhd":258:11:258:22|M
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@N: CD630 :"d:\rtc_demo\smartgen\pll_100_10\pll_100_10.vhd":7:7:7:16|M
@W:  :"d:\rtc_demo\smartgen\pll_100_10\pll_100_10.vhd":47:4:47:7|M
@N: CD630 :"d:\rtc_demo\smartgen\rco\rco.vhd":7:7:7:9|M
@N: CD630 :"d:\rtc_demo\smartgen\shift8_reg\shift8_reg.vhd":7:7:7:16|M
@N: CD630 :"d:\rtc_demo\smartgen\vr_mon\vr_mon.vhd":7:7:7:12|M
@W: CL168 :"d:\rtc_demo\smartgen\vr_mon\vr_mon.vhd":34:4:34:12|M
@N: CD630 :"d:\rtc_demo\smartgen\xtal_rtc\xtal_rtc.vhd":7:7:7:14|M
@W:  :"d:\rtc_demo\smartgen\xtal_rtc\xtal_rtc.vhd":40:4:40:10|M
