<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PLL_100_10</name><fileSets><fileSet fileSetId="HDL_FILESET"><file fileId="1"><name>PLL_100_10.vhd</name><fileType>VHDLSource</fileType></file></fileSet><fileSet fileSetId="OTHER_FILESET"><file fileId="2"><name>PLL_100_10.gen</name><fileType><userFileType type="GEN"/></fileType></file><file fileId="3"><name>PLL_100_10.log</name><fileType><userFileType type="LOG"/></fileType></file></fileSet></fileSets><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>OTHER_FILESET</fileSetRef><name>Other</name></view></views><category>Clock Conditioning / PLL</category><function>Static PLL</function><variation>Static PLL</variation><vendor>Actel</vendor><version>2.0</version></Component>