#Build: Synplify 8.5B, Build 429R, Dec  8 2005
#install: D:\Libero71\Synplify\Synplify_85B
#OS: Windows XP 5.1
#Hostname: WXP-WONGAL

#Thu Jun 22 15:22:47 2006

$ Start of Compile
#Thu Jun 22 15:22:47 2006

Synplicity VHDL Compiler, version 3.4.1, Build 089R, built Mar  8 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@N:"D:\RTC_Demo\hdl\RTC_demo.vhd":56:7:56:14|Top entity is set to RTC_demo.
VHDL syntax check successful!
File D:\RTC_Demo\hdl\RTC_calendar.vhd changed - recompiling
@N: CD630 :"D:\RTC_Demo\hdl\RTC_demo.vhd":35:7:35:14|Synthesizing work.rtc_demo.def_arch 
@W: CD279 :"D:\RTC_Demo\hdl\RTC_demo.vhd":173:9:173:19|Port rtcpsmmatch of component analog_rtc not found on corresponding entity
@W: CD434 :"D:\RTC_Demo\hdl\RTC_demo.vhd":417:33:417:43|Signal nvm_acm_wen in the sensitivity list is not used in the process
@N: CD630 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":7:7:7:16|Synthesizing work.analog_rtc.def_arch 
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":5552:10:5552:11|Synthesizing work.ab.syn_black_box 
Post processing for work.ab.syn_black_box
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":225:11:225:27|Bit <0> of signal assc_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":225:11:225:27|Bit <1> of signal assc_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":225:11:225:27|Bit <2> of signal assc_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":225:11:225:27|Bit <3> of signal assc_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":225:11:225:27|Bit <4> of signal assc_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":225:11:225:27|Bit <5> of signal assc_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":225:11:225:27|Bit <6> of signal assc_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":225:11:225:27|Bit <7> of signal assc_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":231:11:231:29|Bit <0> of signal assc_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":231:11:231:29|Bit <1> of signal assc_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":231:11:231:29|Bit <2> of signal assc_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":231:11:231:29|Bit <3> of signal assc_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":231:11:231:29|Bit <4> of signal assc_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":231:11:231:29|Bit <5> of signal assc_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":231:11:231:29|Bit <6> of signal assc_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":231:11:231:29|Bit <7> of signal assc_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":237:11:237:27|Bit <0> of signal assc_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":237:11:237:27|Bit <1> of signal assc_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":237:11:237:27|Bit <2> of signal assc_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":237:11:237:27|Bit <3> of signal assc_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":237:11:237:27|Bit <4> of signal assc_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":237:11:237:27|Bit <5> of signal assc_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":237:11:237:27|Bit <6> of signal assc_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":237:11:237:27|Bit <7> of signal assc_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":243:11:243:29|Bit <0> of signal assc_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":243:11:243:29|Bit <1> of signal assc_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":243:11:243:29|Bit <2> of signal assc_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":243:11:243:29|Bit <3> of signal assc_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":243:11:243:29|Bit <4> of signal assc_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":243:11:243:29|Bit <5> of signal assc_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":243:11:243:29|Bit <6> of signal assc_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":243:11:243:29|Bit <7> of signal assc_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":249:11:249:27|Bit <0> of signal assc_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":249:11:249:27|Bit <1> of signal assc_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":249:11:249:27|Bit <2> of signal assc_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":249:11:249:27|Bit <3> of signal assc_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":249:11:249:27|Bit <4> of signal assc_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":249:11:249:27|Bit <5> of signal assc_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":249:11:249:27|Bit <6> of signal assc_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":249:11:249:27|Bit <7> of signal assc_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":255:11:255:22|Bit <0> of signal adc_mode_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":255:11:255:22|Bit <1> of signal adc_mode_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":255:11:255:22|Bit <2> of signal adc_mode_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":258:11:258:22|Bit <0> of signal adc_chnr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":258:11:258:22|Bit <1> of signal adc_chnr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":258:11:258:22|Bit <2> of signal adc_chnr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":258:11:258:22|Bit <3> of signal adc_chnr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":261:11:261:21|Bit <0> of signal adc_stc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":261:11:261:21|Bit <1> of signal adc_stc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":261:11:261:21|Bit <2> of signal adc_stc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":261:11:261:21|Bit <3> of signal adc_stc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":261:11:261:21|Bit <4> of signal adc_stc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":261:11:261:21|Bit <5> of signal adc_stc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":261:11:261:21|Bit <6> of signal adc_stc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":265:11:265:21|Bit <0> of signal adc_tvc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":265:11:265:21|Bit <1> of signal adc_tvc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":265:11:265:21|Bit <2> of signal adc_tvc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":265:11:265:21|Bit <3> of signal adc_tvc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":265:11:265:21|Bit <4> of signal adc_tvc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":265:11:265:21|Bit <5> of signal adc_tvc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":265:11:265:21|Bit <6> of signal adc_tvc_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":270:11:270:24|Bit <0> of signal adc_result_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":270:11:270:24|Bit <1> of signal adc_result_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":270:11:270:24|Bit <2> of signal adc_result_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":270:11:270:24|Bit <3> of signal adc_result_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":270:11:270:24|Bit <4> of signal adc_result_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":270:11:270:24|Bit <5> of signal adc_result_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":270:11:270:24|Bit <6> of signal adc_result_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":270:11:270:24|Bit <7> of signal adc_result_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":270:11:270:24|Bit <8> of signal adc_result_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":270:11:270:24|Bit <9> of signal adc_result_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":270:11:270:24|Bit <10> of signal adc_result_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":283:11:283:25|Bit <0> of signal ev_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":283:11:283:25|Bit <1> of signal ev_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":283:11:283:25|Bit <2> of signal ev_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":283:11:283:25|Bit <3> of signal ev_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":283:11:283:25|Bit <4> of signal ev_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":283:11:283:25|Bit <5> of signal ev_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":283:11:283:25|Bit <6> of signal ev_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":283:11:283:25|Bit <7> of signal ev_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":288:11:288:27|Bit <0> of signal ev_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":288:11:288:27|Bit <1> of signal ev_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":288:11:288:27|Bit <2> of signal ev_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":288:11:288:27|Bit <3> of signal ev_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":288:11:288:27|Bit <4> of signal ev_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":288:11:288:27|Bit <5> of signal ev_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":288:11:288:27|Bit <6> of signal ev_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":288:11:288:27|Bit <7> of signal ev_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":294:11:294:25|Bit <0> of signal ev_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":294:11:294:25|Bit <1> of signal ev_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":294:11:294:25|Bit <2> of signal ev_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":294:11:294:25|Bit <3> of signal ev_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":294:11:294:25|Bit <4> of signal ev_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":294:11:294:25|Bit <5> of signal ev_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":294:11:294:25|Bit <6> of signal ev_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":294:11:294:25|Bit <7> of signal ev_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":299:11:299:27|Bit <0> of signal ev_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":299:11:299:27|Bit <1> of signal ev_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":299:11:299:27|Bit <2> of signal ev_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":299:11:299:27|Bit <3> of signal ev_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":299:11:299:27|Bit <4> of signal ev_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":299:11:299:27|Bit <5> of signal ev_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":299:11:299:27|Bit <6> of signal ev_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":299:11:299:27|Bit <7> of signal ev_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":305:11:305:25|Bit <0> of signal ev_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":305:11:305:25|Bit <1> of signal ev_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":305:11:305:25|Bit <2> of signal ev_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":305:11:305:25|Bit <3> of signal ev_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":305:11:305:25|Bit <4> of signal ev_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":305:11:305:25|Bit <5> of signal ev_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":305:11:305:25|Bit <6> of signal ev_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":305:11:305:25|Bit <7> of signal ev_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":310:11:310:25|Bit <0> of signal ev_asscaddr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":310:11:310:25|Bit <1> of signal ev_asscaddr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":310:11:310:25|Bit <2> of signal ev_asscaddr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":310:11:310:25|Bit <3> of signal ev_asscaddr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":310:11:310:25|Bit <4> of signal ev_asscaddr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":310:11:310:25|Bit <5> of signal ev_asscaddr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":310:11:310:25|Bit <6> of signal ev_asscaddr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":310:11:310:25|Bit <7> of signal ev_asscaddr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":316:11:316:25|Bit <0> of signal assc_seqout_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":316:11:316:25|Bit <1> of signal assc_seqout_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":316:11:316:25|Bit <2> of signal assc_seqout_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":316:11:316:25|Bit <3> of signal assc_seqout_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":316:11:316:25|Bit <4> of signal assc_seqout_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":322:11:322:27|Bit <0> of signal assc_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":322:11:322:27|Bit <1> of signal assc_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":322:11:322:27|Bit <2> of signal assc_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":322:11:322:27|Bit <3> of signal assc_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":322:11:322:27|Bit <4> of signal assc_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":322:11:322:27|Bit <5> of signal assc_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":322:11:322:27|Bit <6> of signal assc_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":322:11:322:27|Bit <7> of signal assc_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":328:11:328:24|Bit <0> of signal tr_ev_addr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":328:11:328:24|Bit <1> of signal tr_ev_addr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":328:11:328:24|Bit <2> of signal tr_ev_addr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":328:11:328:24|Bit <3> of signal tr_ev_addr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":328:11:328:24|Bit <4> of signal tr_ev_addr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":328:11:328:24|Bit <5> of signal tr_ev_addr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":328:11:328:24|Bit <6> of signal tr_ev_addr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":328:11:328:24|Bit <7> of signal tr_ev_addr_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":334:11:334:23|Bit <0> of signal ev_chhold_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":334:11:334:23|Bit <1> of signal ev_chhold_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":334:11:334:23|Bit <2> of signal ev_chhold_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":334:11:334:23|Bit <3> of signal ev_chhold_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":338:11:338:25|Bit <0> of signal ev_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":338:11:338:25|Bit <1> of signal ev_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":338:11:338:25|Bit <2> of signal ev_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":338:11:338:25|Bit <3> of signal ev_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":338:11:338:25|Bit <4> of signal ev_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":338:11:338:25|Bit <5> of signal ev_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":338:11:338:25|Bit <6> of signal ev_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":338:11:338:25|Bit <7> of signal ev_ram_do_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":344:11:344:25|Bit <0> of signal tr_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":344:11:344:25|Bit <1> of signal tr_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":344:11:344:25|Bit <2> of signal tr_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":344:11:344:25|Bit <3> of signal tr_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":344:11:344:25|Bit <4> of signal tr_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":344:11:344:25|Bit <5> of signal tr_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":344:11:344:25|Bit <6> of signal tr_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":344:11:344:25|Bit <7> of signal tr_ram_di_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":349:11:349:27|Bit <0> of signal tr_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":349:11:349:27|Bit <1> of signal tr_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":349:11:349:27|Bit <2> of signal tr_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":349:11:349:27|Bit <3> of signal tr_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":349:11:349:27|Bit <4> of signal tr_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":349:11:349:27|Bit <5> of signal tr_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":349:11:349:27|Bit <6> of signal tr_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":349:11:349:27|Bit <7> of signal tr_ram_addr_a_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":355:11:355:25|Bit <0> of signal tr_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":355:11:355:25|Bit <1> of signal tr_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":355:11:355:25|Bit <2> of signal tr_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":355:11:355:25|Bit <3> of signal tr_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":355:11:355:25|Bit <4> of signal tr_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":355:11:355:25|Bit <5> of signal tr_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":355:11:355:25|Bit <6> of signal tr_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":355:11:355:25|Bit <7> of signal tr_ram_di_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":360:11:360:27|Bit <0> of signal tr_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":360:11:360:27|Bit <1> of signal tr_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":360:11:360:27|Bit <2> of signal tr_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":360:11:360:27|Bit <3> of signal tr_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":360:11:360:27|Bit <4> of signal tr_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":360:11:360:27|Bit <5> of signal tr_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":360:11:360:27|Bit <6> of signal tr_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":360:11:360:27|Bit <7> of signal tr_ram_addr_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":366:11:366:25|Bit <0> of signal tr_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":366:11:366:25|Bit <1> of signal tr_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":366:11:366:25|Bit <2> of signal tr_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":366:11:366:25|Bit <3> of signal tr_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":366:11:366:25|Bit <4> of signal tr_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":366:11:366:25|Bit <5> of signal tr_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":366:11:366:25|Bit <6> of signal tr_ram_do_b_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC.vhd":366:11:366:25|Bit <7> of signal tr_ram_do_b_net is undriven 
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":4606:10:4606:12|Synthesizing work.vcc.syn_black_box 
Post processing for work.vcc.syn_black_box
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":2020:10:2020:12|Synthesizing work.gnd.syn_black_box 
Post processing for work.gnd.syn_black_box
@N: CD630 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC_assc_ram.vhd":7:7:7:25|Synthesizing work.analog_rtc_assc_ram.def_arch 
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":5075:10:5075:15|Synthesizing work.ram4k9.syn_black_box 
Post processing for work.ram4k9.syn_black_box
Post processing for work.analog_rtc_assc_ram.def_arch
@N: CD630 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC_smev_ram.vhd":7:7:7:25|Synthesizing work.analog_rtc_smev_ram.def_arch 
Post processing for work.analog_rtc_smev_ram.def_arch
@N: CD630 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC_smev_wrapper.vhd":83:7:83:29|Synthesizing work.analog_rtc_smev_wrapper.def_arch 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\smev.vhd":308:7:308:10|Synthesizing work.smev.behv 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\smev.vhd":10:0:10:10|Synthesizing work.nbnjbfrkqwq.qhrkzzskhwz 
@N: CD231 :"D:\RTC_Demo\smartgen\common\vhdl\smev.vhd":61:12:61:13|Using onehot encoding for type vspwsmpffhb (kntgqgfbzkr="100000000000000000")
@W: CD638 :"D:\RTC_Demo\smartgen\common\vhdl\smev.vhd":77:0:77:10|Signal smsgrfvbrts is undriven 
Post processing for work.nbnjbfrkqwq.qhrkzzskhwz
@N: CL201 :"D:\RTC_Demo\smartgen\common\vhdl\smev.vhd":247:71:247:72|Trying to extract state machine for register tkcbxxqbtfx
Extracted state machine for register tkcbxxqbtfx
State machine has 18 reachable states with original encodings of:
   000000000000000001
   000000000000000010
   000000000000000100
   000000000000001000
   000000000000010000
   000000000000100000
   000000000001000000
   000000000010000000
   000000000100000000
   000000001000000000
   000000010000000000
   000000100000000000
   000001000000000000
   000010000000000000
   000100000000000000
   001000000000000000
   010000000000000000
   100000000000000000
@W: CL159 :"D:\RTC_Demo\smartgen\common\vhdl\smev.vhd":19:0:19:10|Input zxrxtxxbsks is unused
@W: CL159 :"D:\RTC_Demo\smartgen\common\vhdl\smev.vhd":19:57:19:67|Input zhkvvfnsbjb is unused
@W: CL159 :"D:\RTC_Demo\smartgen\common\vhdl\smev.vhd":24:0:24:10|Input mqmgjkmdztb is unused
Post processing for work.smev.behv
Post processing for work.analog_rtc_smev_wrapper.def_arch
@N: CD630 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC_smtr_ram.vhd":7:7:7:25|Synthesizing work.analog_rtc_smtr_ram.def_arch 
Post processing for work.analog_rtc_smtr_ram.def_arch
@N: CD630 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC_smtr_wrapper.vhd":75:7:75:29|Synthesizing work.analog_rtc_smtr_wrapper.def_arch 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\smtr.vhd":283:56:283:59|Synthesizing work.smtr.behv 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\smtr.vhd":10:0:10:10|Synthesizing work.ccfdxrhchsz.djzfpsxghmt 
@N: CD231 :"D:\RTC_Demo\smartgen\common\vhdl\smtr.vhd":62:12:62:13|Using onehot encoding for type bzhvcjnmprc (tddtwhmsmxw="100000000000")
@W: CD638 :"D:\RTC_Demo\smartgen\common\vhdl\smtr.vhd":72:0:72:10|Signal jjnnjkrjzfq is undriven 
@W: CD638 :"D:\RTC_Demo\smartgen\common\vhdl\smtr.vhd":77:0:77:10|Signal mgqspspvvwp is undriven 
@W: CD638 :"D:\RTC_Demo\smartgen\common\vhdl\smtr.vhd":86:49:86:59|Signal czjszchcxth is undriven 
@W: CD638 :"D:\RTC_Demo\smartgen\common\vhdl\smtr.vhd":91:29:91:39|Signal rdqhbcjchvq is undriven 
Post processing for work.ccfdxrhchsz.djzfpsxghmt
@N: CL201 :"D:\RTC_Demo\smartgen\common\vhdl\smtr.vhd":254:30:254:31|Trying to extract state machine for register frcskdnwvmx
Extracted state machine for register frcskdnwvmx
State machine has 12 reachable states with original encodings of:
   000000000001
   000000000010
   000000000100
   000000001000
   000000010000
   000000100000
   000001000000
   000010000000
   000100000000
   001000000000
   010000000000
   100000000000
@W: CL234 :"D:\RTC_Demo\smartgen\common\vhdl\smtr.vhd":21:51:21:61|Input port bits <8 to 1> of qxzrwpjhcww(8 downto 0) are unused 
@W: CL159 :"D:\RTC_Demo\smartgen\common\vhdl\smtr.vhd":19:0:19:10|Input qbrqxpmkpsw is unused
@W: CL159 :"D:\RTC_Demo\smartgen\common\vhdl\smtr.vhd":19:57:19:67|Input nktsnhmjrbx is unused
@W: CL159 :"D:\RTC_Demo\smartgen\common\vhdl\smtr.vhd":22:30:22:40|Input dnmrkvrtbjn is unused
Post processing for work.smtr.behv
Post processing for work.analog_rtc_smtr_wrapper.def_arch
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":3755:10:3755:12|Synthesizing work.or2.syn_black_box 
Post processing for work.or2.syn_black_box
@N: CD630 :"D:\RTC_Demo\smartgen\Analog_RTC\Analog_RTC_assc_wrapper.vhd":115:7:115:29|Synthesizing work.analog_rtc_assc_wrapper.def_arch 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\assc.vhd":374:56:374:59|Synthesizing work.assc.behv 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\assc.vhd":10:0:10:10|Synthesizing work.cwgmnvwgkwq.wzrwkfmxjkf 
@N: CD231 :"D:\RTC_Demo\smartgen\common\vhdl\assc.vhd":80:28:80:29|Using onehot encoding for type bzrdgxjrssj (zhnxfbzxsbj="100000000000000")
Post processing for work.cwgmnvwgkwq.wzrwkfmxjkf
@W: CL169 :"D:\RTC_Demo\smartgen\common\vhdl\assc.vhd":315:51:315:52|Pruning Register pbpfdkhvxdb  
@W: CL169 :"D:\RTC_Demo\smartgen\common\vhdl\assc.vhd":315:51:315:52|Pruning Register dvpgmbcxcxr(10 downto 0)  
@W: CL169 :"D:\RTC_Demo\smartgen\common\vhdl\assc.vhd":301:57:301:58|Pruning Register htqbzwtrpxj  
@W: CL169 :"D:\RTC_Demo\smartgen\common\vhdl\assc.vhd":301:57:301:58|Pruning Register hxjrdtjfjrt(9 downto 0)  
@N: CL201 :"D:\RTC_Demo\smartgen\common\vhdl\assc.vhd":294:46:294:47|Trying to extract state machine for register zwnnqcvfccb
Extracted state machine for register zwnnqcvfccb
State machine has 15 reachable states with original encodings of:
   000000000000001
   000000000000010
   000000000000100
   000000000001000
   000000000010000
   000000000100000
   000000001000000
   000000010000000
   000000100000000
   000001000000000
   000010000000000
   000100000000000
   001000000000000
   010000000000000
   100000000000000
@W: CL159 :"D:\RTC_Demo\smartgen\common\vhdl\assc.vhd":18:55:18:65|Input cnwsmzznwfg is unused
@W: CL159 :"D:\RTC_Demo\smartgen\common\vhdl\assc.vhd":19:30:19:40|Input npqxxjzzczt is unused
Post processing for work.assc.behv
Post processing for work.analog_rtc_assc_wrapper.def_arch
Post processing for work.analog_rtc.def_arch
@N: CD630 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":7:7:7:16|Synthesizing work.nvm_analog.def_arch 
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":5721:10:5721:12|Synthesizing work.nvm.syn_black_box 
Post processing for work.nvm.syn_black_box
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <0> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <1> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <2> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <3> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <4> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <5> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <6> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <7> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <8> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <9> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <10> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <11> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <12> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <13> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <14> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <15> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <16> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <17> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <18> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <19> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <20> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <21> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <22> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <23> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <24> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <25> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <26> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <27> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <28> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <29> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":85:11:85:24|Bit <30> of signal nvm_dat_to_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <0> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <1> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <2> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <3> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <4> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <5> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <6> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <7> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <8> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <9> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <10> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <11> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <12> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <13> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <14> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <15> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":102:11:102:21|Bit <16> of signal nvm_add_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":110:11:110:23|Bit <0> of signal nvm_width_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <0> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <1> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <2> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <3> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <4> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <5> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <6> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <7> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <8> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <9> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <10> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <11> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <12> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <13> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <14> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <15> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <16> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <17> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <18> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <19> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <20> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <21> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <22> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <23> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <24> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <25> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <26> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <27> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <28> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <29> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":117:11:117:26|Bit <30> of signal nvm_dat_from_net is undriven 
@W: CD639 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":134:11:134:24|Bit <0> of signal nvm_status_net is undriven 
@N: CD630 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog_init_wrapper.vhd":127:7:127:29|Synthesizing work.nvm_analog_init_wrapper.def_arch 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg.vhd":585:7:585:13|Synthesizing work.initcfg.behavior 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg.vhd":10:0:10:10|Synthesizing work.grwzcnqmqzm.mjtkskcsjhk 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xf.vhd":37:60:37:69|Synthesizing work.initcfg_xf.behavior 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xf.vhd":10:0:10:10|Synthesizing work.jhmkpjjmdkx.bmnqpbgpmvq 
Post processing for work.jhmkpjjmdkx.bmnqpbgpmvq
Post processing for work.initcfg_xf.behavior
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xe.vhd":27:0:27:9|Synthesizing work.initcfg_xe.behavior 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xe.vhd":10:0:10:10|Synthesizing work.gpbdjfttbjd.zsftcmnmkdb 
Post processing for work.gpbdjfttbjd.zsftcmnmkdb
Post processing for work.initcfg_xe.behavior
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xd.vhd":56:28:56:37|Synthesizing work.initcfg_xd.behavior 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xd.vhd":10:0:10:10|Synthesizing work.dxwqxgdccxc.cmvhvtvbzkh 
Post processing for work.dxwqxgdccxc.cmvhvtvbzkh
Post processing for work.initcfg_xd.behavior
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xc.vhd":155:28:155:37|Synthesizing work.initcfg_xc.behavior 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xc.vhd":10:0:10:10|Synthesizing work.ffppvfwnggt.zgctkkxfnjk 
Post processing for work.ffppvfwnggt.zgctkkxfnjk
Post processing for work.initcfg_xc.behavior
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xb.vhd":70:7:70:16|Synthesizing work.initcfg_xb.behavior 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xb.vhd":11:7:11:17|Synthesizing work.wbsfnwwctpn.mmwvfpfbppr 
@N: CD231 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xb.vhd":23:20:23:21|Using onehot encoding for type cjhswcdjptj (cqppqjpknwn="100000000")
Post processing for work.wbsfnwwctpn.mmwvfpfbppr
@N: CL201 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xb.vhd":47:30:47:31|Trying to extract state machine for register crpwsdfhcqq
Extracted state machine for register crpwsdfhcqq
State machine has 9 reachable states with original encodings of:
   000000001
   000000010
   000000100
   000001000
   000010000
   000100000
   001000000
   010000000
   100000000
Post processing for work.initcfg_xb.behavior
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xa.vhd":57:7:57:16|Synthesizing work.initcfg_xa.behavior 
@N: CD630 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xa.vhd":11:7:11:17|Synthesizing work.stnpfdkggvx.zkzbcmxmrjf 
@N: CD231 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xa.vhd":21:20:21:21|Using onehot encoding for type bfjbqwgdgfk (tvzdqnwfvfh="10000000")
Post processing for work.stnpfdkggvx.zkzbcmxmrjf
@N: CL201 :"D:\RTC_Demo\smartgen\common\vhdl\initcfg_xa.vhd":41:47:41:48|Trying to extract state machine for register mwtvnzdkmwm
Extracted state machine for register mwtvnzdkmwm
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Post processing for work.initcfg_xa.behavior
Post processing for work.grwzcnqmqzm.mjtkskcsjhk
Post processing for work.initcfg.behavior
Post processing for work.nvm_analog_init_wrapper.def_arch
Post processing for work.nvm_analog.def_arch
@W: CL168 :"D:\RTC_Demo\smartgen\NVM_analog\NVM_analog.vhd":410:4:410:18|Pruning instance VCC_power_inst1 - not in use ... 
@N: CD630 :"D:\RTC_Demo\smartgen\XTAL_RTC\XTAL_RTC.vhd":7:7:7:14|Synthesizing work.xtal_rtc.def_arch 
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":4759:10:4759:15|Synthesizing work.clksrc.syn_black_box 
Post processing for work.clksrc.syn_black_box
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":5759:10:5759:15|Synthesizing work.xtlosc.syn_black_box 
Post processing for work.xtlosc.syn_black_box
Post processing for work.xtal_rtc.def_arch
@N: CD630 :"D:\RTC_Demo\hdl\LCD_DIS.vhd":34:7:34:13|Synthesizing work.lcd_dis.def_arch 
@W: CG296 :"D:\RTC_Demo\hdl\LCD_DIS.vhd":107:16:107:22|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\RTC_Demo\hdl\LCD_DIS.vhd":122:14:122:19|Referenced variable lcd_en is not in sensitivity list
@N: CD630 :"D:\RTC_Demo\hdl\Data_to_LCD.vhd":9:7:9:9|Synthesizing work.lcd.behavioural 
@N: CD232 :"D:\RTC_Demo\hdl\Data_to_LCD.vhd":30:16:30:17|Using gray code encoding for type state_type
Post processing for work.lcd.behavioural
@N: CL201 :"D:\RTC_Demo\hdl\Data_to_LCD.vhd":55:2:55:3|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 38 reachable states with original encodings of:
   000000
   000001
   000010
   000011
   000100
   000101
   000110
   000111
   001000
   001001
   001010
   001011
   001100
   001101
   001110
   001111
   010000
   010001
   010010
   010011
   010100
   010101
   010110
   010111
   011000
   011001
   011010
   011011
   011100
   011101
   011110
   011111
   110000
   110001
   110010
   110011
   110110
   110111
@W: CL234 :"D:\RTC_Demo\hdl\Data_to_LCD.vhd":14:3:14:10|Input port bits <7 to 4> of rtc_year(7 downto 0) are unused 
@W: CL234 :"D:\RTC_Demo\hdl\Data_to_LCD.vhd":16:7:16:14|Input port bits <7 to 6> of rtc_date(7 downto 0) are unused 
@W: CL234 :"D:\RTC_Demo\hdl\Data_to_LCD.vhd":17:3:17:11|Input port bits <7 to 5> of rtc_hours(7 downto 0) are unused 
@W: CL209 :"D:\RTC_Demo\hdl\Data_to_LCD.vhd":18:7:18:17|Input port bit <7> of rtc_minutes(7 downto 0) is unused 
@W: CL209 :"D:\RTC_Demo\hdl\Data_to_LCD.vhd":19:7:19:17|Input port bit <7> of rtc_seconds(7 downto 0) is unused 
@N: CD630 :"D:\RTC_Demo\hdl\my_clk_divider.vhd":6:7:6:17|Synthesizing work.clk_divider.def_arch 
@N: CD630 :"D:\RTC_Demo\hdl\clockdiv.vhd":5:7:5:14|Synthesizing work.clockdiv.behavioural 
Post processing for work.clockdiv.behavioural
Post processing for work.clk_divider.def_arch
@W: CL168 :"D:\RTC_Demo\hdl\my_clk_divider.vhd":27:8:27:14|Pruning instance GEN_label.23.clk_div - not in use ... 
@W: CL168 :"D:\RTC_Demo\hdl\my_clk_divider.vhd":27:8:27:14|Pruning instance GEN_label.22.clk_div - not in use ... 
@W: CL168 :"D:\RTC_Demo\hdl\my_clk_divider.vhd":27:8:27:14|Pruning instance GEN_label.21.clk_div - not in use ... 
@W: CL168 :"D:\RTC_Demo\hdl\my_clk_divider.vhd":27:8:27:14|Pruning instance GEN_label.20.clk_div - not in use ... 
@W: CL168 :"D:\RTC_Demo\hdl\my_clk_divider.vhd":27:8:27:14|Pruning instance GEN_label.19.clk_div - not in use ... 
@W: CL168 :"D:\RTC_Demo\hdl\my_clk_divider.vhd":27:8:27:14|Pruning instance GEN_label.18.clk_div - not in use ... 
@W: CL168 :"D:\RTC_Demo\hdl\my_clk_divider.vhd":27:8:27:14|Pruning instance GEN_label.17.clk_div - not in use ... 
@W: CL168 :"D:\RTC_Demo\hdl\my_clk_divider.vhd":27:8:27:14|Pruning instance GEN_label.16.clk_div - not in use ... 
@W: CL168 :"D:\RTC_Demo\hdl\my_clk_divider.vhd":27:8:27:14|Pruning instance GEN_label.15.clk_div - not in use ... 
@W: CL168 :"D:\RTC_Demo\hdl\my_clk_divider.vhd":27:8:27:14|Pruning instance GEN_label.14.clk_div - not in use ... 
Post processing for work.lcd_dis.def_arch
@N: CD630 :"D:\RTC_Demo\hdl\RTC_calendar.vhd":36:7:36:18|Synthesizing work.rtc_calendar.def_arch 
@N: CD232 :"D:\RTC_Demo\hdl\RTC_calendar.vhd":124:17:124:18|Using gray code encoding for type rtccal_type
@N: CD364 :"D:\RTC_Demo\hdl\RTC_calendar.vhd":420:21:420:29|Removed redundant assignment
@N: CD630 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":7:7:7:17|Synthesizing work.rip_count32.def_arch 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <0> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <1> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <2> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <3> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <4> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <5> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <6> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <7> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <8> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <9> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <10> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <11> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <12> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <13> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <14> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <15> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <16> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <17> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <18> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <19> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <20> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <21> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <22> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <23> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <24> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <25> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <26> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <27> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <28> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":42:11:42:13|Bit <29> of signal clk is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <1> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <2> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <3> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <4> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <5> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <6> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <7> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <8> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <9> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <10> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <11> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <12> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <13> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <14> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <15> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <16> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <17> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <18> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <19> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <20> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <21> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <22> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <23> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <24> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <25> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <26> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <27> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <28> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <29> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <30> of signal din is undriven 
@W: CD639 :"D:\RTC_Demo\hdl\RIP_COUNT32.vhd":51:11:51:13|Bit <31> of signal din is undriven 
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":1736:10:1736:17|Synthesizing work.dfn1e1c0.syn_black_box 
Post processing for work.dfn1e1c0.syn_black_box
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":3554:10:3554:12|Synthesizing work.mx2.syn_black_box 
Post processing for work.mx2.syn_black_box
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":3563:10:3563:13|Synthesizing work.mx2a.syn_black_box 
Post processing for work.mx2a.syn_black_box
@N: CD630 :"D:\RTC_Demo\smartgen\equal0\equal0.vhd":7:7:7:12|Synthesizing work.equal0.def_arch 
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":61:10:61:14|Synthesizing work.and3c.syn_black_box 
Post processing for work.and3c.syn_black_box
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":34:10:34:13|Synthesizing work.and3.syn_black_box 
Post processing for work.and3.syn_black_box
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":3650:10:3650:13|Synthesizing work.nor2.syn_black_box 
Post processing for work.nor2.syn_black_box
Post processing for work.equal0.def_arch
Post processing for work.rip_count32.def_arch
Post processing for work.rtc_calendar.def_arch
@W: CL171 :"D:\RTC_Demo\hdl\RTC_calendar.vhd":375:1:375:2|Pruning Register bit <7> of numdays_month(7 downto 0)  
@W: CL171 :"D:\RTC_Demo\hdl\RTC_calendar.vhd":375:1:375:2|Pruning Register bit <6> of numdays_month(7 downto 0)  
@N: CL201 :"D:\RTC_Demo\hdl\RTC_calendar.vhd":375:1:375:2|Trying to extract state machine for register RTCcal_present
Extracted state machine for register RTCcal_present
State machine has 29 reachable states with original encodings of:
   00000
   00001
   00010
   00011
   00100
   00101
   00110
   00111
   01000
   01001
   01010
   01011
   01100
   01101
   01110
   01111
   10010
   10100
   10101
   10110
   10111
   11000
   11001
   11010
   11011
   11100
   11101
   11110
   11111
@W: CL159 :"D:\RTC_Demo\hdl\RTC_calendar.vhd":42:2:42:7|Input clk1hz is unused
@N: CD630 :"D:\RTC_Demo\smartgen\Shift8_reg\Shift8_reg.vhd":7:7:7:16|Synthesizing work.shift8_reg.def_arch 
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":1669:10:1669:15|Synthesizing work.dfn1c1.syn_black_box 
Post processing for work.dfn1c1.syn_black_box
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":1040:10:1040:13|Synthesizing work.buff.syn_black_box 
Post processing for work.buff.syn_black_box
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":2236:10:2236:12|Synthesizing work.inv.syn_black_box 
Post processing for work.inv.syn_black_box
Post processing for work.shift8_reg.def_arch
@N: CD630 :"D:\RTC_Demo\smartgen\VR_mon\VR_mon.vhd":7:7:7:12|Synthesizing work.vr_mon.def_arch 
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":4748:10:4748:14|Synthesizing work.vrpsm.syn_black_box 
Post processing for work.vrpsm.syn_black_box
Post processing for work.vr_mon.def_arch
@W: CL168 :"D:\RTC_Demo\smartgen\VR_mon\VR_mon.vhd":34:4:34:12|Pruning instance VCC_1_net - not in use ... 
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":1182:10:1182:15|Synthesizing work.clkint.syn_black_box 
Post processing for work.clkint.syn_black_box
@N: CD630 :"D:\RTC_Demo\smartgen\PLL_100_10\PLL_100_10.vhd":7:7:7:16|Synthesizing work.pll_100_10.def_arch 
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":4892:10:4892:12|Synthesizing work.pll.syn_black_box 
Post processing for work.pll.syn_black_box
Post processing for work.pll_100_10.def_arch
@N: CD630 :"D:\RTC_Demo\smartgen\RCO\RCO.vhd":7:7:7:9|Synthesizing work.rco.def_arch 
@N: CD630 :"D:\Libero71\Synplify\Synplify_85B\lib\proasic\fusion.vhd":4866:10:4866:14|Synthesizing work.rcosc.syn_black_box 
Post processing for work.rcosc.syn_black_box
Post processing for work.rco.def_arch
Post processing for work.rtc_demo.def_arch
@W: CL170 :"D:\RTC_Demo\hdl\RTC_demo.vhd":365:2:365:3|Pruning bit <15> of RTCcount(15 downto 0) - not in use ... 
@W: CL170 :"D:\RTC_Demo\hdl\RTC_demo.vhd":432:2:432:3|Pruning bit <7> of count(7 downto 0) - not in use ... 
@END
Process took 0h:00m:10s realtime, 0h:00m:10s cputime
# Thu Jun 22 15:22:58 2006

###########################################################[
Synplicity Proasic Technology Mapper, Version 8.4.0.p, Build 075R, Built Mar  8 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Version 8.5B
@W: BN227 |This data was produced by a restricted version of Synplicity software. The results contain Synplicity IP and are not licensed to be used for production design work or design services
@N: MF249 |Running in 32-bit mode.
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK0": remove clock marking
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK1": remove clock marking
@W: BN154 |View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed


@W: MO129 :"d:\rtc_demo\hdl\rtc_calendar.vhd":375:1:375:2|Sequential instance reg_loadrtc has been reduced to a combinational gate by constant propagation
Automatic dissolve at startup in view:work.RIP_COUNT32(def_arch) of \$1I149(equal0)
Automatic dissolve at startup in view:work.RTC_calendar(def_arch) of rtccount(RIP_COUNT32)
@W: BN116 :"d:\rtc_demo\hdl\rtc_calendar.vhd":375:1:375:2|Removing sequential instance rreg_loadrtc of view:PrimLib.dffr(prim) because there are no references to its outputs 
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.6.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.5.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.10.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.2.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.4.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.9.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.13.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.1.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.8.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.12.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.11.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.3.clk_div(clockdiv)
Automatic dissolve at startup in view:work.CLK_DIVIDER(def_arch) of GEN_label.7.clk_div(clockdiv)
Automatic dissolve at startup in view:work.LCD_DIS(def_arch) of CLK_DIVIDER_intance(CLK_DIVIDER)
Automatic dissolve at startup in view:work.INITCFG_XF(behavior) of u_jhmkpjjmdkx(jhmkpjjmdkx)
Automatic dissolve at startup in view:work.grwzcnqmqzm(mjtkskcsjhk) of user_clk_sel(INITCFG_XF)
Automatic dissolve at startup in view:work.Analog_RTC(def_arch) of Analog_RTC_assc_ram_inst(Analog_RTC_assc_ram)
Automatic dissolve at startup in view:work.Analog_RTC(def_arch) of Analog_RTC_smev_ram_inst(Analog_RTC_smev_ram)
Automatic dissolve at startup in view:work.Analog_RTC(def_arch) of Analog_RTC_smtr_ram_inst(Analog_RTC_smtr_ram)
Automatic dissolve at startup in view:work.RTC_demo(def_arch) of XTALRTC(XTAL_RTC)
Automatic dissolve at startup in view:work.RTC_demo(def_arch) of sreg8(Shift8_reg)
Automatic dissolve at startup in view:work.RTC_demo(def_arch) of Vreg(VR_mon)
Automatic dissolve at startup in view:work.RTC_demo(def_arch) of PLL_acm(PLL_100_10)
Automatic dissolve at startup in view:work.RTC_demo(def_arch) of RC_osc(RCO)
@W: MO129 :"d:\rtc_demo\hdl\rtc_calendar.vhd":375:1:375:2|Sequential instance rr_loadrtc has been reduced to a combinational gate by constant propagation
@W: MO129 :"d:\rtc_demo\smartgen\common\vhdl\initcfg_xf.vhd":29:30:29:31|Sequential instance user_clk_sel.u_jhmkpjjmdkx.bmnfdkrhvvn has been reduced to a combinational gate by constant propagation
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
@N: MF238 :"d:\rtc_demo\hdl\rtc_demo.vhd":435:12:435:20|Found 7 bit incrementor, 'un2_count[6:0]'
@N: MF238 :"d:\rtc_demo\hdl\rtc_demo.vhd":368:15:368:26|Found 15 bit incrementor, 'un6_rtccount[14:0]'
Encoding state machine work.RTC_calendar(def_arch)-RTCcal_present[0:28]
original code -> new code
   00000 -> 00000
   00001 -> 00001
   00010 -> 00010
   00011 -> 00011
   00100 -> 00100
   00101 -> 00101
   00110 -> 00110
   00111 -> 00111
   01000 -> 01000
   01001 -> 01001
   01010 -> 01010
   01011 -> 01011
   01100 -> 01100
   01101 -> 01101
   01110 -> 01110
   01111 -> 01111
   10010 -> 10010
   10100 -> 10100
   10101 -> 10101
   10110 -> 10110
   10111 -> 10111
   11000 -> 11000
   11001 -> 11001
   11010 -> 11010
   11011 -> 11011
   11100 -> 11100
   11101 -> 11101
   11110 -> 11110
   11111 -> 11111
@N: MF238 :"d:\rtc_demo\hdl\rtc_calendar.vhd":522:33:522:59|Found 4 bit incrementor, 'un25_count_date[3:0]'
@N: MF238 :"d:\rtc_demo\hdl\rtc_calendar.vhd":534:34:534:61|Found 4 bit incrementor, 'un22_count_month[3:0]'
@N: MF238 :"d:\rtc_demo\hdl\rtc_calendar.vhd":540:32:540:58|Found 4 bit incrementor, 'un11_count_year[3:0]'
@N: MF238 :"d:\rtc_demo\hdl\rtc_calendar.vhd":474:35:474:64|Found 4 bit incrementor, 'un23_count_seconds[3:0]'
@N: MF238 :"d:\rtc_demo\hdl\rtc_calendar.vhd":486:35:486:64|Found 4 bit incrementor, 'un24_count_minutes[3:0]'
@N: MF238 :"d:\rtc_demo\hdl\rtc_calendar.vhd":503:33:503:60|Found 4 bit incrementor, 'un30_count_hours[3:0]'
Encoding state machine work.lcd(behavioural)-state[0:37]
original code -> new code
   000000 -> 000000
   000001 -> 000001
   000010 -> 000010
   000011 -> 000011
   000100 -> 000100
   000101 -> 000101
   000110 -> 000110
   000111 -> 000111
   001000 -> 001000
   001001 -> 001001
   001010 -> 001010
   001011 -> 001011
   001100 -> 001100
   001101 -> 001101
   001110 -> 001110
   001111 -> 001111
   010000 -> 010000
   010001 -> 010001
   010010 -> 010010
   010011 -> 010011
   010100 -> 010100
   010101 -> 010101
   010110 -> 010110
   010111 -> 010111
   011000 -> 011000
   011001 -> 011001
   011010 -> 011010
   011011 -> 011011
   011100 -> 011100
   011101 -> 011101
   011110 -> 011110
   011111 -> 011111
   110000 -> 110000
   110001 -> 110001
   110010 -> 110010
   110011 -> 110011
   110110 -> 110110
   110111 -> 110111
Encoding state machine work.stnpfdkggvx(zkzbcmxmrjf)-mwtvnzdkmwm[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine work.wbsfnwwctpn(mmwvfpfbppr)-crpwsdfhcqq[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
@W: MO129 :"d:\rtc_demo\smartgen\common\vhdl\initcfg_xb.vhd":47:30:47:31|Sequential instance NVManalog.NVM_analog_init_wrapper_inst.U0.u_grwzcnqmqzm.save_fsm.u_wbsfnwwctpn.qmdjrgthbvj has been reduced to a combinational gate by constant propagation
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
Encoding state machine work.cwgmnvwgkwq(wzrwkfmxjkf)-zwnnqcvfccb[0:14]
original code -> new code
   000000000000001 -> 000000000000001
   000000000000010 -> 000000000000010
   000000000000100 -> 000000000000100
   000000000001000 -> 000000000001000
   000000000010000 -> 000000000010000
   000000000100000 -> 000000000100000
   000000001000000 -> 000000001000000
   000000010000000 -> 000000010000000
   000000100000000 -> 000000100000000
   000001000000000 -> 000001000000000
   000010000000000 -> 000010000000000
   000100000000000 -> 000100000000000
   001000000000000 -> 001000000000000
   010000000000000 -> 010000000000000
   100000000000000 -> 100000000000000
Encoding state machine work.ccfdxrhchsz(djzfpsxghmt)-frcskdnwvmx[0:11]
original code -> new code
   000000000001 -> 000000000001
   000000000010 -> 000000000010
   000000000100 -> 000000000100
   000000001000 -> 000000001000
   000000010000 -> 000000010000
   000000100000 -> 000000100000
   000001000000 -> 000001000000
   000010000000 -> 000010000000
   000100000000 -> 000100000000
   001000000000 -> 001000000000
   010000000000 -> 010000000000
   100000000000 -> 100000000000
Encoding state machine work.nbnjbfrkqwq(qhrkzzskhwz)-tkcbxxqbtfx[0:17]
original code -> new code
   000000000000000001 -> 000000000000000001
   000000000000000010 -> 000000000000000010
   000000000000000100 -> 000000000000000100
   000000000000001000 -> 000000000000001000
   000000000000010000 -> 000000000000010000
   000000000000100000 -> 000000000000100000
   000000000001000000 -> 000000000001000000
   000000000010000000 -> 000000000010000000
   000000000100000000 -> 000000000100000000
   000000001000000000 -> 000000001000000000
   000000010000000000 -> 000000010000000000
   000000100000000000 -> 000000100000000000
   000001000000000000 -> 000001000000000000
   000010000000000000 -> 000010000000000000
   000100000000000000 -> 000100000000000000
   001000000000000000 -> 001000000000000000
   010000000000000000 -> 010000000000000000
   100000000000000000 -> 100000000000000000
@N: MF176 |Default generator successful 
@N: MF179 :"d:\rtc_demo\smartgen\common\vhdl\smev.vhd":173:22:173:51|Found 12 bit by 12 bit '<' comparator, 'pvtdpmmqdpp.un2_pbzxzjhqhwz'
@N: MF238 :"d:\rtc_demo\smartgen\common\vhdl\smev.vhd":183:30:183:53|Found 5 bit incrementor, 'un3_ckghxwbsztp[4:0]'
@W: MO129 :"d:\rtc_demo\smartgen\common\vhdl\initcfg_xf.vhd":32:18:32:19|Sequential instance user_clk_sel.u_jhmkpjjmdkx.zmbsbbtjszd has been reduced to a combinational gate by constant propagation
@W: MO129 :"d:\rtc_demo\smartgen\common\vhdl\initcfg_xf.vhd":32:18:32:19|Sequential instance user_clk_sel.u_jhmkpjjmdkx.cjjcvbqtckq has been reduced to a combinational gate by constant propagation
Automatic dissolve during optimization of view:work.RTC_calendar(def_arch) of un18_count_date_1(PM_ADDC__0_2_AFS600)
Automatic dissolve during optimization of view:work.INITCFG(behavior) of u_grwzcnqmqzm(grwzcnqmqzm)
Automatic dissolve during optimization of view:work.NVM_analog_init_wrapper(def_arch) of U0(INITCFG)
Automatic dissolve during optimization of view:work.NVM_analog(def_arch) of NVM_analog_init_wrapper_inst(NVM_analog_init_wrapper)
Automatic dissolve during optimization of view:work.RTC_demo(def_arch) of LCD_DIS_inst(LCD_DIS)

Finished factoring (Time elapsed 0h:00m:11s; Memory used current: 36MB peak: 37MB)
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":111:38:111:39|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.rhjxdmgzftc[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":111:38:111:39|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.rhjxdmgzftc[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[31] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[30] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[29] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[28] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[27] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[26] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[25] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[24] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[23] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[22] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[21] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[20] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[19] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[18] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[17] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[16] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[15] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[14] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[13] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[12] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[11] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[10] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[9] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[8] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[7] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[6] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[5] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[4] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[3] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\smtr.vhd":123:36:123:37|Removing sequential instance AnalogRTC.Analog_RTC_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\assc.vhd":170:38:170:39|Removing sequential instance AnalogRTC.Analog_RTC_assc_wrapper_inst.U0.u_cwgmnvwgkwq.rgqpfbkzbqs of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\assc.vhd":299:42:299:43|Removing sequential instance AnalogRTC.Analog_RTC_assc_wrapper_inst.U0.u_cwgmnvwgkwq.fbqggfmhjcw of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W: BN116 :"d:\rtc_demo\smartgen\common\vhdl\initcfg_xb.vhd":51:66:52:12|Removing sequential instance NVManalog.NVM_analog_init_wrapper_inst.U0.u_grwzcnqmqzm.save_fsm.u_wbsfnwwctpn.crpwsdfhcqq[8] of view:PrimLib.dffs(prim) because there are no references to its outputs 
@W: MO129 :"d:\rtc_demo\smartgen\common\vhdl\initcfg_xb.vhd":42:27:42:54|Sequential instance NVManalog.NVM_analog_init_wrapper_inst.U0.u_grwzcnqmqzm.save_fsm.u_wbsfnwwctpn.crpwsdfhcqq[6] has been reduced to a combinational gate by constant propagation

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:12s; Memory used current: 37MB peak: 38MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:13s; Memory used current: 37MB peak: 38MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:13s; Memory used current: 37MB peak: 38MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:13s; Memory used current: 37MB peak: 38MB)

Finished preparing to map (Time elapsed 0h:00m:15s; Memory used current: 38MB peak: 39MB)
Promoting Net INIT_DONE_c on CLKINT  I_266
Promoting Net AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3] on CLKINT  I_267
Promoting Net RTC_cal.RTCcal_present[2] on CLKINT  I_268
Replicating RTC_cal.N_918, fanout 19 segments 2
Replicating RTC_cal.N_413, fanout 41 segments 3
Replicating RTC_cal.un1_rtc_init, fanout 59 segments 4
Buffering SW2_c, fanout 28 segments 2
Buffering SW1_c, fanout 34 segments 3
Replicating RTC_cal.RTCcal_present[4], fanout 33 segments 3
Replicating RTC_cal.RTCcal_present[3], fanout 23 segments 2
Replicating RTC_cal.RTCcal_present[1], fanout 35 segments 3
Replicating RTC_cal.RTCcal_present[0], fanout 39 segments 3
Buffering RTC_cal.rtccount.\$1N156, fanout 32 segments 2
Replicating RTC_cal.count_ld, fanout 64 segments 4
Replicating LCD_DIS_inst.lcd_instance.state[5], fanout 20 segments 2
Replicating LCD_DIS_inst.lcd_instance.state[4], fanout 19 segments 2
Replicating LCD_DIS_inst.lcd_instance.state[2], fanout 26 segments 2
Replicating LCD_DIS_inst.lcd_instance.state[0], fanout 24 segments 2
Replicating NVManalog.NVM_analog_init_wrapper_inst.U0.u_grwzcnqmqzm.user_control.u_ffppvfwnggt.N_4924, fanout 18 segments 2
Replicating NVManalog.NVM_analog_init_wrapper_inst.U0.u_grwzcnqmqzm.gpbbjwsprsj[2], fanout 17 segments 2
Replicating NVManalog.NVM_analog_init_wrapper_inst.U0.u_grwzcnqmqzm.gpbbjwsprsj[0], fanout 19 segments 2
Replicating NVManalog.NVM_analog_init_wrapper_inst.U0.u_grwzcnqmqzm.bfcqzvtnrcn, fanout 22 segments 2
Replicating AnalogRTC.Analog_RTC_assc_wrapper_inst.U0.u_cwgmnvwgkwq.jrdxqdwndbg[3], fanout 18 segments 2
Replicating AnalogRTC.Analog_RTC_assc_wrapper_inst.U0.u_cwgmnvwgkwq.jrdxqdwndbg[2], fanout 25 segments 2
Replicating AnalogRTC.Analog_RTC_assc_wrapper_inst.U0.u_cwgmnvwgkwq.jrdxqdwndbg[1], fanout 27 segments 2
Replicating AnalogRTC.Analog_RTC_assc_wrapper_inst.U0.u_cwgmnvwgkwq.jrdxqdwndbg[0], fanout 25 segments 2
Replicating AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.tkcbxxqbtfx[4], fanout 30 segments 2
Replicating AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rgmpzqrbghh, fanout 18 segments 2
Replicating AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[2], fanout 37 segments 3
Replicating AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[1], fanout 34 segments 3
Replicating AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[0], fanout 32 segments 2
Buffering LCD_DIS_inst.lcd_en, fanout 21 segments 2

Finished technology mapping (Time elapsed 0h:00m:16s; Memory used current: 42MB peak: 44MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:17s; Memory used current: 42MB peak: 44MB)

Added 6 Buffers
Added 35 Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:17s; Memory used current: 42MB peak: 44MB)
Writing Analyst data base D:\RTC_Demo\synthesis\RTC_demo.srm
Writing EDIF Netlist and constraint files
@W:"d:\rtc_demo\smartgen\pll_100_10\pll_100_10.vhd":47:4:47:7|Net ACM_CLK_c appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\smartgen\xtal_rtc\xtal_rtc.vhd":40:4:40:10|Net RTCCLK appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":443:4:443:19|Net CLK_net_9 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":193:4:193:19|Net CLK_net_27 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":400:4:400:19|Net CLK_net_19 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":467:4:467:18|Net CLK_net_4 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":185:4:185:18|Net CLK_net_5 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":336:4:336:19|Net CLK_net_11 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":297:4:297:19|Net CLK_net_21 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":205:4:205:19|Net CLK_net_15 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":253:4:253:19|Net CLK_net_14 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":169:4:169:19|Net CLK_net_25 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":233:4:233:19|Net CLK_net_24 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":344:4:344:19|Net CLK_net_10 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":495:4:495:19|Net CLK_net_12 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":305:4:305:19|Net CLK_net_20 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":471:4:471:19|Net CLK_net_22 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":451:4:451:18|Net CLK_net_6 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":197:4:197:19|Net CLK_net_28 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":213:4:213:18|Net CLK_net_1 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":149:4:149:18|Net CLK_net_7 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":360:4:360:19|Net CLK_net_29 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":109:4:109:18|Net CLK_net_2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":229:4:229:19|Net CLK_net_13 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":317:4:317:19|Net CLK_net_16 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":201:4:201:19|Net CLK_net_23 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":455:4:455:18|Net CLK_net_3 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":289:4:289:19|Net CLK_net_26 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":269:4:269:19|Net CLK_net_8 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":273:4:273:18|Net CLK[31] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":249:4:249:19|Net CLK_net_18 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":257:4:257:18|Net Z\\CLK\\ appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\rip_count32.vhd":221:4:221:19|Net CLK_net_17 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net net[6] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net net[2] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net net[10] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net net[11] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net net[7] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net net[12] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net net[8] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net net[3] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net net[1] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net net[9] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net net[4] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net net[5] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\rtc_demo\hdl\clockdiv.vhd":20:8:20:9|Net lcd_en appears to be a clock source which was not identified. Assuming default frequency. 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jun 22 15:23:20 2006
#


Top view:               RTC_demo
Library name:           fusion
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree )
Requested Frequency:    1.0 MHz
Wire load mode:         top
Wire load model:        fusion
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 949.002

                   Requested     Estimated     Requested     Estimated                 Clock      Clock           
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type       Group           
------------------------------------------------------------------------------------------------------------------
System             1.0 MHz       19.6 MHz      1000.000      50.998        949.002     system     default_clkgroup
==================================================================================================================





Clock Relationships
*******************

Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------
========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                                             Starting                                                   Arrival            
Instance                                                                     Reference     Type         Pin     Net                     Time        Slack  
                                                                             Clock                                                                         
-----------------------------------------------------------------------------------------------------------------------------------------------------------
RTC_cal.RTCcal_present[2]                                                    System        DFN1C0       Q       RTCcal_present_0[2]     0.364       949.002
AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[0]       System        DFN1E0C0     Q       rdgwgtpkbgc[0]          0.364       949.747
AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc_0[0]     System        DFN1E0C0     Q       rdgwgtpkbgc_0[0]        0.364       950.075
AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnvtvdkcnpp[5]       System        DFN1C0       Q       bnvtvdkcnpp[5]          0.364       951.115
AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rqrqhcwpqdn[2]       System        DFN1E1C0     Q       rqrqhcwpqdn[2]          0.364       951.171
RTC_cal.RTCcal_present_0[3]                                                  System        DFN1C0       Q       RTCcal_present_0[3]     0.364       951.437
AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rqrqhcwpqdn[3]       System        DFN1E1C0     Q       rqrqhcwpqdn[3]          0.364       951.437
AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rqrqhcwpqdn[1]       System        DFN1E1C0     Q       rqrqhcwpqdn[1]          0.364       951.462
AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnvtvdkcnpp[2]       System        DFN1C0       Q       bnvtvdkcnpp[2]          0.364       951.564
AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnvtvdkcnpp[3]       System        DFN1C0       Q       bnvtvdkcnpp[3]          0.364       951.567
===========================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                Starting                                                     Required            
Instance                                                        Reference     Type       Pin       Net                       Time         Slack  
                                                                Clock                                                                            
-------------------------------------------------------------------------------------------------------------------------------------------------
RTC_cal.count_month[3]                                          System        DFN1C0     D         count_month_13[3]         999.590      949.002
RTC_cal.count_month[1]                                          System        DFN1C0     D         count_month_13[1]         999.590      949.018
RTC_cal.count_year[1]                                           System        DFN1C0     D         count_year_8[1]           999.590      949.070
RTC_cal.count_year[2]                                           System        DFN1C0     D         count_year_8[2]           999.590      949.070
RTC_cal.count_month[4]                                          System        DFN1C0     D         count_month_13[4]         999.590      949.118
RTC_cal.count_month[0]                                          System        DFN1C0     D         count_month_13[0]         999.590      949.127
RTC_cal.count_month[2]                                          System        DFN1C0     D         count_month_13[2]         999.590      949.142
RTC_cal.count_year[0]                                           System        DFN1C0     D         count_year_8[0]           999.590      949.179
RTC_cal.count_year[3]                                           System        DFN1C0     D         count_year_8[3]           999.590      949.194
AnalogRTC.Analog_RTC_smev_ram_inst.Analog_RTC_smev_ram_R0C0     System        RAM4K9     DINB1     EV_RAM_DI_B_net_net_6     998.930      949.747
=================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        1000.000
    - Setup time:                            0.410
    = Required time:                         999.590

    - Propagation time:                      50.588
    = Slack (critical) :                     949.002

    Number of logic level(s):                13
    Starting point:                          RTC_cal.RTCcal_present[2] / Q
    Ending point:                            RTC_cal.count_month[3] / D
    The start point is clocked by            System [rising] on pin CLK
    The end   point is clocked by            System [rising] on pin CLK

Instance / Net                                    Pin      Pin               Arrival     No. of    
Name                                   Type       Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
RTC_cal.RTCcal_present[2]              DFN1C0     Q        Out     0.364     0.364       -         
RTCcal_present_0[2]                    Net        -        -       0.844     -           1         
I_268                                  CLKINT     A        In      -         1.208       -         
I_268                                  CLKINT     Y        Out     0.100     1.308       -         
RTC_cal.RTCcal_present[2]              Net        -        -       7.298     -           66        
RTC_cal.ACMADDR_1_0_a3[6]              NOR2B      B        In      -         8.605       -         
RTC_cal.ACMADDR_1_0_a3[6]              NOR2B      Y        Out     0.351     8.956       -         
N_455                                  Net        -        -       1.982     -           3         
RTC_cal.RTC_act_i_o5_i_a2              NOR2A      B        In      -         10.938      -         
RTC_cal.RTC_act_i_o5_i_a2              NOR2A      Y        Out     0.232     11.170      -         
N_1022                                 Net        -        -       1.982     -           3         
RTC_cal.clr_sec_flag_i_o5              NOR3B      B        In      -         13.151      -         
RTC_cal.clr_sec_flag_i_o5              NOR3B      Y        Out     0.358     13.509      -         
N_414                                  Net        -        -       1.419     -           2         
RTC_cal.trigger_i_o5                   OR2B       B        In      -         14.929      -         
RTC_cal.trigger_i_o5                   OR2B       Y        Out     0.351     15.280      -         
N_421                                  Net        -        -       3.120     -           5         
RTC_cal.count_seconds_0_sqmuxa         OR2A       B        In      -         18.400      -         
RTC_cal.count_seconds_0_sqmuxa         OR2A       Y        Out     0.362     18.762      -         
count_seconds_0_sqmuxa                 Net        -        -       4.446     -           8         
RTC_cal.count_minutes_0_sqmuxa         OR2A       B        In      -         23.207      -         
RTC_cal.count_minutes_0_sqmuxa         OR2A       Y        Out     0.362     23.569      -         
count_minutes_0_sqmuxa                 Net        -        -       5.610     -           11        
RTC_cal.count_hours_3_sqmuxa           OR2A       B        In      -         29.179      -         
RTC_cal.count_hours_3_sqmuxa           OR2A       Y        Out     0.362     29.541      -         
count_hours_3_sqmuxa                   Net        -        -       5.610     -           11        
RTC_cal.count_date_0_sqmuxa_i_0_o2     OR2A       B        In      -         35.152      -         
RTC_cal.count_date_0_sqmuxa_i_0_o2     OR2A       Y        Out     0.362     35.514      -         
N_917                                  Net        -        -       6.400     -           14        
RTC_cal.count_month_0_sqmuxa_0_a2      NOR3B      C        In      -         41.914      -         
RTC_cal.count_month_0_sqmuxa_0_a2      NOR3B      Y        Out     0.276     42.190      -         
count_month_0_sqmuxa                   Net        -        -       4.887     -           9         
RTC_cal.count_month_12_r[3]            NOR3       C        In      -         47.077      -         
RTC_cal.count_month_12_r[3]            NOR3       Y        Out     0.416     47.493      -         
count_month_12[3]                      Net        -        -       0.844     -           1         
RTC_cal.count_month_13[3]              MX2        B        In      -         48.337      -         
RTC_cal.count_month_13[3]              MX2        Y        Out     0.325     48.662      -         
N_718                                  Net        -        -       0.844     -           1         
RTC_cal.count_month_13_r[3]            OA1A       C        In      -         49.505      -         
RTC_cal.count_month_13_r[3]            OA1A       Y        Out     0.239     49.744      -         
count_month_13[3]                      Net        -        -       0.844     -           1         
RTC_cal.count_month[3]                 DFN1C0     D        In      -         50.588      -         
===================================================================================================
Total path delay (propagation time + setup) of 50.998 is 4.869(9.5%) logic and 46.129(90.5%) route.



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Report for cell RTC_demo.def_arch
  Cell usage:
              cell count     area count*area
               MX2   372      1.0      372.0
            DFN1C0   220      1.0      220.0
             NOR2A   154      1.0      154.0
             NOR2B   143      1.0      143.0
          DFN1E1C0   128      1.0      128.0
              XOR2   116      1.0      116.0
          DFN1E0C0    94      1.0       94.0
              OR2B    85      1.0       85.0
              OR2A    80      1.0       80.0
            OUTBUF    75      0.0        0.0
              MX2C    65      1.0       65.0
              OR3B    60      1.0       60.0
             NOR3C    57      1.0       57.0
               VCC    54      0.0        0.0
               GND    54      0.0        0.0
              NOR2    54      1.0       54.0
              OR3A    46      1.0       46.0
             AOI1B    43      1.0       43.0
            DFN1C1    40      1.0       40.0
               OR2    39      1.0       39.0
              OA1A    39      1.0       39.0
             NOR3B    36      1.0       36.0
              OR3C    36      1.0       36.0
              AND3    34      1.0       34.0
              MX2A    32      1.0       32.0
               OR3    29      1.0       29.0
             XNOR2    27      1.0       27.0
              AO1A    25      1.0       25.0
              AND2    25      1.0       25.0
             NOR3A    24      1.0       24.0
              AO1B    20      1.0       20.0
               INV    19      1.0       19.0
             XNOR3    17      1.0       17.0
              AO1C    17      1.0       17.0
              NOR3    12      1.0       12.0
              AO13    12      1.0       12.0
              MX2B    12      1.0       12.0
              OA1B    11      1.0       11.0
               OA1    11      1.0       11.0
               AO1    10      1.0       10.0
             AND3C    10      1.0       10.0
              OA1C    10      1.0       10.0
              MAJ3     9      1.0        9.0
              XA1A     9      1.0        9.0
              AO1D     9      1.0        9.0
            DFN1P0     8      1.0        8.0
              MIN3     8      1.0        8.0
               XA1     8      1.0        8.0
              OAI1     8      1.0        8.0
              XOR3     8      1.0        8.0
              BUFF     8      1.0        8.0
              AO18     6      1.0        6.0
              XAI1     6      1.0        6.0
              AOI1     5      1.0        5.0
             AOI1A     5      1.0        5.0
            CLKINT     4      0.0        0.0
             INBUF     4      0.0        0.0
            RAM4K9     3      0.0        0.0
             AND2A     3      1.0        3.0
             NAND2     2      1.0        2.0
             AXOI5     2      1.0        2.0
              AX1C     2      1.0        2.0
             MAJ3X     2      1.0        2.0
              AXO2     2      1.0        2.0
          DFN1E0P0     2      1.0        2.0
              AX1A     2      1.0        2.0
               AX1     2      1.0        2.0
              XO1A     1      1.0        1.0
            CLKSRC     1      0.0        0.0
                AB     1      0.0        0.0
              AX1B     1      1.0        1.0
              AO16     1      1.0        1.0
            XTLOSC     1      0.0        0.0
               NVM     1      0.0        0.0
             AXOI7     1      1.0        1.0
               XO1     1      1.0        1.0
              XA1C     1      1.0        1.0
              AXO7     1      1.0        1.0
              XA1B     1      1.0        1.0
             AXOI4     1      1.0        1.0
             VRPSM     1      0.0        0.0
               PLL     1      0.0        0.0
             RCOSC     1      0.0        0.0
                   -----          ----------
             TOTAL  2590              2389.0
Mapper successful!
Process took 0h:00m:21s realtime, 0h:00m:18s cputime
# Thu Jun 22 15:23:20 2006

###########################################################]
