KEY LIBERO "7.1"
KEY CAPTURE "7.1.0.14"
KEY HDLTechnology "VHDL"
KEY VendorTechnology_Family "Fusion"
KEY VendorTechnology_Die "IR6X6M2"
KEY VendorTechnology_Package "fg256"
KEY ProjectLocation "D:\RTC_Demo"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "RTC_demo"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST FileManager
VALUE "<project>\hdl\clockdiv.vhd,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\hdl\Data_to_LCD.vhd,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\hdl\LCD_DIS.vhd,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\hdl\my_clk_divider.vhd,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\hdl\RIP_COUNT32.vhd,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\hdl\RTC_calendar.vhd,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\hdl\RTC_demo.vhd,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\constraint\RTC_demo.pdc,pdc"
STATE="utd"
ENDFILE
VALUE "<project>\stimulus\RTC_demo_tbench.vhd,tb_hdl"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\Shift8_reg\Shift8_reg.cxf,actgen_cxf"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\Shift8_reg\Shift8_reg.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\Shift8_reg\Shift8_reg.cxf"
ENDFILE
VALUE "<project>\smartgen\Shift8_reg\Shift8_reg.gen,gen"
STATE="utd"
PARENT="<project>\smartgen\Shift8_reg\Shift8_reg.cxf"
ENDFILE
VALUE "<project>\smartgen\Shift8_reg\Shift8_reg.log,log"
STATE="utd"
PARENT="<project>\smartgen\Shift8_reg\Shift8_reg.cxf"
ENDFILE
VALUE "<project>\smartgen\PLL_100_10\PLL_100_10.cxf,actgen_cxf"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\PLL_100_10\PLL_100_10.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\PLL_100_10\PLL_100_10.cxf"
ENDFILE
VALUE "<project>\smartgen\PLL_100_10\PLL_100_10.gen,gen"
STATE="utd"
PARENT="<project>\smartgen\PLL_100_10\PLL_100_10.cxf"
ENDFILE
VALUE "<project>\smartgen\PLL_100_10\PLL_100_10.log,log"
STATE="utd"
PARENT="<project>\smartgen\PLL_100_10\PLL_100_10.cxf"
ENDFILE
VALUE "<project>\smartgen\equal0\equal0.cxf,actgen_cxf"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\equal0\equal0.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\equal0\equal0.cxf"
ENDFILE
VALUE "<project>\smartgen\equal0\equal0.gen,gen"
STATE="utd"
PARENT="<project>\smartgen\equal0\equal0.cxf"
ENDFILE
VALUE "<project>\smartgen\equal0\equal0.log,log"
STATE="utd"
PARENT="<project>\smartgen\equal0\equal0.cxf"
ENDFILE
VALUE "<project>\smartgen\RCO\RCO.cxf,actgen_cxf"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\RCO\RCO.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\RCO\RCO.cxf"
ENDFILE
VALUE "<project>\smartgen\RCO\RCO.gen,gen"
STATE="utd"
PARENT="<project>\smartgen\RCO\RCO.cxf"
ENDFILE
VALUE "<project>\smartgen\RCO\RCO.log,log"
STATE="utd"
PARENT="<project>\smartgen\RCO\RCO.cxf"
ENDFILE
VALUE "<project>\smartgen\VR_mon\VR_mon.cxf,actgen_cxf"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\VR_mon\VR_mon.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\VR_mon\VR_mon.cxf"
ENDFILE
VALUE "<project>\smartgen\VR_mon\VR_mon.gen,gen"
STATE="utd"
PARENT="<project>\smartgen\VR_mon\VR_mon.cxf"
ENDFILE
VALUE "<project>\smartgen\VR_mon\VR_mon.log,log"
STATE="utd"
PARENT="<project>\smartgen\VR_mon\VR_mon.cxf"
ENDFILE
VALUE "<project>\smartgen\common\vhdl\assc.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\common\vhdl\smev.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\common\vhdl\smtr.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\common\vhdl\initcfg.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\NVM_analog\NVM_analog.cxf"
ENDFILE
VALUE "<project>\smartgen\common\vhdl\initcfg_xa.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\NVM_analog\NVM_analog.cxf"
ENDFILE
VALUE "<project>\smartgen\common\vhdl\initcfg_xb.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\NVM_analog\NVM_analog.cxf"
ENDFILE
VALUE "<project>\smartgen\common\vhdl\initcfg_xc.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\NVM_analog\NVM_analog.cxf"
ENDFILE
VALUE "<project>\smartgen\common\vhdl\initcfg_xd.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\NVM_analog\NVM_analog.cxf"
ENDFILE
VALUE "<project>\smartgen\common\vhdl\initcfg_xe.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\NVM_analog\NVM_analog.cxf"
ENDFILE
VALUE "<project>\smartgen\common\vhdl\initcfg_xf.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\NVM_analog\NVM_analog.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC.cxf,actgen_cxf"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_assc_wrapper.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_assc_ram.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smev_wrapper.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smtr_wrapper.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smev_ram.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smtr_ram.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_acm_rtc_ram_R0C0.mem,sim"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_acm_ram_R0C0.mem,sim"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_assc_ram_R0C0.mem,sim"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smev_ram_R0C0.mem,sim"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smtr_ram_R0C0.mem,sim"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC.log,log"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC.gen,gen"
STATE="utd"
PARENT="<project>\smartgen\Analog_RTC\Analog_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\NVM_analog\NVM_analog.cxf,actgen_cxf"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\NVM_analog\NVM_analog.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\NVM_analog\NVM_analog.cxf"
ENDFILE
VALUE "<project>\smartgen\NVM_analog\NVM_analog_init_wrapper.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\NVM_analog\NVM_analog.cxf"
ENDFILE
VALUE "<project>\smartgen\NVM_analog\NVM_analog.mem,sim"
STATE="utd"
PARENT="<project>\smartgen\NVM_analog\NVM_analog.cxf"
ENDFILE
VALUE "<project>\smartgen\NVM_analog\NVM_analog.log,log"
STATE="utd"
PARENT="<project>\smartgen\NVM_analog\NVM_analog.cxf"
ENDFILE
VALUE "<project>\smartgen\NVM_analog\NVM_analog.gen,gen"
STATE="utd"
PARENT="<project>\smartgen\NVM_analog\NVM_analog.cxf"
ENDFILE
VALUE "<project>\synthesis\RTC_demo.edn,syn_edn"
STATE="utd"
ENDFILE
VALUE "<project>\synthesis\RTC_demo_sdc.sdc,syn_sdc"
STATE="utd"
ENDFILE
VALUE "<project>\synthesis\RTC_demo.vhd,syn_hdl"
STATE="utd"
ENDFILE
VALUE "<project>\synthesis\RTC_demo_drc.rpt,log"
STATE="utd"
ENDFILE
VALUE "<project>\designer\impl1\RTC_demo.adb,adb"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\XTAL_RTC\XTAL_RTC.cxf,actgen_cxf"
STATE="utd"
ENDFILE
VALUE "<project>\smartgen\XTAL_RTC\XTAL_RTC.vhd,hdl"
STATE="utd"
PARENT="<project>\smartgen\XTAL_RTC\XTAL_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\XTAL_RTC\XTAL_RTC.gen,gen"
STATE="utd"
PARENT="<project>\smartgen\XTAL_RTC\XTAL_RTC.cxf"
ENDFILE
VALUE "<project>\smartgen\XTAL_RTC\XTAL_RTC.log,log"
STATE="utd"
PARENT="<project>\smartgen\XTAL_RTC\XTAL_RTC.cxf"
ENDFILE
VALUE "<project>\designer\impl1\RTC_demo.stp,stp"
STATE="utd"
ENDFILE
VALUE "<project>\designer\impl1\RTC_demo_fp\RTC_demo.pro,pro"
STATE="utd"
ENDFILE
VALUE "<project>\designer\impl1\RTC_demo.pro,pro"
STATE="utd"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST RecentFile
ENDLIST
LIST AssociatedStimulus
LIST RTC_demo
VALUE "<project>\stimulus\RTC_demo_tbench.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST NVM_analog
VALUE "<project>\smartgen\NVM_analog\NVM_analog.mem,sim"
VALUE "<project>\smartgen\NVM_analog\NVM_analog.mem,sim"
VALUE "<project>\smartgen\NVM_analog\NVM_analog.mem,sim"
ENDLIST
LIST Analog_RTC
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_acm_rtc_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_acm_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_assc_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smev_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smtr_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_acm_rtc_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_acm_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_assc_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smev_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smtr_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_acm_rtc_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_acm_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_acm_rtc_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_acm_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_assc_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smev_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smtr_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_acm_rtc_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_acm_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_assc_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smev_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\Analog_RTC\Analog_RTC_smtr_ram_R0C0.mem,sim"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=TRUE
CompilePackage=TRUE
IncludeWaveDo=FALSE
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
UpdateViewDrawIni=TRUE
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
Type=Synthesis
Profile=Synplify_82G
Tool=Synplify
Location=D:\Libero71\Synplify\Synplify_85B\bin\synplify.exe
AdditionalParameter=
Batch=FALSE
EndProfile
Type=Simulation
Profile=ModelSim
Tool=ModelSim
Location=D:\Libero71\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=FALSE
EndProfile
Type=Stimulus
Profile=WFL
Tool=WFL
Location=d:\Libero71\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=FALSE
EndProfile
Type=PhySynthesis
Profile=PALACE_1
Tool=PALACE
Location=d:\Libero70\PALACE\bin\palace_actel.exe
AdditionalParameter=
Batch=FALSE
EndProfile
Type=Program
Profile=FlashPro
Tool=FlashPro
Location=d:\Libero71\FlashPro\bin\FlashPro.exe
AdditionalParameter=
Batch=FALSE
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "RTC_demo"
LIST Impl1
LiberoState=Post_Layout
ideSTIMULUS=StateSuccess
ideSYNTHESIS=StateSuccess
ideDESIGNER=StateSuccess
LIST Files Out Of Date
RTC_demo.vhd
ENDLIST
LIST Files Up To Date
RTC_demo.edn
RTC_demo_sdc.sdc
RTC_demo.stp
RTC_demo.adb
ENDLIST
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST OODAdbs
ENDLIST
