--*******************************************************************
-- RTC Demo Design
-- Actel Corporation
-- Date: 2/3/2006
-- Design Description:
-- Using the Fusion device’s RTC, this application provides a count 
-- of seconds, minutes, hours, day of the week, day of the month, month,
-- and year. The month-ending date is automatically adjusted for months
-- with less than 31 days, including corrections for leap years. Moreover,
-- the FPGA core can be powered off to save power, and the RTC will continue 
-- to keep track of the time and date information.
--
--****************************************************************************
-- IMPORTANT-READ THESE TERMS CAREFULLY BEFORE UTILIZING THE INFORMATION
-- CONTAINED IN THIS APPLICATION NOTE. 
--
-- NO SUPPORT/NO WARRANTY. THE DESIGN FILES AND DOCUMENTATION ARE PROVIDED
-- WITHOUT SUPPORT OR WARRANTY OF ANY KIND. ACTEL IS NOT OBLIGATED TO 
-- PROVIDE UPDATES, BUG FIXES, OR TECHNICAL SUPPORT AND DISCLAIMS ALL 
-- WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE, AND WARRANTIES OF NON-INFRINGEMENT OF THE
-- RIGHTS OF THIRD PARTIES (INCLUDING, WITHOUT LIMITATION, RIGHTS UNDER PATENT,
-- COPYRIGHT, TRADE SECRET, OR OTHER INTELLECTUAL PROPERTY RIGHTS).  RECIPIENT
-- ACCEPTS THE APPLICATION NOTE DESIGN FILES AND DOCUMENTATION IN "AS-IS"
-- CONDITION.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.NUMERIC_BIT.all;
use ieee.STD_LOGIC_ARITH.all;


entity LCD_DIS is
    port(	CLK 			: in std_logic; --osc clock    
    		RS_LCD 		: out std_logic; --LCD signals
    		DATA_LCD 		: out std_logic_vector(7 downto 4); --LCD signals
    		EN_LCD 		: out std_logic; --LCD signals
    		R_nW_LCD 		: out std_logic; --LCD signals 
    		SW2      		: in std_logic;                   
    		RTC_year		: in std_logic_vector(7 downto 0);
    		RTC_month		: in std_logic_vector(7 downto 0);
    		RTC_date		: in std_logic_vector(7 downto 0);
		RTC_hours		: in std_logic_vector(7 downto 0); 
          RTC_minutes	: in std_logic_vector(7 downto 0); 
          RTC_seconds	: in std_logic_vector(7 downto 0);	    		
    		SW1 			: in std_logic --asyn_clr
    );
end LCD_DIS;

architecture DEF_ARCH of LCD_DIS is 

    component CLK_DIVIDER
        port(CLK, ACLR : in std_logic; DIVIDED_CLK : out std_logic);
    end component;

    component lcd
    Port (  lcd_data 	: out std_logic_vector (7 downto 4);
             clk        	: in std_logic;
		   reset      	: in std_logic;  -- active high
		   SW2      	: in std_logic;                   
		   RTC_year	: in std_logic_vector(7 downto 0);
		   RTC_month	: in std_logic_vector(7 downto 0);
		   RTC_date	: in std_logic_vector(7 downto 0);		   
		   RTC_hours	: in std_logic_vector(7 downto 0);
	        RTC_minutes	: in std_logic_vector(7 downto 0);
	        RTC_seconds	: in std_logic_vector(7 downto 0);		   		   
		   lcd_enable 	: out std_logic;
             lcd_rs 	: out std_logic;
 		   lcd_rw 	: out std_logic);
    end component;


    --divided clock signal
    signal clk_internal: std_logic;

     --counter signals that go to the LCD and LED
    signal LCD_net: std_logic_vector (7 downto 4);
    signal lcd_rw, lcd_rs, lcd_en : std_logic;          
    
  --  signal count_net: std_logic_vector (7 downto 0); 


begin 

--divide the 10 Mhz clock by 23
CLK_DIVIDER_intance : CLK_DIVIDER
      port map(CLK => CLK, ACLR => SW1, DIVIDED_CLK => clk_internal);

lcd_instance: lcd
    port map ( lcd_data 		=> LCD_net, 
    		     clk 			=> clk_internal, 
    		     reset 		=> SW1, 
    			lcd_enable 	=> lcd_en, 
    			lcd_rs 		=> lcd_rs, 
    			lcd_rw 		=> lcd_rw,
    			SW2      		=> SW2,      	
    			RTC_year		=> RTC_year,	
    			RTC_month		=> RTC_month,	
    			RTC_date		=> RTC_date,	    			
    			RTC_hours	     => RTC_hours,	 
    			RTC_minutes	=> RTC_minutes,
    			RTC_seconds	=> RTC_seconds
    			); 


clear_LCD_LED : process(SW1, LCD_net, lcd_rw, lcd_rs)
begin

if SW1='1' then
    R_nW_LCD <= '0';
    RS_LCD <= '0';
    EN_LCD <= '0';
    DATA_LCD(7) <='0';
    DATA_LCD(6) <='0';
    DATA_LCD(5) <='0';
    DATA_LCD(4) <='0';

else
    R_nW_LCD <= lcd_rw ;
    RS_LCD <= lcd_rs ;
    EN_LCD <= lcd_en;
    DATA_LCD(7) <=LCD_net(7);
    DATA_LCD(6) <=LCD_net(6);
    DATA_LCD(5) <=LCD_net(5);
    DATA_LCD(4) <=LCD_net(4);

end if;

end process clear_LCD_LED;


end DEF_ARCH; 
