-- Generated by WaveFormer Lite Version 10.04a at 13:51:55 on 2/3/2006
-- Stimulator for stimulus

-- Generation Settings:
--   Export type: Stimulus only (reactive export not enabled)

-- Clock Domains:

--   Unclocked
--   ---------
--     Signals:
--       SYS_RESET
--       POWER_down

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library fusion;
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    SYS_RESET : inout std_logic := '0';
    POWER_down : inout std_logic := '0';
    INIT_DONE : in std_logic := 'Z';
    VAREF : inout std_logic := 'Z';
    DATAVALID : in std_logic := 'Z';
    ASSC_DONE : in std_logic := 'Z';
    ASSC_CHSAT : in std_logic := 'Z';
    ASSC_CHLATD : in std_logic := 'Z';

    RS_LCD 		: in std_logic; --LCD signals
    DATA_LCD 		: in std_logic_vector(7 downto 4);
    EN_LCD 		: in std_logic;
    R_nW_LCD 		: in std_logic;  
    SW1    		: out std_logic;  

    XTAL1 		: inout std_logic := '0';
    ACM_CLK 		: in std_logic := 'Z';
    RTCCLK_out 	: in std_logic := 'Z';    		
    FPGAGOOD	 	: in std_logic;     
    PUCORE 	 	: in std_logic;
    PUB		 	: out std_logic;  	        	   	   	                
    SW2    		: out std_logic;                 
    RTC_act		: in std_logic;
    clk_78khz		: in std_logic;
    
    RTC_year : in std_logic_vector(7 downto 0) := "ZZZZZZZZ";
    RTC_month : in std_logic_vector(7 downto 0) := "ZZZZZZZZ";
    RTC_date : in std_logic_vector(7 downto 0) := "ZZZZZZZZ";
    RTC_day : in std_logic_vector(7 downto 0) := "ZZZZZZZZ";
    RTC_hours : in std_logic_vector(7 downto 0) := "ZZZZZZZZ";
    RTC_minutes : in std_logic_vector(7 downto 0) := "ZZZZZZZZ";
    RTC_seconds : in std_logic_vector(7 downto 0) := "ZZZZZZZZ");

end stimulus;

architecture STIMULATOR of stimulus is

--  -- Control Signal Declarations
--  signal tb_status : TStatus;
--  signal tb_ParameterInitFlag : boolean := false;
--
--  -- Parm Declarations
--  signal XTAL1_MinHL : time := 0 ns;
--  signal XTAL1_MaxHL : time := 0 ns;
--  signal XTAL1_MinLH : time := 0 ns;
--  signal XTAL1_MaxLH : time := 0 ns;
--  signal XTAL1_JFall : time := 0 ns;
--  signal XTAL1_JRise : time := 0 ns;
--  signal XTAL1_Duty : real := 0.0;
--  signal XTAL1_Period : time := 0 ns;
--  signal XTAL1_Offset : time := 0 ns;
--
--  -- Status Control block.
--
begin
--
--  process
--    variable good : boolean;
--  begin
--    wait until tb_ParameterInitFlag;
--    tb_status <= TB_ONCE;
--    wait for 19748 ns;
--    tb_status <= TB_DONE;
--    wait;
--  end process;
--
--  -- Parm Assignment Block
--  AssignParms : process
--    variable XTAL1_MinHL_real : real;
--    variable XTAL1_MaxHL_real : real;
--    variable XTAL1_MinLH_real : real;
--    variable XTAL1_MaxLH_real : real;
--    variable XTAL1_JFall_real : real;
--    variable XTAL1_JRise_real : real;
--    variable XTAL1_Duty_real : real;
--    variable XTAL1_Period_real : real;
--    variable XTAL1_Offset_real : real;
--  begin
--    XTAL1_MinHL_real := 0.0;
--    XTAL1_MinHL <= XTAL1_MinHL_real * 1 ns;
--    XTAL1_MaxHL_real := 0.0;
--    XTAL1_MaxHL <= XTAL1_MaxHL_real * 1 ns;
--    XTAL1_MinLH_real := 0.0;
--    XTAL1_MinLH <= XTAL1_MinLH_real * 1 ns;
--    XTAL1_MaxLH_real := 0.0;
--    XTAL1_MaxLH <= XTAL1_MaxLH_real * 1 ns;
--    XTAL1_JFall_real := 0.0;
--    XTAL1_JFall <= XTAL1_JFall_real * 1 ns;
--    XTAL1_JRise_real := 0.0;
--    XTAL1_JRise <= XTAL1_JRise_real * 1 ns;
--    XTAL1_Duty_real := 50.0;
--    XTAL1_Duty <= XTAL1_Duty_real;
--    XTAL1_Period_real := 30517.578;
--    XTAL1_Period <= XTAL1_Period_real * 1 ns;
--    XTAL1_Offset_real := 0.0;
--    XTAL1_Offset <= XTAL1_Offset_real * 1 ns;
--    tb_ParameterInitFlag <= true;
--    wait;
--  end process;
--
--  -- Clocks
--
--  -- Clock Instantiation
--  tb_XTAL1 : entity syncad_vhdl_lib.tb_clock_minmax
--    generic map (name => "tb_XTAL1",
--                initialize => true,
--                state1 => '1',
--                state2 => '0')
--    port map (tb_status,
--              XTAL1,
--              XTAL1_MinLH,
--              XTAL1_MaxLH,
--              XTAL1_MinHL,
--              XTAL1_MaxHL,
--              XTAL1_Offset,
--              XTAL1_Period,
--              XTAL1_Duty,
--              XTAL1_JRise,
--              XTAL1_JFall);
--
  -- Clocked Sequences            
  
  XTAL1	<= not XTAL1 after 3000 ns;

  -- Sequence: Unclocked
  Unclocked : process
  begin
--  wait for 300 ns;
	sw1		<= '0';
	sw2		<= '0';
  	POWER_down <= '0';
  	PUB		 <= '1';
  	sys_reset <= '0';
  	wait for 300 ns;
  	sys_reset <= '1';
  	wait for 300 ns;
  	sys_reset <= '0';
--  wait until (STATE_VARIABLE < 1.0);
  	wait for 4 ms;
  	POWER_down <= '1';
  	wait for 5 ms;	-- simulate a shutdown
  	
  	POWER_down <= '0';
  	sys_reset <= '0';
  	wait for 300 ns;
  	sys_reset <= '1';
  	wait for 300 ns;
  	sys_reset <= '0';
  	
  	wait for 3 ms;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library fusion;
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal SYS_RESET : std_logic;
  signal POWER_down : std_logic;
  signal INIT_DONE : std_logic;
  signal VAREF : std_logic;
  signal DATAVALID : std_logic;
  signal ASSC_DONE : std_logic;
  signal ASSC_CHSAT : std_logic;
  signal ASSC_CHLATD : std_logic;
  signal ACM_CLK : std_logic;
  signal RTCCLK_out : std_logic;
  signal RTC_year : std_logic_vector(7 downto 0);
  signal RTC_month : std_logic_vector(7 downto 0);
  signal RTC_date : std_logic_vector(7 downto 0);
  signal RTC_day : std_logic_vector(7 downto 0);
  signal RTC_hours : std_logic_vector(7 downto 0);
  signal RTC_minutes : std_logic_vector(7 downto 0);
  signal RTC_seconds : std_logic_vector(7 downto 0);
  signal XTAL1 : std_logic;
  signal RS_LCD 		: std_logic; --LCD signals      
  signal DATA_LCD 		: std_logic_vector(7 downto 4); 
  signal EN_LCD 		: std_logic;                    
  signal R_nW_LCD 		: std_logic;                    
  signal SW1    		: std_logic;       
  signal SW2    		: std_logic;            
  signal RTC_act		: std_logic;                    
--  signal toggle		: std_logic;                    
  signal clk_78khz		: std_logic;       
  signal FPGAGOOD	 	: std_logic;  
  signal PUCORE 	 	: std_logic;  
  signal PUB		 	: std_logic; 
  
  
  
               

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (SYS_RESET => SYS_RESET,
              POWER_down => POWER_down,
              INIT_DONE => INIT_DONE,
              VAREF => VAREF,
              DATAVALID => DATAVALID,
              ASSC_DONE => ASSC_DONE,
              ASSC_CHSAT => ASSC_CHSAT,
              ASSC_CHLATD => ASSC_CHLATD,
              ACM_CLK => ACM_CLK,
              clk_78khz	=> clk_78khz,
              RTCCLK_out => RTCCLK_out,
              RTC_year => RTC_year,
              RTC_month => RTC_month,
              RTC_date => RTC_date,
              RS_LCD 	=> RS_LCD,
              DATA_LCD 	=> DATA_LCD, 	
              EN_LCD 	=> EN_LCD, 	
              R_nW_LCD 	=> R_nW_LCD, 	
              SW1    	=> sw1,    	
              SW2    	=> sw2,
              RTC_act	=> RTC_act,
              FPGAGOOD	=> FPGAGOOD,	
              PUCORE 	=> PUCORE, 	
              PUB		=> PUB,		              	
--              toggle	=> toggle,
              RTC_day => RTC_day,
              RTC_hours => RTC_hours,
              RTC_minutes => RTC_minutes,
              RTC_seconds => RTC_seconds,
              XTAL1 => XTAL1);

  -- Instantiation of Model Under Test.
  RTC_demoSP1_0 : entity work.RTC_demoSP1
    port map (SYS_RESET => SYS_RESET,
              POWER_down => POWER_down,
              INIT_DONE => INIT_DONE,
              VAREF => VAREF,
              DATAVALID => DATAVALID,
              ASSC_DONE => ASSC_DONE,
              ASSC_CHSAT => ASSC_CHSAT,
              ASSC_CHLATD => ASSC_CHLATD,
              ACM_CLK => ACM_CLK,
              clk_78khz	=> clk_78khz,
              XTAL1 => XTAL1,
              RS_LCD 	=> RS_LCD,
              DATA_LCD 	=> DATA_LCD, 	
              EN_LCD 	=> EN_LCD, 	
              R_nW_LCD 	=> R_nW_LCD, 	
              SW1    	=> sw1,    	
              SW2    	=> sw2,
              RTC_act	=> RTC_act,	
		    FPGAGOOD	=> FPGAGOOD,	  
              PUCORE 	=> PUCORE, 	  
              PUB		=> PUB,		  
              RTCCLK_out => RTCCLK_out,
              RTC_year => RTC_year,
              RTC_month => RTC_month,
              RTC_date => RTC_date,
              RTC_day => RTC_day,
              RTC_hours => RTC_hours,
              RTC_minutes => RTC_minutes,
              RTC_seconds => RTC_seconds);
end tbGeneratedCode;
