Version:7.0.0.6
ACTGENU_CALL:1
BATCH:T
FAM:Fusion
OUTFORMAT:VHDL
LPMTYPE:LPM_PLL_STATIC
LPM_HINT:NONE
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:F
"DESDIR:D:/backup/Projects/G3SOC/StarterKit/PwrM/smartgen\PLL_100_10"
GEN_BEHV_MODULE:T
SMARTGEN_DIE:IR6X6M2
SMARTGEN_PACKAGE:fg256
 FIN:100.000
 CLKASRC:0
 FBDLY:1
 FBMUX:1
 XDLYSEL:0
 PRIMFREQ:10.000
 PPHASESHIFT:0
 DLYAVAL:1
 OAMUX:4
