Imported the files:
   D:\RTC_Demo\synthesis\RTC_demo.edn
   D:\RTC_Demo\constraint\RTC_demo.pdc

The Import command succeeded ( 00:00:21 )
The design D:\RTC_Demo\designer\impl1\RTC_demo.adb was last modified by software version
7.1.0.14.
Opened an existing Libero design D:\RTC_Demo\designer\impl1\RTC_demo.adb.
'BA_NAME' set to 'RTC_demo_ba'

The Execute Script command succeeded ( 00:00:00 )
=====================================================================
Parameters used to run compile:
===============================

Family      : Fusion
Device      : AFS600
Package     : 256 FBGA
Source      : D:\RTC_Demo\synthesis\RTC_demo.edn
              D:\RTC_Demo\constraint\RTC_demo.pdc
Format      : EDIF
Topcell     : RTC_demo
Speed grade : -2
Temp        : 0:25:70
Voltage     : 1.58:1.50:1.42

Keep Existing Physical Constraints : Yes
Keep Existing Timing Constraints   : Yes

pdc_abort_on_error                 : Yes
pdc_eco_display_unmatched_objects  : No
pdc_eco_max_warnings               : 10000

demote_globals                     : No
promote_globals                    : No
localclock_max_shared_instances    : 12
localclock_buffer_tree_max_fanout  : 12

combine_register                   : No
delete_buffer_tree                 : No

report_high_fanout_nets_limit      : 10

=====================================================================
Compile starts ...

Warning: CMP201: Net: PLL_acm/Core_GLB is floating
Warning: CMP201: Net: PLL_acm/Core_GLC is floating
Warning: CMP201: Net: PLL_acm/Core_LOCK is floating
Warning: CMP201: Net: PLL_acm/Core_YB is floating
Warning: CMP201: Net: PLL_acm/Core_YC is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_21 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_20 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_19 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_18 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_17 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_16 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_15 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_14 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_13 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_12 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_11 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_10 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_9 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_8 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_7 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_6 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_5 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_4 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_3 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_2 is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net_net_1 is floating
Warning: CMP201: Net: NVManalog/Z_NVM_DAT_FROM_net_ is floating
Warning: CMP201: Net: NVManalog/NVM_DAT_FROM_net[31] is floating
Warning: CMP201: Net: NVManalog/Z_NVM_STATUS_net_ is floating
Warning: CMP201: Net: NVManalog/NVM_STATUS_net[1] is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DACOUT0 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DACOUT1 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DACOUT2 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DACOUT3 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DACOUT4 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DACOUT5 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DACOUT6 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DACOUT7 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DACOUT8 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DACOUT9 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DATOUT0 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DATOUT1 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DATOUT2 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DATOUT3 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DATOUT4 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DATOUT5 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DATOUT6 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DATOUT7 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DATOUT8 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DATOUT9 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DAVOUT0 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DAVOUT1 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DAVOUT2 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DAVOUT3 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DAVOUT4 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DAVOUT5 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DAVOUT6 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DAVOUT7 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DAVOUT8 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_DAVOUT9 is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_RTCMATCH is floating
Warning: CMP201: Net: AnalogRTC/AB_INST_SAMPLE is floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smtr_ram_inst/Analog_RTC_smtr_ram_R0C0_DOUTA0 is
         floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smtr_ram_inst/Analog_RTC_smtr_ram_R0C0_DOUTA1 is
         floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smtr_ram_inst/Analog_RTC_smtr_ram_R0C0_DOUTA2 is
         floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smtr_ram_inst/Analog_RTC_smtr_ram_R0C0_DOUTA3 is
         floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smtr_ram_inst/Analog_RTC_smtr_ram_R0C0_DOUTA4 is
         floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smtr_ram_inst/Analog_RTC_smtr_ram_R0C0_DOUTA5 is
         floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smtr_ram_inst/Analog_RTC_smtr_ram_R0C0_DOUTA6 is
         floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smtr_ram_inst/Analog_RTC_smtr_ram_R0C0_DOUTA7 is
         floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smtr_ram_inst/Analog_RTC_smtr_ram_R0C0_DOUTA8 is
         floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smev_ram_inst/EV_RAM_DO_A_net_net_6 is floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smev_ram_inst/EV_RAM_DO_A_net_net_5 is floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smev_ram_inst/EV_RAM_DO_A_net_net_4 is floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smev_ram_inst/EV_RAM_DO_A_net_net_3 is floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smev_ram_inst/EV_RAM_DO_A_net_net_2 is floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smev_ram_inst/EV_RAM_DO_A_net_net_1 is floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smev_ram_inst/Z_EV_RAM_DO_A_net_ is floating
Warning: CMP201: Net: AnalogRTC/Analog_RTC_smev_ram_inst/EV_RAM_DO_A_net[8] is floating

Netlist Optimization Report
===========================

Optimized macros:
  - Dangling net drivers:   0
  - Buffers:                0
  - Inverters:              1
  - Tieoff:                 2
  - Logic combining:        81

    Total macros optimized  84

There were 0 error(s) and 79 warning(s) in this design.
=====================================================================

Reading previous post-compile physical placement constraints.


There were 0 error(s) and 0 warning(s).

=====================================================================

Reading user pdc (Physical Design Constraints) file(s) postcompile


There were 0 error(s) and 0 warning(s).

=====================================================================
Compile report:
===============

    CORE                     Used:   2305  Total:  13824   (16.67%)
    IO (W/ clocks)           Used:     79  Total:    119   (66.39%)
    Differential IO          Used:      0  Total:     58   (0.00%)
    GLOBAL (Chip+Quadrant)   Used:      6  Total:     18   (33.33%)
    PLL                      Used:      1  Total:      2   (50.00%)
    RAM/FIFO                 Used:      3  Total:     24   (12.50%)
    FlashROM                 Used:      0  Total:      1   (0.00%)
    RC oscillator            Used:      1  Total:      1   (100.00%)
    XTL oscillator           Used:      1  Total:      1   (100.00%)
    NVM                      Used:      1  Total:      2   (50.00%)
    AB                       Used:      1  Total:      1   (100.00%)
    AnalogIO                 Used:      0  Total:     46   (0.00%)
    VRPSM                    Used:      1  Total:      1   (100.00%)
    NGMUX                    Used:      0  Total:      2   (0.00%)

Global Information:

    Type            | Used   | Total
    ----------------|--------|-------------
    Chip global     | 6      | 6  (100.00%)
    Quadrant global | 0      | 12 (0.00%)

Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 1813         | 1813
    SEQ     | 492          | 492

I/O Function:

    Type                          | w/o register  | w/ register  | w/ DDR register
    ------------------------------|---------------|--------------|----------------
    Input I/O                     | 4             | 0            | 0
    Output I/O                    | 75            | 0            | 0
    Bidirectional I/O             | 0             | 0            | 0
    Differential Input I/O Pairs  | 0             | 0            | 0
    Differential Output I/O Pairs | 0             | 0            | 0

I/O Technology:

                                    |   Voltages    |             I/Os
    --------------------------------|-------|-------|-------|--------|--------------
    I/O Standard(s)                 | Vcci  | Vref  | Input | Output | Bidirectional
    --------------------------------|-------|-------|-------|--------|--------------
    LVTTL                           | 3.30v | N/A   | 4     | 75     | 0

Net information report:
=======================

The following nets have been assigned to a chip global resource:
    Fanout  Type          Name
    --------------------------
    466     SET/RESET_NET Net   : sys_reset_gl
                          Driver: reset/U_CLKSRC
                          Source: NETLIST
    456     CLK_NET       Net   : ACM_CLK_c
                          Driver: PLL_acm/Core
                          Source: ESSENTIAL
    111     INT_NET       Net   : INIT_DONE_c
                          Driver: I_266/U_CLKSRC
                          Source: NETLIST
    67      INT_NET       Net   :
AnalogRTC.Analog_RTC_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3]
                          Driver: I_267/U_CLKSRC
                          Source: NETLIST
    66      INT_NET       Net   : RTC_cal.RTCcal_present[2]
                          Driver: I_268/U_CLKSRC
                          Source: NETLIST
    16      CLK_NET       Net   : RTCCLK_out_c
                          Driver: XTALRTC/clksrc1
                          Source: ESSENTIAL

High fanout nets in the post compile netlist:
    Fanout  Type          Name
    --------------------------
    16      INT_NET       Net   :
NVManalog/NVM_analog_init_wrapper_inst/U0/u_grwzcnqmqzm/gpbbjwsprsj[1]
                          Driver:
NVManalog/NVM_analog_init_wrapper_inst/U0/u_grwzcnqmqzm/init_fsm/u_stnpfdkggvx/rhjctqnqzsn[1]
    16      INT_NET       Net   :
NVManalog/NVM_analog_init_wrapper_inst/U0/u_grwzcnqmqzm/vvpkfmmpprk[0]
                          Driver:
NVManalog/NVM_analog_init_wrapper_inst/U0/u_grwzcnqmqzm/save_fsm/u_wbsfnwwctpn/bzcdnkppzhj[0]
    16      INT_NET       Net   : RTC_cal/count_ld_2
                          Driver: RTC_cal/count_ld_0_2
    16      INT_NET       Net   : RTC_cal/count_ld_1
                          Driver: RTC_cal/count_ld_0_1
    16      INT_NET       Net   : RTC_cal/count_ld_0
                          Driver: RTC_cal/count_ld_0_0
    16      INT_NET       Net   : RTC_cal/count_ld
                          Driver: RTC_cal/count_ld_0
    16      INT_NET       Net   : RTC_cal/rtccount/Z$1N156_1
                          Driver: RTC_cal/rtccount/$1I153_1
    16      INT_NET       Net   : RTC_cal/rtccount/Z$1N156_0
                          Driver: RTC_cal/rtccount/$1I153_0
    16      INT_NET       Net   :
AnalogRTC/Analog_RTC_assc_wrapper_inst/U0/u_cwgmnvwgkwq/zwnnqcvfccb[3]
                          Driver:
AnalogRTC/Analog_RTC_assc_wrapper_inst/U0/u_cwgmnvwgkwq/zwnnqcvfccb[3]
    16      INT_NET       Net   :
AnalogRTC/Analog_RTC_smev_wrapper_inst/U0/u_nbnjbfrkqwq/rdgwgtpkbgc_0[0]
                          Driver:
AnalogRTC/Analog_RTC_smev_wrapper_inst/U0/u_nbnjbfrkqwq/rdgwgtpkbgc_0[0]

Nets that are candidates for clock assignment and the resulting fanout:
    Fanout  Type          Name
    --------------------------
    38      SET/RESET_NET Net   : SW1_c
                          Driver: SW1_pad
    32      INT_NET       Net   : RTC_cal/rtccount/Z$1N156
                          Driver: RTC_cal/rtccount/$1I153
    28      INT_NET       Net   : SW2_c
                          Driver: SW2_pad
    21      CLK_NET       Net   : LCD_DIS_inst/lcd_en
                          Driver: LCD_DIS_inst/CLK_DIVIDER_intance/GEN_label_13_clk_div/Q_net
    16      INT_NET       Net   :
NVManalog/NVM_analog_init_wrapper_inst/U0/u_grwzcnqmqzm/gpbbjwsprsj[1]
                          Driver:
NVManalog/NVM_analog_init_wrapper_inst/U0/u_grwzcnqmqzm/init_fsm/u_stnpfdkggvx/rhjctqnqzsn[1]
    16      INT_NET       Net   :
NVManalog/NVM_analog_init_wrapper_inst/U0/u_grwzcnqmqzm/vvpkfmmpprk[0]
                          Driver:
NVManalog/NVM_analog_init_wrapper_inst/U0/u_grwzcnqmqzm/save_fsm/u_wbsfnwwctpn/bzcdnkppzhj[0]
    16      INT_NET       Net   : RTC_cal/count_ld_2
                          Driver: RTC_cal/count_ld_0_2
    16      INT_NET       Net   : RTC_cal/count_ld_1
                          Driver: RTC_cal/count_ld_0_1
    16      INT_NET       Net   : RTC_cal/count_ld_0
                          Driver: RTC_cal/count_ld_0_0
    16      INT_NET       Net   : RTC_cal/count_ld
                          Driver: RTC_cal/count_ld_0

The Compile command succeeded ( 00:00:13 )
Pre-assigned technologies detected in (5) out of (5) I/O Bank(s).
All I/O Banks have pre-assigned technologies. Skipping I/O Bank Assigner.

Running the Prelayout checker before global net placement.
Regions Consistency Checker completed.
IO Checker completed.

Running global net placement.


Global net placement completed successfully.

Running the Prelayout checker after global net placement.
Regions Consistency Checker completed.
IO Checker completed.
While analyzing gated clock network, ambiguities have been found on gates
RTC_cal/rtccount/$1I82_ARRAY_26:Y, RTC_cal/rtccount/$1I82_ARRAY_23:Y,
RTC_cal/rtccount/$1I82_ARRAY_20:Y, RTC_cal/rtccount/$1I82_ARRAY_16:Y,
RTC_cal/rtccount/$1I82_ARRAY_5:Y, RTC_cal/rtccount/$1I82_ARRAY_8:Y,
RTC_cal/rtccount/$1I82_ARRAY_9:Y, RTC_cal/rtccount/$1I82_ARRAY_21:Y,
RTC_cal/rtccount/$1I82_ARRAY_13:Y, RTC_cal/rtccount/$1I82_ARRAY_10:Y,
RTC_cal/rtccount/$1I82_ARRAY_2:Y, RTC_cal/rtccount/$1I82_ARRAY_29:Y,
RTC_cal/rtccount/$1I82_ARRAY_22:Y, RTC_cal/rtccount/$1I82_ARRAY_11:Y,
RTC_cal/rtccount/$1I82_ARRAY_1:Y, RTC_cal/rtccount/$1I82_ARRAY_19:Y,
RTC_cal/rtccount/$1I82_ARRAY_12:Y, RTC_cal/rtccount/$1I82_ARRAY_25:Y,
RTC_cal/rtccount/$1I82_ARRAY_28:Y, RTC_cal/rtccount/$1I82_ARRAY_4:Y,
RTC_cal/rtccount/$1I82_ARRAY_15:Y, RTC_cal/rtccount/$1I82_ARRAY_27:Y,
RTC_cal/rtccount/$1I82_ARRAY_18:Y, RTC_cal/rtccount/$1I82_ARRAY_30:Y,
RTC_cal/rtccount/$1I82_ARRAY_24:Y, RTC_cal/rtccount/$1I82_ARRAY_6:Y,
RTC_cal/rtccount/$1I82_ARRAY_31:Y, RTC_cal/rtccount/$1I82_ARRAY_17:Y,
RTC_cal/rtccount/$1I82_ARRAY_7:Y, RTC_cal/rtccount/$1I82_ARRAY_3:Y,
RTC_cal/rtccount/$1I82_ARRAY_14:Y.
The timing models of these gates have been simplified for Static Timing Analysis.

desqdplacer V6_2_0.0 - 5/16/05
Design: D:\RTC_Demo\designer\impl1\RTC_demoStarted: Thu Jun 22 15:30:20 2006

Initial IO placement.
Initial RAM placement.
IO & RAM improvement.
Core placement.
Core improvement.

Runtimes: IO Placement         = 0 seconds
          RAM Placement        = 0 seconds
          IO & RAM Improvement = 2 seconds
          Core Placement       = 9 seconds
          Core Improvement     = 52 seconds


desqdplacer completed successfully.

Design: D:\RTC_Demo\designer\impl1\RTC_demo
Finished: Thu Jun 22 15:31:23 2006
Total CPU Time:     00:01:02            Total Elapsed Time: 00:01:03
                        o - o - o - o - o - o



gfblrouter V5_0_7.0 - 07/17/03 

Design: RTC_demo                        Started: Thu Jun 22 15:31:31 2006



 Initial routing.

Initial routing...

        Pass 0: Shorts = 0. Open nets = 2387.

        Pass 0: Shorts = 0. Open nets = 812.

        Pass 0: Shorts = 0. Open nets = 802.

        Pass 0: Shorts = 0. Open nets = 786.

        Pass 0: Shorts = 0. Open nets = 774.

        Pass 0: Shorts = 0. Open nets = 768.

        Pass 0: Shorts = 0. Open nets = 759.

        Pass 0: Shorts = 0. Open nets = 738.

        Pass 0: Shorts = 0. Open nets = 711.

        Pass 0: Shorts = 0. Open nets = 683.

        Pass 0: Shorts = 0. Open nets = 663.

        Pass 0: Shorts = 0. Open nets = 643.

        Pass 0: Shorts = 0. Open nets = 611.

        Pass 0: Shorts = 0. Open nets = 595.

        Pass 0: Shorts = 0. Open nets = 572.

        Pass 0: Shorts = 0. Open nets = 560.

        Pass 0: Shorts = 0. Open nets = 541.

        Pass 0: Shorts = 0. Open nets = 520.

        Pass 0: Shorts = 0. Open nets = 497.

        Pass 0: Shorts = 0. Open nets = 477.

        Pass 0: Shorts = 0. Open nets = 461.

        Pass 0: Shorts = 0. Open nets = 442.

        Pass 0: Shorts = 0. Open nets = 411.

        Pass 0: Shorts = 0. Open nets = 387.

        Pass 0: Shorts = 0. Open nets = 351.

        Pass 0: Shorts = 0. Open nets = 327.

        Pass 0: Shorts = 0. Open nets = 291.

        Pass 0: Shorts = 0. Open nets = 265.

        Pass 0: Shorts = 0. Open nets = 246.

        Pass 0: Shorts = 0. Open nets = 225.

        Pass 0: Shorts = 0. Open nets = 200.

        Pass 0: Shorts = 0. Open nets = 182.

        Pass 0: Shorts = 0. Open nets = 167.

        Pass 0: Shorts = 0. Open nets = 141.

        Pass 0: Shorts = 0. Open nets = 89.

        Pass 0: Shorts = 0. Open nets = 37.

        Pass 0: Shorts = 0. Open nets = 5.

        Pass 0: Shorts = 0. Open nets = 0.

After pass 0: Shorts = 0. Open nets = 0.



 Iterative improvement.

        Pass 1: Shorts = 0. Open nets = 0.

Balancing the clock successfully done.



gfblrouter completed successfully.



Design: RTC_demo                        

Finished: Thu Jun 22 15:32:03 2006

Total CPU Time:     00:00:31            Total Elapsed Time: 00:00:32

                        o - o - o - o - o - o



Loading the Timing data for the design.
While analyzing gated clock network, ambiguities have been found on gates
RTC_cal/rtccount/$1I82_ARRAY_26:Y, RTC_cal/rtccount/$1I82_ARRAY_23:Y,
RTC_cal/rtccount/$1I82_ARRAY_20:Y, RTC_cal/rtccount/$1I82_ARRAY_16:Y,
RTC_cal/rtccount/$1I82_ARRAY_5:Y, RTC_cal/rtccount/$1I82_ARRAY_8:Y,
RTC_cal/rtccount/$1I82_ARRAY_9:Y, RTC_cal/rtccount/$1I82_ARRAY_21:Y,
RTC_cal/rtccount/$1I82_ARRAY_13:Y, RTC_cal/rtccount/$1I82_ARRAY_10:Y,
RTC_cal/rtccount/$1I82_ARRAY_2:Y, RTC_cal/rtccount/$1I82_ARRAY_29:Y,
RTC_cal/rtccount/$1I82_ARRAY_22:Y, RTC_cal/rtccount/$1I82_ARRAY_11:Y,
RTC_cal/rtccount/$1I82_ARRAY_1:Y, RTC_cal/rtccount/$1I82_ARRAY_19:Y,
RTC_cal/rtccount/$1I82_ARRAY_12:Y, RTC_cal/rtccount/$1I82_ARRAY_25:Y,
RTC_cal/rtccount/$1I82_ARRAY_28:Y, RTC_cal/rtccount/$1I82_ARRAY_4:Y,
RTC_cal/rtccount/$1I82_ARRAY_15:Y, RTC_cal/rtccount/$1I82_ARRAY_27:Y,
RTC_cal/rtccount/$1I82_ARRAY_18:Y, RTC_cal/rtccount/$1I82_ARRAY_30:Y,
RTC_cal/rtccount/$1I82_ARRAY_24:Y, RTC_cal/rtccount/$1I82_ARRAY_6:Y,
RTC_cal/rtccount/$1I82_ARRAY_31:Y, RTC_cal/rtccount/$1I82_ARRAY_17:Y,
RTC_cal/rtccount/$1I82_ARRAY_7:Y, RTC_cal/rtccount/$1I82_ARRAY_3:Y,
RTC_cal/rtccount/$1I82_ARRAY_14:Y.
The timing models of these gates have been simplified for Static Timing Analysis.
Finished loading the Timing data.
TIMER: Timing constraints requirements have been met.

The Layout command succeeded ( 00:02:12 )
Warning: File D:\RTC_Demo\designer\impl1\RTC_demo.stp already exists
         Do you want to replace it? [YES]

The Export-map command succeeded ( 00:00:35 )
Warning: Overwriting the existing file: ./RTC_demo.stp.
Wrote to the file: .\RTC_demo.stp

The Generate programming file command succeeded ( 00:00:40 )
Design saved to file D:\RTC_Demo\designer\impl1\RTC_demo.adb.
Design saved to file D:\RTC_Demo\designer\impl1\RTC_demo.adb.
Design closed.

