Version:7.0.0.13
ACTGENU_CALL:1
BATCH:T
FAM:Fusion
OUTFORMAT:VHDL
LPMTYPE:LPM_DFF
LPM_HINT:SISO
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:F
"DESDIR:D:/data/datasheets/Fusion/Demo Design/RTC_demo/smartgen\Shift8_reg"
GEN_BEHV_MODULE:T
SMARTGEN_DIE:IR6X6M2
SMARTGEN_PACKAGE:fg256
 CLR_POLARITY:0
 CLR_FANIN:AUTO
 CLR_VAL:8
 EN_POLARITY:2
 EN_FANIN:AUTO
 EN_VAL:6
 SHEN_POLARITY:1
 SHEN_FANIN:AUTO
 SHEN_VAL:6
 CLK_EDGE:RISE
 CLK_FANIN:MANUAL
 CLK_VAL:1
 WIDTH:8
 FF_TYPE:REGULAR
