`timescale 1 ns/100 ps
// Version: 7.1 7.1.0.14


module ANALOG_RTC_smev_ram(DATAA,QA,DATAB,QB,ADDRESSA,ADDRESSB,
        RWA,RWB,BLKA,BLKB,CLOCK,RESET);
input [8:0] DATAA;
output [8:0] QA;
input [8:0] DATAB;
output [8:0] QB;
input [8:0] ADDRESSA, ADDRESSB;
input RWA, RWB, BLKA, BLKB, CLOCK, RESET;

    wire VCC, GND;
    
    VCC VCC_1_net(.Y(VCC));
    GND GND_1_net(.Y(GND));
    RAM4K9 ANALOG_RTC_smev_ram_R0C0(.ADDRA11(GND), .ADDRA10(GND), 
        .ADDRA9(GND), .ADDRA8(ADDRESSA[8]), .ADDRA7(ADDRESSA[7]), 
        .ADDRA6(ADDRESSA[6]), .ADDRA5(ADDRESSA[5]), .ADDRA4(
        ADDRESSA[4]), .ADDRA3(ADDRESSA[3]), .ADDRA2(ADDRESSA[2]), 
        .ADDRA1(ADDRESSA[1]), .ADDRA0(ADDRESSA[0]), .ADDRB11(GND), 
        .ADDRB10(GND), .ADDRB9(GND), .ADDRB8(ADDRESSB[8]), 
        .ADDRB7(ADDRESSB[7]), .ADDRB6(ADDRESSB[6]), .ADDRB5(
        ADDRESSB[5]), .ADDRB4(ADDRESSB[4]), .ADDRB3(ADDRESSB[3]), 
        .ADDRB2(ADDRESSB[2]), .ADDRB1(ADDRESSB[1]), .ADDRB0(
        ADDRESSB[0]), .DINA8(DATAA[8]), .DINA7(DATAA[7]), .DINA6(
        DATAA[6]), .DINA5(DATAA[5]), .DINA4(DATAA[4]), .DINA3(
        DATAA[3]), .DINA2(DATAA[2]), .DINA1(DATAA[1]), .DINA0(
        DATAA[0]), .DINB8(DATAB[8]), .DINB7(DATAB[7]), .DINB6(
        DATAB[6]), .DINB5(DATAB[5]), .DINB4(DATAB[4]), .DINB3(
        DATAB[3]), .DINB2(DATAB[2]), .DINB1(DATAB[1]), .DINB0(
        DATAB[0]), .WIDTHA0(VCC), .WIDTHA1(VCC), .WIDTHB0(VCC), 
        .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(GND), .WMODEA(VCC), 
        .WMODEB(VCC), .BLKA(BLKA), .BLKB(BLKB), .WENA(RWA), .WENB(
        RWB), .CLKA(CLOCK), .CLKB(CLOCK), .RESET(RESET), .DOUTA8(
        QA[8]), .DOUTA7(QA[7]), .DOUTA6(QA[6]), .DOUTA5(QA[5]), 
        .DOUTA4(QA[4]), .DOUTA3(QA[3]), .DOUTA2(QA[2]), .DOUTA1(
        QA[1]), .DOUTA0(QA[0]), .DOUTB8(QB[8]), .DOUTB7(QB[7]), 
        .DOUTB6(QB[6]), .DOUTB5(QB[5]), .DOUTB4(QB[4]), .DOUTB3(
        QB[3]), .DOUTB2(QB[2]), .DOUTB1(QB[1]), .DOUTB0(QB[0]));
    
endmodule
