/*******************************************************************************
* Actel Corportation
* Fusion's Context Saving and Reload Application Note's Design Example
*
* Target Device:    AFS600 256 FBGA
* File Name:    PM_CONTEXT_SAVING_TOP.v
* Date:         June 2006
* Language:     Verilog
*
* Description:  PM_CONTEXT_SAVING_TOP is the design's top module for 
* the context saving and reload application in a power management
* system. All macros generated from SmartGen are instantiated and 
* connected to the CONTEXT_CNTRL module.
*
* SmartGen Macros:
* RC_OSC - RC Oscillator
* PLL_CLK100_10 - Statis PLL
* NGMUX_CLK - No-glitch Mux
* XTAL - Crystal Oscillator
* PMVREG - Voltage Regulator Power Supply Monitor
* ANALOG_RTC - Analog System with RTC circuit
* SRAM - Sram with Initialization 
* FLASH - Flash for Sram and Analog System initialization
********************************************************************************
* IMPORTANT-READ THESE TERMS CAREFULLY BEFORE UTILIZING THE INFORMATION
* CONTAINED IN THIS APPLICATION NOTE. 
*
* NO SUPPORT/NO WARRANTY. THE DESIGN FILES AND DOCUMENTATION ARE PROVIDED
* WITHOUT SUPPORT OR WARRANTY OF ANY KIND. ACTEL IS NOT OBLIGATED TO 
* PROVIDE UPDATES, BUG FIXES, OR TECHNICAL SUPPORT AND DISCLAIMS ALL 
* WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, AND WARRANTIES OF NON-INFRINGEMENT OF THE
* RIGHTS OF THIRD PARTIES (INCLUDING, WITHOUT LIMITATION, RIGHTS UNDER PATENT,
* COPYRIGHT, TRADE SECRET, OR OTHER INTELLECTUAL PROPERTY RIGHTS).  RECIPIENT
* ACCEPTS THE APPLICATION NOTE DESIGN FILES AND DOCUMENTATION IN "AS-IS"
* CONDITION.
*******************************************************************************/


`timescale 1 ns/100 ps


module PM_CONTEXT_SAVING_TOP ( SYS_RESETn
    , SYS_CLOCK
    , XTL
    , PUB
    , VRPU_IN
    , VAREF
    , SAVE_SRAM_TO_FLASH
    , UPDATE_SRAM_FROM_FLASH
    , VRPU_AUTO_SHDN_EN
    , WENn
    , RENn
    , WADDR
    , RADDR
    , WD
    , RD
    , CONTEXT_DONE
    , FPGAGOOD
);


/* PM_CONTEXT_SAVING_TOP Port Declarations */
input	SYS_RESETn;             // External active-low reset input
output  SYS_CLOCK;              // NGMUX clock output
input   XTL;                    // External crystal input frequency
input	PUB;                    // External active-low voltage regulator power-up input
input   VRPU_IN;                // Voltage regulator power-down input
input   VAREF;                  // External analog voltage reference input
input   SAVE_SRAM_TO_FLASH;     // Sram to Flash save command input
input   UPDATE_SRAM_FROM_FLASH; // Update Sram from Flash command input
input	VRPU_AUTO_SHDN_EN;      // Auto-shutdown after a save command enable

input   WENn;                   // Active-low Sram write enable input
input   RENn;                   // Active-low Sram read enable input
input   [5:0]    WADDR;         // Sram write address bus input
input   [5:0]    RADDR;         // Sram read address bus input
input   [15:0]   WD;            // Sram write data bus input
output  [15:0]   RD;            // Sram read data bus input

output	CONTEXT_DONE;           // Context initialization interface done output
output	FPGAGOOD;               // Ouput from voltage regulator indicating FPGA power is good


/* PM_CONTEXT_SAVING_TOP Interconnects */

// Clock Network System Interconnects
wire    RCOSC_CLOCK;
wire    CLOCK_100;
wire    CLOCK_DIV10;
wire    RTC_CLOCK;
wire    PLL_LOCK;
wire	NGMUX_SEL;

// Power Management System Interconnects
wire	VRPU;
wire    VRPU_AUTO_SHDN;
wire	PUCORE;

wire    RTCXTLSEL;
wire    [1:0]   RTCXTLMODE_I;
wire    RTCMATCH;
wire    RTCPSMMATCH;

// Embedded Memory System Interconnects
wire    [8:0]	INITADDR;
wire    [8:0]	INITDATA;
wire    [8:0]	INITDOUT0;
wire    SRAM_block_0_DAT_VAL;

wire    CLIENT_UPDATE;
wire    SAVE_COMPLETE;
wire    INIT_POWER_UP;
wire    FLASH_RESETn;

wire	INIT_WEN_MASK;
wire    INIT_ACM_WEN;
wire    INIT_ACM_RTC_WEN;
wire    INIT_ASSC_WEN;
wire    INIT_EV_WEN;
wire    INIT_TR_WEN;
wire	MASK_INIT_ACM_RTC_WEN;
wire    MASK_INIT_ACM_WEN;
wire    MASK_INIT_ASSC_WEN;
wire    MASK_INIT_EV_WEN;
wire    MASK_INIT_TR_WEN;


/* Macro and Madule Instances */

// Clock Network System: RC Oscillator instance
RC_OSC U_RCOSC (.CLKOUT(RCOSC_CLOCK));

// Clock Network System: Static PLL instance
// YB port was required to be enabled in order to use the
// GLC output port.
PLL_CLK100_10 U_PLL
( .POWERDOWN(SYS_RESETn)
    , .CLKA(RCOSC_CLOCK)
    , .LOCK(PLL_LOCK)
    , .GLA(CLOCK_100)
    , .YB()
    , .GLC(CLOCK_DIV10)
    , .OADIVRST(SYS_RESETn)
);

// Clock Network System: No-glitch Mux instance
// CLK0 and CLK1 inputs must be driven by GLA and GLC 
// PLL output ports. Both inputs each must have a fanout of 1.
NGMUX_CLK U_NGMUX( .CLK0(CLOCK_100)
    , .CLK1(CLOCK_DIV10)
    , .S(NGMUX_SEL)
    , .GL(SYS_CLOCK)
);

// Clock Network System: Crystal Oscillator instance
XTAL U_XTAL ( .XTL(XTL)
    , .CLKOUT(RTC_CLOCK)
    , .SELMODE(RTCXTLSEL)
    , .RTC_MODE0(RTCXTLMODE_I[0])
    , .RTC_MODE1(RTCXTLMODE_I[1])
);

// 2-input mux used to select between a controlled shutdown of the 
// voltage regulator through VRPU_IN inputs or an auto-shutdown
// through the VRPU_AUTO_SHDN CONTEXT_CNTRL output. The VRPU_AUTO_SHDN_EN
// input is the select to this mux and the output is connected directly
// to the VRPU input of the PWVREG macro.
assign VRPU = VRPU_AUTO_SHDN_EN ? VRPU_AUTO_SHDN : VRPU_IN;

// Power management System: Voltage Regulator Power Supply instance
PMVREG U_PMVREG ( .PUB(PUB)
    ,.VRPU(VRPU)
    ,.FPGAGOOD(FPGAGOOD)
    ,.PUCORE(PUCORE)
    ,.RTCPSMMATCH(RTCPSMMATCH)
);

// The INIT_*_WEN signals are masked using the INIT_WEN_MASK CONTEXT_CNTRL
// output. These signals are masked to prevent updates of the RTC
// configuration registers when an UPDATE_SRAM_FROM_FLASH command has been issued.
assign MASK_INIT_ACM_RTC_WEN = INIT_ACM_RTC_WEN & INIT_WEN_MASK;
assign MASK_INIT_ACM_WEN = INIT_ACM_WEN & INIT_WEN_MASK;
assign MASK_INIT_ASSC_WEN = INIT_ASSC_WEN & INIT_WEN_MASK;
assign MASK_INIT_EV_WEN = INIT_EV_WEN & INIT_WEN_MASK;
assign MASK_INIT_TR_WEN = INIT_TR_WEN & INIT_WEN_MASK;

// Power management System: Analog System with RTC instance
ANALOG_RTC U_ANALOG_RTC ( .SYS_CLK(SYS_CLOCK)
    , .SYS_RESET(SYS_RESETn)
    , .VAREF(VAREF)
    , .DATAVALID()
    , .ASSC_DONE()
    , .ASSC_WAIT()
    , .ASSC_CHSAT()
    , .ASSC_CHLATD()
    , .INIT_ADDR(INITADDR)
    , .INIT_DATA(INITDATA)
    , .INIT_ACM_WEN(MASK_INIT_ACM_WEN)
    , .INIT_ACM_RTC_WEN(MASK_INIT_ACM_RTC_WEN)
    , .INIT_ASSC_WEN(MASK_INIT_ASSC_WEN)
    , .INIT_EV_WEN(MASK_INIT_EV_WEN)
    , .INIT_TR_WEN(MASK_INIT_TR_WEN)
    , .INIT_DONE(INIT_DONE)
    , .RTCCLK(RTC_CLOCK)
    , .RTCXTLSEL(RTCXTLSEL)
    , .RTCXTLMODE_I(RTCXTLMODE_I)
    , .RTCMATCH(RTCMATCH)
    , .RTCPSMMATCH(RTCPSMMATCH)
);

// Context Control Module Instance
CONTEXT_CNTRL U_CCNTRL( .SYS_RESETn(SYS_RESETn)
    , .PLL_LOCK(PLL_LOCK)
    , .NGMUX_SEL(NGMUX_SEL)
    , .CONTEXT_CLK(SYS_CLOCK)
    , .SAVE_SRAM_TO_FLASH(SAVE_SRAM_TO_FLASH)
    , .UPDATE_SRAM_FROM_FLASH(UPDATE_SRAM_FROM_FLASH)
    , .CONTEXT_DONE(CONTEXT_DONE)
    , .FLASH_RESETn(FLASH_RESETn)
    , .INIT_POWER_UP(INIT_POWER_UP)
    , .CLIENT_UPDATE(CLIENT_UPDATE)
    , .INIT_WEN_MASK(INIT_WEN_MASK)
    , .INIT_DONE(INIT_DONE)
    , .SAVE_COMPLETE(SAVE_COMPLETE)
    , .VRPU_AUTO_SHDN(VRPU_AUTO_SHDN)
);

// Embedded Memory System: Sram with initialization instance
SRAM U_SRAM( .WD(WD)                        // PM_CONTEXT_SAVING_TOP input
    , .RD(RD)                               // PM_CONTEXT_SAVING_TOP output
    , .WEN(WENn)                            // PM_CONTEXT_SAVING_TOP input
    , .REN(RENn)                            // PM_CONTEXT_SAVING_TOP input
    , .WADDR(WADDR)                         // PM_CONTEXT_SAVING_TOP input
    , .RADDR(RADDR)                         // PM_CONTEXT_SAVING_TOP input
    , .RWCLK(SYS_CLOCK)                     // from NGMUX_CLK
    , .RESET(SYS_RESETn)                    // PM_CONTEXT_SAVING_TOP input
    , .INITADDR(INITADDR)                   // from FLASH
    , .INITACTIVE(INIT_POWER_UP)            // from CONTEXT_CNTRL
    , .INITDATA(INITDATA)                   // from FLASH
    , .INIT_CLIENT_0(SRAM_block_0_DAT_VAL)  // from FLASH
    , .SAVEACTIVE(CLIENT_UPDATE)            // from CONTEXT_CNTRL
    , .INITDOUT0(INITDOUT0)                 // to FLASH
);

// Embedded Memory System: Flash with Sram and RTC initialization instance
FLASH U_FLASH( .INIT_CLK(SYS_CLOCK)         // from NGMUX_CLK
    , .SYS_RESET(FLASH_RESETn)              // from CONTEXT_CNTRL
    , .INIT_POWER_UP(INIT_POWER_UP)         // from CONTEXT_CNTRL
    , .INIT_DONE(INIT_DONE)                 // to CONTEXT_CNTRL
    , .INIT_DATA(INITDATA)                  // to SRAM
    , .INIT_ADDR(INITADDR)                  // to SRAM
    , .INIT_ACM_RTC_WEN(INIT_ACM_RTC_WEN)   // to ANALOG_RTC
    , .INIT_ACM_WEN(INIT_ACM_WEN)           // to ANALOG_RTC
    , .INIT_ASSC_WEN(INIT_ASSC_WEN)         // to ANALOG_RTC
    , .INIT_EV_WEN(INIT_EV_WEN)             // to ANALOG_RTC
    , .INIT_TR_WEN(INIT_TR_WEN)             // to ANALOG_RTC
    , .SRAM_block_0_DAT_VAL(SRAM_block_0_DAT_VAL)   // to SRAM
    , .SRAM_block_0_AVAIL(CLIENT_UPDATE)    // from CONTEXT_CNTRL
    , .SRAM_block_0_DIN(INITDOUT0)          // from SRAM
    , .SAVE_COMPLETE(SAVE_COMPLETE)         // to CONTEXT_CNTRL
    , .CLIENT_UPDATE(CLIENT_UPDATE)         // from CONTEXT_CNTRL
);

endmodule