`timescale 1 ns/100 ps
// Version: 7.1 7.1.0.14


module PMVREG(PUB,VRPU,FPGAGOOD,PUCORE,RTCPSMMATCH);
input PUB, VRPU;
output  FPGAGOOD, PUCORE;
input  RTCPSMMATCH;

    wire VCC, SOC_GND_NET;
    wire SOC_VCC_NET_IOCNTL = VCC;
    wire SOC_GND_NET_VRFPD = SOC_GND_NET;
    
    VCC VCC_1_net(.Y(VCC));
    GND GND_1_net(.Y(SOC_GND_NET));
    VRPSM VRPSM1(.PUB(PUB), .VRPU(VRPU), .VRINITSTATE(VCC), 
        .RTCPSMMATCH(RTCPSMMATCH), .FPGAGOOD(FPGAGOOD), .PUCORE(
        PUCORE));
    
endmodule
