module ANALOG_RTC_smtr_wrapper ( CLK,
               NRESET,
               EV_CHHOLD,
               EV_DONE,
               EV_RAM_WR_BUSY_B,
               GPI,
               GPO,
               INIT_ADDR,
               INIT_TR_WR,
               INIT_DI,
               INIT_DONE,
               USER_TR_ADDR,
               USER_TR_RD,
               USER_TR_RAM_BUSY,
               TR_EV_ADDR,
               TR_EV_RD,
               TR_TRFLAG,
               TR_DONE,
               EV_RAM_DO_A,
               TR_RAM_ADDR_A,
               TR_RAM_RW_A,
               TR_RAM_CSN_A,
               TR_RAM_DI_A,
               TR_RAM_ADDR_B,
               TR_RAM_RW_B,
               TR_RAM_CSN_B,
               TR_RAM_DI_B,
               TR_RAM_DO_B,
               TR_RAM_WR_BUSY_B );

    input CLK;
    input NRESET;
    input[4 : 0] EV_CHHOLD;
    input EV_DONE;
    input EV_RAM_WR_BUSY_B;
    input[(((2**0)*32)-1) : 0] GPI;
    output[(((2**0)*32)-1) : 0] GPO;
    input[9-1 : 0] INIT_ADDR;
    input INIT_TR_WR;
    input[8 : 0] INIT_DI;
    input INIT_DONE;
    input[9-1 : 0] USER_TR_ADDR;
    input USER_TR_RD;
    output USER_TR_RAM_BUSY;
    output[9-1 : 0] TR_EV_ADDR;
    output TR_EV_RD;
    output TR_TRFLAG;
    output TR_DONE;
    input[8 : 0] EV_RAM_DO_A;
    output[9-1 : 0] TR_RAM_ADDR_A;
    output TR_RAM_RW_A;
    output TR_RAM_CSN_A;
    output[8 : 0] TR_RAM_DI_A;
    output[9-1 : 0] TR_RAM_ADDR_B;
    output TR_RAM_RW_B;
    output TR_RAM_CSN_B;
    output[8 : 0] TR_RAM_DI_B;
    input[8 : 0] TR_RAM_DO_B;
    output TR_RAM_WR_BUSY_B;

    wire CLK;
    wire NRESET;
    wire [4 : 0]EV_CHHOLD;
    wire EV_DONE;
    wire EV_RAM_WR_BUSY_B;
    wire [(((2**0)*32)-1) : 0]GPI;
    wire [(((2**0)*32)-1) : 0]GPO;
    wire [9-1 : 0]INIT_ADDR;
    wire INIT_TR_WR;
    wire [8 : 0]INIT_DI;
    wire INIT_DONE;
    wire [9-1 : 0]USER_TR_ADDR;
    wire USER_TR_RD;
    wire USER_TR_RAM_BUSY;
    wire [9-1 : 0]TR_EV_ADDR;
    wire TR_EV_RD;
    wire TR_TRFLAG;
    wire TR_DONE;
    wire [8 : 0]EV_RAM_DO_A;
    wire [9-1 : 0]TR_RAM_ADDR_A;
    wire TR_RAM_RW_A;
    wire TR_RAM_CSN_A;
    wire [8 : 0]TR_RAM_DI_A;
    wire [9-1 : 0]TR_RAM_ADDR_B;
    wire TR_RAM_RW_B;
    wire TR_RAM_CSN_B;
    wire [8 : 0]TR_RAM_DI_B;
    wire [8 : 0]TR_RAM_DO_B;
    wire TR_RAM_WR_BUSY_B;

    defparam user_ANALOG_RTC_smtr_wrapper.GPI_BITS = 0;
    defparam user_ANALOG_RTC_smtr_wrapper.GPO_BITS = 0;
    defparam user_ANALOG_RTC_smtr_wrapper.ALLOW_USER_TR = 0;
    defparam user_ANALOG_RTC_smtr_wrapper.EV_ASIZE = 9;
    defparam user_ANALOG_RTC_smtr_wrapper.TR_ASIZE = 9;

    SMTR user_ANALOG_RTC_smtr_wrapper ( 
	.CLK (CLK),
	.NRESET (NRESET),
	.EV_CHHOLD (EV_CHHOLD),
	.EV_DONE (EV_DONE),
	.EV_RAM_WR_BUSY_B (EV_RAM_WR_BUSY_B),
	.GPI (GPI),
	.GPO (GPO),
	.INIT_ADDR (INIT_ADDR),
	.INIT_TR_WR (INIT_TR_WR),
	.INIT_DI (INIT_DI),
	.INIT_DONE (INIT_DONE),
	.USER_TR_ADDR (USER_TR_ADDR),
	.USER_TR_RD (USER_TR_RD),
	.USER_TR_RAM_BUSY (USER_TR_RAM_BUSY),
	.TR_EV_ADDR (TR_EV_ADDR),
	.TR_EV_RD (TR_EV_RD),
	.TR_TRFLAG (TR_TRFLAG),
	.TR_DONE (TR_DONE),
	.EV_RAM_DO_A (EV_RAM_DO_A),
	.TR_RAM_ADDR_A (TR_RAM_ADDR_A),
	.TR_RAM_RW_A (TR_RAM_RW_A),
	.TR_RAM_CSN_A (TR_RAM_CSN_A),
	.TR_RAM_DI_A (TR_RAM_DI_A),
	.TR_RAM_ADDR_B (TR_RAM_ADDR_B),
	.TR_RAM_RW_B (TR_RAM_RW_B),
	.TR_RAM_CSN_B (TR_RAM_CSN_B),
	.TR_RAM_DI_B (TR_RAM_DI_B),
	.TR_RAM_DO_B (TR_RAM_DO_B),
	.TR_RAM_WR_BUSY_B (TR_RAM_WR_BUSY_B) );

endmodule