# Created by Libero IDE 7.1.0.14
# Thu Jun 01 12:32:32 2006

# (NEW DESIGN)

# create a new design
new_design -name "OSC" -family "Fusion"

# set default back-annotation base-name
set_defvar "BA_NAME" "OSC_ba"

# set working directory
set_defvar "DESDIR" "D:/Actelprj/PowerManagement_ContextSaving/designer/impl1"

# set back-annotation output directory
set_defvar "BA_DIR" "D:/Actelprj/PowerManagement_ContextSaving/designer/impl1"

# enable the export back-annotation netlist
set_defvar "BA_NETLIST_ALSO" "1"

# set EDIF options
set_defvar "EDNINFLAVOR" "GENERIC"

# set HDL options
set_defvar "NETLIST_NAMING_STYLE" "VERILOG"

# setup status report options
set_defvar "EXPORT_STATUS_REPORT" "1"
set_defvar "EXPORT_STATUS_REPORT_FILENAME" "OSC.rpt"

# legacy audit-mode flags (left here for historical reasons)
set_defvar "AUDIT_NETLIST_FILE" "1"
set_defvar "AUDIT_DCF_FILE" "1"
set_defvar "AUDIT_PIN_FILE" "1"
set_defvar "AUDIT_ADL_FILE" "1"

# import of input files
import_source  \
-format "edif" -edif_flavor "GENERIC" -netlist_naming "VERILOG" {../../synthesis/OSC.edn}

# export translation of original netlist
export -format "verilog" {../../synthesis/OSC.v}

set_device -die "AFS600" -package "484 FBGA"
import_source  \
-format "edif" -edif_flavor "GENERIC" -netlist_naming "VERILOG" {../../synthesis/OSC.edn}
set_defvar "BLOCK" "T"
set_defvar "ENABLE_BLOCK_MODE" "1"

puts "IDE_BEGINNING_OF_COMPILE"

compile
export -format "log" {..\..\synthesis\OSC_drc_temp.rpt}
