`timescale 1 ns/100 ps
// Version: 7.1 7.1.0.14


module SRAM(WD,RD,WEN,REN,WADDR,RADDR,RWCLK,RESET,INITADDR,
        INITACTIVE,INITDATA,INIT_CLIENT_0,SAVEACTIVE,INITDOUT0);
input [15:0] WD;
output [15:0] RD;
input  WEN, REN;
input [5:0] WADDR, RADDR;
input RWCLK, RESET;
input [8:0] INITADDR;
input INITACTIVE;
input [8:0] INITDATA;
input INIT_CLIENT_0, SAVEACTIVE;
output [8:0] INITDOUT0;

    wire INITDOUT0_0_net, INITDOUT0_1_net, INITDOUT0_2_net, 
        INITDOUT0_3_net, INITDOUT0_4_net, INITDOUT0_5_net, 
        INITDOUT0_6_net, INITDOUT0_7_net, INITDOUT0_8_net, 
        INITDATA_EXT_9_net, DINARESULT_C0_0_net, 
        DINARESULT_C0_1_net, DINARESULT_C0_2_net, 
        DINARESULT_C0_3_net, DINARESULT_C0_4_net, 
        DINARESULT_C0_5_net, DINARESULT_C0_6_net, 
        DINARESULT_C0_7_net, DINARESULT_C0_8_net, 
        DINARESULT_C0_9_net, DINARESULT_C0_10_net, 
        DINARESULT_C0_11_net, DINARESULT_C0_12_net, 
        DINARESULT_C0_13_net, DINARESULT_C0_14_net, 
        DINARESULT_C0_15_net, DINARESULT_C0_16_net, 
        DINARESULT_C0_17_net, ADDRA_INT_0_net, ADDRA_INT_1_net, 
        ADDRA_INT_2_net, ADDRA_INT_3_net, ADDRA_INT_4_net, 
        ADDRA_INT_5_net, ADDRA_INT_6_net, ADDRA_INT_7_net, 
        ADDRA_INT_8_net, ADDRB_INT_0_net, ADDRB_INT_1_net, 
        ADDRB_INT_2_net, ADDRB_INT_3_net, ADDRB_INT_4_net, 
        ADDRB_INT_5_net, ADDRB_INT_6_net, ADDRB_INT_7_net, 
        ADDRB_INT_8_net, WIDTHA0X, WIDTHA1X, WIDTHB0X, WIDTHB1X, 
        ENABLEA_00, RWAXINT, ENABLEB_00, RWBXINT, BUFF_1_Y, 
        BUFF_0_Y;
    wire ADDRA_GEN_NORMADDR_EXT_0_net = INITDATA_EXT_9_net;
    wire ADDRB_GEN_NORMADDR_EXT_0_net = INITDATA_EXT_9_net;
    wire VCC;
    wire GND = INITDATA_EXT_9_net;
    assign RD[0] = INITDOUT0_0_net;
    assign RD[1] = INITDOUT0_1_net;
    assign RD[2] = INITDOUT0_2_net;
    assign RD[3] = INITDOUT0_3_net;
    assign RD[4] = INITDOUT0_4_net;
    assign RD[5] = INITDOUT0_5_net;
    assign RD[6] = INITDOUT0_6_net;
    assign RD[7] = INITDOUT0_7_net;
    assign RD[8] = INITDOUT0_8_net;
    assign INITDOUT0[0] = INITDOUT0_0_net;
    assign INITDOUT0[1] = INITDOUT0_1_net;
    assign INITDOUT0[2] = INITDOUT0_2_net;
    assign INITDOUT0[3] = INITDOUT0_3_net;
    assign INITDOUT0[4] = INITDOUT0_4_net;
    assign INITDOUT0[5] = INITDOUT0_5_net;
    assign INITDOUT0[6] = INITDOUT0_6_net;
    assign INITDOUT0[7] = INITDOUT0_7_net;
    assign INITDOUT0[8] = INITDOUT0_8_net;
    
    VCC VCC_1_net(.Y(VCC));
    GND GND_1_net(.Y(INITDATA_EXT_9_net));
    MX2 MX2_ADDRA_INT_8_inst(.A(ADDRA_GEN_NORMADDR_EXT_0_net), .B(
        INITADDR[8]), .S(INITACTIVE), .Y(ADDRA_INT_8_net));
    MX2 MX2_ADDRA_INT_3_inst(.A(WADDR[2]), .B(INITADDR[3]), .S(
        INITACTIVE), .Y(ADDRA_INT_3_net));
    MX2 MX2_ADDRA_INT_7_inst(.A(ADDRA_GEN_NORMADDR_EXT_0_net), .B(
        INITADDR[7]), .S(INITACTIVE), .Y(ADDRA_INT_7_net));
    MX2 MX2_ADDRB_INT_7_inst(.A(ADDRB_GEN_NORMADDR_EXT_0_net), .B(
        INITADDR[7]), .S(SAVEACTIVE), .Y(ADDRB_INT_7_net));
    MX2 MX2_DINARESULT_C0_1_inst(.A(WD[1]), .B(INITDATA[1]), .S(
        BUFF_1_Y), .Y(DINARESULT_C0_1_net));
    MX2 MX2_WIDTHB0X(.A(GND), .B(VCC), .S(SAVEACTIVE), .Y(
        WIDTHB0X));
    BUFF BUFF_1(.A(INITACTIVE), .Y(BUFF_1_Y));
    MX2 MX2_DINARESULT_C0_10_inst(.A(WD[10]), .B(
        INITDATA_EXT_9_net), .S(BUFF_0_Y), .Y(
        DINARESULT_C0_10_net));
    MX2B ENAMX_0_0_inst(.A(WEN), .B(INIT_CLIENT_0), .S(INITACTIVE)
        , .Y(ENABLEA_00));
    MX2 MX2_ADDRB_INT_6_inst(.A(RADDR[5]), .B(INITADDR[6]), .S(
        SAVEACTIVE), .Y(ADDRB_INT_6_net));
    MX2 MX2_ADDRA_INT_6_inst(.A(WADDR[5]), .B(INITADDR[6]), .S(
        INITACTIVE), .Y(ADDRA_INT_6_net));
    FLEXRAM512X18 SRAM_R0C0(.RADDR8(ADDRB_INT_8_net), .RADDR7(
        ADDRB_INT_7_net), .RADDR6(ADDRB_INT_6_net), .RADDR5(
        ADDRB_INT_5_net), .RADDR4(ADDRB_INT_4_net), .RADDR3(
        ADDRB_INT_3_net), .RADDR2(ADDRB_INT_2_net), .RADDR1(
        ADDRB_INT_1_net), .RADDR0(ADDRB_INT_0_net), .WADDR8(
        ADDRA_INT_8_net), .WADDR7(ADDRA_INT_7_net), .WADDR6(
        ADDRA_INT_6_net), .WADDR5(ADDRA_INT_5_net), .WADDR4(
        ADDRA_INT_4_net), .WADDR3(ADDRA_INT_3_net), .WADDR2(
        ADDRA_INT_2_net), .WADDR1(ADDRA_INT_1_net), .WADDR0(
        ADDRA_INT_0_net), .WD17(DINARESULT_C0_17_net), .WD16(
        DINARESULT_C0_16_net), .WD15(DINARESULT_C0_15_net), .WD14(
        DINARESULT_C0_14_net), .WD13(DINARESULT_C0_13_net), .WD12(
        DINARESULT_C0_12_net), .WD11(DINARESULT_C0_11_net), .WD10(
        DINARESULT_C0_10_net), .WD9(DINARESULT_C0_9_net), .WD8(
        DINARESULT_C0_8_net), .WD7(DINARESULT_C0_7_net), .WD6(
        DINARESULT_C0_6_net), .WD5(DINARESULT_C0_5_net), .WD4(
        DINARESULT_C0_4_net), .WD3(DINARESULT_C0_3_net), .WD2(
        DINARESULT_C0_2_net), .WD1(DINARESULT_C0_1_net), .WD0(
        DINARESULT_C0_0_net), .RW0(WIDTHB0X), .RW1(WIDTHB1X), 
        .WW0(WIDTHA0X), .WW1(WIDTHA1X), .PIPE(GND), .REN(
        ENABLEB_00), .WEN(ENABLEA_00), .RCLK(RWCLK), .WCLK(RWCLK), 
        .RESET(RESET), .RD17(), .RD16(), .RD15(RD[15]), .RD14(
        RD[14]), .RD13(RD[13]), .RD12(RD[12]), .RD11(RD[11]), 
        .RD10(RD[10]), .RD9(RD[9]), .RD8(INITDOUT0_8_net), .RD7(
        INITDOUT0_7_net), .RD6(INITDOUT0_6_net), .RD5(
        INITDOUT0_5_net), .RD4(INITDOUT0_4_net), .RD3(
        INITDOUT0_3_net), .RD2(INITDOUT0_2_net), .RD1(
        INITDOUT0_1_net), .RD0(INITDOUT0_0_net));
    defparam SRAM_R0C0.MEMORYFILE = "SRAM_R0C0.mem";
    MX2 MX2_ADDRA_INT_2_inst(.A(WADDR[1]), .B(INITADDR[2]), .S(
        INITACTIVE), .Y(ADDRA_INT_2_net));
    MX2 MX2_ADDRA_INT_0_inst(.A(ADDRA_GEN_NORMADDR_EXT_0_net), .B(
        INITADDR[0]), .S(INITACTIVE), .Y(ADDRA_INT_0_net));
    MX2 MX2_ADDRB_INT_1_inst(.A(RADDR[0]), .B(INITADDR[1]), .S(
        SAVEACTIVE), .Y(ADDRB_INT_1_net));
    MX2 MX2_ADDRA_INT_5_inst(.A(WADDR[4]), .B(INITADDR[5]), .S(
        INITACTIVE), .Y(ADDRA_INT_5_net));
    MX2 MX2_DINARESULT_C0_3_inst(.A(WD[3]), .B(INITDATA[3]), .S(
        BUFF_1_Y), .Y(DINARESULT_C0_3_net));
    MX2 MX2_ADDRB_INT_2_inst(.A(RADDR[1]), .B(INITADDR[2]), .S(
        SAVEACTIVE), .Y(ADDRB_INT_2_net));
    MX2 MX2_DINARESULT_C0_4_inst(.A(WD[4]), .B(INITDATA[4]), .S(
        BUFF_1_Y), .Y(DINARESULT_C0_4_net));
    MX2 MX2_ADDRA_INT_4_inst(.A(WADDR[3]), .B(INITADDR[4]), .S(
        INITACTIVE), .Y(ADDRA_INT_4_net));
    MX2 MX2_DINARESULT_C0_17_inst(.A(GND), .B(INITDATA_EXT_9_net), 
        .S(BUFF_0_Y), .Y(DINARESULT_C0_17_net));
    MX2 MX2_WIDTHA1X(.A(VCC), .B(GND), .S(INITACTIVE), .Y(
        WIDTHA1X));
    MX2B ENBMX_0_0_inst(.A(REN), .B(VCC), .S(SAVEACTIVE), .Y(
        ENABLEB_00));
    MX2 MX2_DINARESULT_C0_14_inst(.A(WD[14]), .B(
        INITDATA_EXT_9_net), .S(BUFF_0_Y), .Y(
        DINARESULT_C0_14_net));
    MX2 MX2_ADDRB_INT_3_inst(.A(RADDR[2]), .B(INITADDR[3]), .S(
        SAVEACTIVE), .Y(ADDRB_INT_3_net));
    MX2 MX2_DINARESULT_C0_12_inst(.A(WD[12]), .B(
        INITDATA_EXT_9_net), .S(BUFF_0_Y), .Y(
        DINARESULT_C0_12_net));
    MX2 MX2_DINARESULT_C0_8_inst(.A(WD[8]), .B(INITDATA[8]), .S(
        BUFF_1_Y), .Y(DINARESULT_C0_8_net));
    BUFF BUFF_0(.A(INITACTIVE), .Y(BUFF_0_Y));
    MX2 MX2_DINARESULT_C0_0_inst(.A(WD[0]), .B(INITDATA[0]), .S(
        BUFF_1_Y), .Y(DINARESULT_C0_0_net));
    MX2 MX2_DINARESULT_C0_16_inst(.A(GND), .B(INITDATA_EXT_9_net), 
        .S(BUFF_0_Y), .Y(DINARESULT_C0_16_net));
    MX2 MX2_ADDRA_INT_1_inst(.A(WADDR[0]), .B(INITADDR[1]), .S(
        INITACTIVE), .Y(ADDRA_INT_1_net));
    MX2 RWMUXA(.A(GND), .B(GND), .S(INITACTIVE), .Y(RWAXINT));
    MX2 MX2_DINARESULT_C0_15_inst(.A(WD[15]), .B(
        INITDATA_EXT_9_net), .S(BUFF_0_Y), .Y(
        DINARESULT_C0_15_net));
    MX2 MX2_DINARESULT_C0_9_inst(.A(WD[9]), .B(INITDATA_EXT_9_net)
        , .S(BUFF_0_Y), .Y(DINARESULT_C0_9_net));
    MX2 MX2_WIDTHA0X(.A(GND), .B(VCC), .S(INITACTIVE), .Y(
        WIDTHA0X));
    MX2 MX2_ADDRB_INT_0_inst(.A(ADDRB_GEN_NORMADDR_EXT_0_net), .B(
        INITADDR[0]), .S(SAVEACTIVE), .Y(ADDRB_INT_0_net));
    MX2 MX2_DINARESULT_C0_5_inst(.A(WD[5]), .B(INITDATA[5]), .S(
        BUFF_1_Y), .Y(DINARESULT_C0_5_net));
    MX2 MX2_ADDRB_INT_4_inst(.A(RADDR[3]), .B(INITADDR[4]), .S(
        SAVEACTIVE), .Y(ADDRB_INT_4_net));
    MX2 MX2_DINARESULT_C0_2_inst(.A(WD[2]), .B(INITDATA[2]), .S(
        BUFF_1_Y), .Y(DINARESULT_C0_2_net));
    MX2 RWMUXB(.A(GND), .B(VCC), .S(SAVEACTIVE), .Y(RWBXINT));
    MX2 MX2_DINARESULT_C0_7_inst(.A(WD[7]), .B(INITDATA[7]), .S(
        BUFF_1_Y), .Y(DINARESULT_C0_7_net));
    MX2 MX2_ADDRB_INT_5_inst(.A(RADDR[4]), .B(INITADDR[5]), .S(
        SAVEACTIVE), .Y(ADDRB_INT_5_net));
    MX2 MX2_DINARESULT_C0_13_inst(.A(WD[13]), .B(
        INITDATA_EXT_9_net), .S(BUFF_0_Y), .Y(
        DINARESULT_C0_13_net));
    MX2 MX2_DINARESULT_C0_11_inst(.A(WD[11]), .B(
        INITDATA_EXT_9_net), .S(BUFF_0_Y), .Y(
        DINARESULT_C0_11_net));
    MX2 MX2_WIDTHB1X(.A(VCC), .B(GND), .S(SAVEACTIVE), .Y(
        WIDTHB1X));
    MX2 MX2_ADDRB_INT_8_inst(.A(ADDRB_GEN_NORMADDR_EXT_0_net), .B(
        INITADDR[8]), .S(SAVEACTIVE), .Y(ADDRB_INT_8_net));
    MX2 MX2_DINARESULT_C0_6_inst(.A(WD[6]), .B(INITDATA[6]), .S(
        BUFF_1_Y), .Y(DINARESULT_C0_6_net));
    
endmodule
