`timescale 1 ns/100 ps
// Version: 7.1 7.1.0.14


module PLL_CLK100_10(POWERDOWN,CLKA,LOCK,GLA,YB,GLC,OADIVRST);
input POWERDOWN, CLKA;
output  LOCK, GLA, YB, GLC;
input  OADIVRST;

    wire VCC, GND;
    
    VCC VCC_1_net(.Y(VCC));
    GND GND_1_net(.Y(GND));
    PLL Core(.CLKA(CLKA), .EXTFB(GND), .POWERDOWN(POWERDOWN), 
        .GLA(GLA), .LOCK(LOCK), .GLB(), .YB(YB), .GLC(GLC), .YC(), 
        .OADIV0(GND), .OADIV1(GND), .OADIV2(GND), .OADIV3(GND), 
        .OADIV4(GND), .OADIVHALF(GND), .OADIVRST(OADIVRST), 
        .OAMUX0(GND), .OAMUX1(GND), .OAMUX2(VCC), .DLYGLA0(GND), 
        .DLYGLA1(GND), .DLYGLA2(GND), .DLYGLA3(GND), .DLYGLA4(GND)
        , .OBDIV0(VCC), .OBDIV1(VCC), .OBDIV2(VCC), .OBDIV3(VCC), 
        .OBDIV4(VCC), .OBMUX0(GND), .OBMUX1(GND), .OBMUX2(VCC), 
        .DLYYB0(GND), .DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), 
        .DLYYB4(GND), .DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), 
        .DLYGLB3(GND), .DLYGLB4(GND), .OCDIV0(VCC), .OCDIV1(GND), 
        .OCDIV2(GND), .OCDIV3(VCC), .OCDIV4(GND), .OCMUX0(GND), 
        .OCMUX1(GND), .OCMUX2(VCC), .DLYYC0(GND), .DLYYC1(GND), 
        .DLYYC2(GND), .DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), 
        .DLYGLC1(GND), .DLYGLC2(GND), .DLYGLC3(GND), .DLYGLC4(GND)
        , .FINDIV0(GND), .FINDIV1(VCC), .FINDIV2(GND), .FINDIV3(
        GND), .FINDIV4(VCC), .FINDIV5(GND), .FINDIV6(GND), 
        .FBDIV0(GND), .FBDIV1(VCC), .FBDIV2(GND), .FBDIV3(GND), 
        .FBDIV4(VCC), .FBDIV5(GND), .FBDIV6(GND), .FBDLY0(GND), 
        .FBDLY1(GND), .FBDLY2(GND), .FBDLY3(GND), .FBDLY4(GND), 
        .FBSEL0(VCC), .FBSEL1(GND), .XDLYSEL(GND), .VCOSEL0(GND), 
        .VCOSEL1(GND), .VCOSEL2(VCC));
    defparam Core.VCOFREQUENCY = 100.000;
    
endmodule
