m255
13
cModel Technology
dD:\Actelprj\Fusion_SRAM_Config\simulation
vcounter
In=R43SPZ161lAd@TCAW1M1
VAnifo>L@Fl`[iHbfbBZ=71
dD:\Actelprj\MasterSerial\simulation
w1186778579
FD:/Actelprj/MasterSerial/hdl/counter.v
L0 4
VAnifo>L@Fl`[iHbfbBZ=71
OW;L;6.1f;31
r1
31
o+incdir+D:/Actelprj/MasterSerial/hdl +incdir+D:/Actelprj/MasterSerial/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
vMasterSerial
IUUzWBCZ3<UlRWJKIP6]zT3
Vbe]4EGE2a@TcW^PhTH1500
dD:\Actelprj\MasterSerial\simulation
w1186778558
FD:/Actelprj/MasterSerial/hdl/MasterSerial.v
L0 3
Vbe]4EGE2a@TcW^PhTH1500
OW;L;6.1f;31
r1
31
o+incdir+D:/Actelprj/MasterSerial/hdl +incdir+D:/Actelprj/MasterSerial/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
n@master@serial
vNVM1
I]DXgedc=;AzQIIIE0ao3P3
VhbBbYZ8cBiGjbO7VemR733
dD:\Actelprj\MasterSerial\simulation
w1186616303
FD:/Actelprj/MasterSerial/smartgen/NVM1/NVM1.v
L0 5
VhbBbYZ8cBiGjbO7VemR733
OW;L;6.1f;31
r1
31
o+incdir+D:/Actelprj/MasterSerial/smartgen/NVM1 +incdir+D:/Actelprj/MasterSerial/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
n@n@v@m1
vNVM2
ID@8=aBJM`VGkeECPjF3d60
VcP?]bogXA`AIYQNZ@ilNh1
dD:\Actelprj\MasterSerial\simulation
w1186616284
FD:/Actelprj/MasterSerial/smartgen/NVM2/NVM2.v
L0 5
VcP?]bogXA`AIYQNZ@ilNh1
OW;L;6.1f;31
r1
31
o+incdir+D:/Actelprj/MasterSerial/smartgen/NVM2 +incdir+D:/Actelprj/MasterSerial/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
n@n@v@m2
vPLL_100_60
I2;igl0MPL]RgUWI3I;@kG3
VH8H^3gLgGRTl^iFhKTRNa2
dD:\Actelprj\MasterSerial\simulation
w1165371472
FD:/Actelprj/MasterSerial/smartgen/PLL_100_60/PLL_100_60.v
L0 5
VH8H^3gLgGRTl^iFhKTRNa2
OW;L;6.1f;31
r1
31
o+incdir+D:/Actelprj/MasterSerial/smartgen/PLL_100_60 +incdir+D:/Actelprj/MasterSerial/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
n@p@l@l_100_60
vRC_Oscillator
ISL;Y;<Ufca8C1=2clh:[03
V[F0caLg[1^63cYG`oQ[e10
dD:\Actelprj\MasterSerial\simulation
w1165371442
FD:/Actelprj/MasterSerial/smartgen/RC_Oscillator/RC_Oscillator.v
L0 5
V[F0caLg[1^63cYG`oQ[e10
OW;L;6.1f;31
r1
31
o+incdir+D:/Actelprj/MasterSerial/smartgen/RC_Oscillator +incdir+D:/Actelprj/MasterSerial/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
n@r@c_@oscillator
vShiftReg
I8cJfcK<iId3R8D4V>=KJI3
VdTk3?TNe^DlFNUC01L`141
dD:\Actelprj\MasterSerial\simulation
w1186777499
FD:/Actelprj/MasterSerial/hdl/ShiftReg.v
L0 2
VdTk3?TNe^DlFNUC01L`141
OW;L;6.1f;31
r1
31
o+incdir+D:/Actelprj/MasterSerial/hdl +incdir+D:/Actelprj/MasterSerial/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
n@shift@reg
vsr8ps
IAL<GR90h[GnBKd5LCFj^N0
V@EOX?H7enoB2B@FFAaNL]2
w1160610455
FD:/Actelprj/Fusion_SRAM_Config/hdl/vsprom_comp.v
L0 61
V@EOX?H7enoB2B@FFAaNL]2
OW;L;6.1b;31
r1
31
o+incdir+D:/Actelprj/Fusion_SRAM_Config/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
vSRAM_Config
I55l@Zk;zK4TF=5Q?;=Zf61
VYZBTUj[8b1DEQ5U08k2kb1
dD:\Actelprj\SPIFlashMemory\simulation
w1161381836
FD:/Actelprj/SPIFlashMemory/smartgen/SRAM_Config/SRAM_Config.v
L0 5
VYZBTUj[8b1DEQ5U08k2kb1
OW;L;6.1b;31
r1
31
o+incdir+D:/Actelprj/SPIFlashMemory/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
n@s@r@a@m_@config
vSRAM_Config1
IH3OoXbEk_J@BbjggfN?;i3
V]od`=TUIn4K5zg>TlK5dk2
dD:\Actelprj\SPIFlashMemory\simulation
w1171705235
FD:/Actelprj/SPIFlashMemory/smartgen/SRAM_Config1/SRAM_Config1.v
L0 5
V]od`=TUIn4K5zg>TlK5dk2
OW;L;6.1b;31
r1
31
o+incdir+D:/Actelprj/SPIFlashMemory/smartgen/SRAM_Config1 +incdir+D:/Actelprj/SPIFlashMemory/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
n@s@r@a@m_@config1
vSRAM_Config2
IeA3_mZW8NJS[=66:iSza13
V30WiDlWV8PIB]Xd9AGN7T3
dD:\Actelprj\SPIFlashMemory\simulation
w1171705257
FD:/Actelprj/SPIFlashMemory/smartgen/SRAM_Config2/SRAM_Config2.v
L0 5
V30WiDlWV8PIB]Xd9AGN7T3
OW;L;6.1b;31
r1
31
o+incdir+D:/Actelprj/SPIFlashMemory/smartgen/SRAM_Config2 +incdir+D:/Actelprj/SPIFlashMemory/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
n@s@r@a@m_@config2
vstimulus
IR=Ol3BKj6idhcb@RiM8182
V@?fPE<<ONH>Dza6AJzEk=0
dD:\Actelprj\MasterSerial\simulation
w1186697924
FD:/Actelprj/MasterSerial/stimulus/MasterSerial_tb.v
L0 25
V@?fPE<<ONH>Dza6AJzEk=0
OW;L;6.1f;31
r1
31
o+incdir+D:/Actelprj/MasterSerial/stimulus +incdir+D:/Actelprj/MasterSerial/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
vtb_clock_minmax
IY?cWAe;[F9]EeFbEEld9l1
V]<miNJ_R^N1gLiJ7V>ii92
dD:\Actelprj\MasterSerial\simulation
w1186697924
FD:/Actelprj/MasterSerial/stimulus/MasterSerial_tb.v
L0 126
V]<miNJ_R^N1gLiJ7V>ii92
OW;L;6.1f;31
r1
31
o+incdir+D:/Actelprj/MasterSerial/stimulus +incdir+D:/Actelprj/MasterSerial/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
vtestbench
Ink8QcLdSbAca=6LI@5MQb3
VhGfW:390DM[oDMzegDH9`2
dD:\Actelprj\MasterSerial\simulation
w1186697924
FD:/Actelprj/MasterSerial/stimulus/MasterSerial_tb.v
L0 233
VhGfW:390DM[oDMzegDH9`2
OW;L;6.1f;31
r1
31
o+incdir+D:/Actelprj/MasterSerial/stimulus +incdir+D:/Actelprj/MasterSerial/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
vvpcounter
IWKYP9L=EGnNRDGg7km5HZ0
VQ@`Fgg4GNeCK_@Uo]gkWO2
w1160610455
FD:/Actelprj/Fusion_SRAM_Config/hdl/vsprom_comp.v
L0 3
VQ@`Fgg4GNeCK_@Uo]gkWO2
OW;L;6.1b;31
r1
31
o+incdir+D:/Actelprj/Fusion_SRAM_Config/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
vvsprom
IoZGVd<9edRQaBDg`e?IgR0
VPmfYoJ]Q3kaXM>7fc>3dd3
w1160619862
FD:/Actelprj/Fusion_SRAM_Config/hdl/vsprom.v
L0 3
VPmfYoJ]Q3kaXM>7fc>3dd3
OW;L;6.1b;31
r1
31
o+incdir+D:/Actelprj/Fusion_SRAM_Config/hdl -work presynth -O0
tGenerateLoopIterationMax 100000
