// ShiftReg.v
/*
--****************************************************************************
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-- CONTAINED IN THIS APPLICATION NOTE. 
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-- NO SUPPORT/NO WARRANTY. THE DESIGN FILES AND DOCUMENTATION ARE PROVIDED
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*/

module ShiftReg (d_in, init, load, clk, d_out);

input [7:0] d_in;
input load;
input init;
input clk;

output d_out;
reg d_out;

reg d_reg;
reg [7:0] d_latch;

always @ (negedge clk)
begin
if (load)
  begin
	  d_latch = d_in;
	  d_reg = d_in[7];
  end
else 
  begin
	  d_latch[7] = d_latch[6]; //shift the data out. MSB first
	  d_latch[6] = d_latch[5];
	  d_latch[5] = d_latch[4];
	  d_latch[4] = d_latch[3];
	  d_latch[3] = d_latch[2];
	  d_latch[1] = d_latch[0];
	  d_latch[0] = 1'bz;
	  d_reg = d_latch[7];
   end
end

always @(init or d_reg)
begin
	if (~init)
	  d_out <= 1'bz;
	else
	  d_out <= d_reg;
end

endmodule
