`timescale 1 ns/100 ps
// Version: 7.3 SP1 7.3.1.9


module ShiftReg(
       rom_data_o,
       SCK_c,
       d_reg,
       load
    );
input  [7:2] rom_data_o;
input  SCK_c;
output d_reg;
input  load;

    wire \d_latch_10[6]_net_1 , \d_latch[5]_net_1 , 
        \d_latch_10[5]_net_1 , \d_latch[4]_net_1 , 
        \d_latch_10[4]_net_1 , \d_latch[3]_net_1 , 
        \d_latch_10[3]_net_1 , \d_latch[2]_net_1 , d_reg_4_net_1, 
        \d_latch[6]_net_1 , VCC, GND, GND_net_1, VCC_net_1;
    
    MX2 \d_latch_10[6]  (.A(\d_latch[5]_net_1 ), .B(rom_data_o[6]), .S(
        load), .Y(\d_latch_10[6]_net_1 ));
    DFN0 \d_latch[6]  (.D(\d_latch_10[6]_net_1 ), .CLK(SCK_c), .Q(
        \d_latch[6]_net_1 ));
    DFN0E1 \d_latch[2]  (.D(rom_data_o[2]), .CLK(SCK_c), .E(load), .Q(
        \d_latch[2]_net_1 ));
    DFN0 \d_latch[5]  (.D(\d_latch_10[5]_net_1 ), .CLK(SCK_c), .Q(
        \d_latch[5]_net_1 ));
    DFN0 \d_latch[3]  (.D(\d_latch_10[3]_net_1 ), .CLK(SCK_c), .Q(
        \d_latch[3]_net_1 ));
    VCC VCC_i_0 (.Y(VCC_net_1));
    DFN0 d_reg_inst_1 (.D(d_reg_4_net_1), .CLK(SCK_c), .Q(d_reg));
    VCC VCC_i (.Y(VCC));
    MX2 d_reg_4 (.A(\d_latch[6]_net_1 ), .B(rom_data_o[7]), .S(load), 
        .Y(d_reg_4_net_1));
    MX2 \d_latch_10[4]  (.A(\d_latch[3]_net_1 ), .B(rom_data_o[4]), .S(
        load), .Y(\d_latch_10[4]_net_1 ));
    GND GND_i_0 (.Y(GND_net_1));
    GND GND_i (.Y(GND));
    DFN0 \d_latch[4]  (.D(\d_latch_10[4]_net_1 ), .CLK(SCK_c), .Q(
        \d_latch[4]_net_1 ));
    MX2 \d_latch_10[3]  (.A(\d_latch[2]_net_1 ), .B(rom_data_o[3]), .S(
        load), .Y(\d_latch_10[3]_net_1 ));
    MX2 \d_latch_10[5]  (.A(\d_latch[4]_net_1 ), .B(rom_data_o[5]), .S(
        load), .Y(\d_latch_10[5]_net_1 ));
    
endmodule


module NVM1(
       rom_data_o,
       rom_addr,
       rom_data_1,
       term_cnt,
       VCC,
       CLK60MHz,
       GND
    );
input  [7:0] rom_data_o;
input  [17:0] rom_addr;
output [7:0] rom_data_1;
input  term_cnt;
input  VCC;
input  CLK60MHz;
input  GND;

    wire NVM_INST_BUSY_0, \NVM_INST_RD[8]_0 , \NVM_INST_RD[9]_0 , 
        \NVM_INST_RD[10]_0 , \NVM_INST_RD[11]_0 , \NVM_INST_RD[12]_0 , 
        \NVM_INST_RD[13]_0 , \NVM_INST_RD[14]_0 , \NVM_INST_RD[15]_0 , 
        \NVM_INST_RD[16]_0 , \NVM_INST_RD[17]_0 , \NVM_INST_RD[18]_0 , 
        \NVM_INST_RD[19]_0 , \NVM_INST_RD[20]_0 , \NVM_INST_RD[21]_0 , 
        \NVM_INST_RD[22]_0 , \NVM_INST_RD[23]_0 , \NVM_INST_RD[24]_0 , 
        \NVM_INST_RD[25]_0 , \NVM_INST_RD[26]_0 , \NVM_INST_RD[27]_0 , 
        \NVM_INST_RD[28]_0 , \NVM_INST_RD[29]_0 , \NVM_INST_RD[30]_0 , 
        \NVM_INST_RD[31]_0 , \NVM_INST_STATUS[0]_0 , 
        \NVM_INST_STATUS[1]_0 , GND_net_1, VCC_net_1;
    
    VCC VCC_i_0 (.Y(VCC_net_1));
    GND GND_i_0 (.Y(GND_net_1));
    NVM #( .MEMORYFILE("NVM1.mem") )  NVM_INST (.RD({
        \NVM_INST_RD[31]_0 , \NVM_INST_RD[30]_0 , \NVM_INST_RD[29]_0 , 
        \NVM_INST_RD[28]_0 , \NVM_INST_RD[27]_0 , \NVM_INST_RD[26]_0 , 
        \NVM_INST_RD[25]_0 , \NVM_INST_RD[24]_0 , \NVM_INST_RD[23]_0 , 
        \NVM_INST_RD[22]_0 , \NVM_INST_RD[21]_0 , \NVM_INST_RD[20]_0 , 
        \NVM_INST_RD[19]_0 , \NVM_INST_RD[18]_0 , \NVM_INST_RD[17]_0 , 
        \NVM_INST_RD[16]_0 , \NVM_INST_RD[15]_0 , \NVM_INST_RD[14]_0 , 
        \NVM_INST_RD[13]_0 , \NVM_INST_RD[12]_0 , \NVM_INST_RD[11]_0 , 
        \NVM_INST_RD[10]_0 , \NVM_INST_RD[9]_0 , \NVM_INST_RD[8]_0 , 
        rom_data_1[7], rom_data_1[6], rom_data_1[5], rom_data_1[4], 
        rom_data_1[3], rom_data_1[2], rom_data_1[1], rom_data_1[0]}), 
        .BUSY(NVM_INST_BUSY_0), .STATUS({\NVM_INST_STATUS[1]_0 , 
        \NVM_INST_STATUS[0]_0 }), .ADDR({rom_addr[17], rom_addr[16], 
        rom_addr[15], rom_addr[14], rom_addr[13], rom_addr[12], 
        rom_addr[11], rom_addr[10], rom_addr[9], rom_addr[8], 
        rom_addr[7], rom_addr[6], rom_addr[5], rom_addr[4], 
        rom_addr[3], rom_addr[2], rom_addr[1], rom_addr[0]}), .WD({GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        rom_data_o[7], rom_data_o[6], rom_data_o[5], rom_data_o[4], 
        rom_data_o[3], rom_data_o[2], rom_data_o[1], rom_data_o[0]}), 
        .DATAWIDTH({GND, GND}), .REN(VCC), .WEN(GND), .PROGRAM(GND), 
        .SPAREPAGE(GND), .AUXBLOCK(GND), .READNEXT(GND), .ERASEPAGE(
        GND), .UNPROTECTPAGE(GND), .DISCARDPAGE(GND), 
        .OVERWRITEPROTECT(GND), .PAGELOSSPROTECT(GND), .CLK(CLK60MHz), 
        .RESET(term_cnt), .PAGESTATUS(GND), .OVERWRITEPAGE(GND), .PIPE(
        GND), .LOCKREQUEST(GND));
    VCC VCC_i (.Y(VCC));
    GND GND_i (.Y(GND));
    
endmodule


module counter(
       rom_addr,
       SCK_c,
       SCK_c_1,
       SCK_c_0,
       load,
       INIT_c,
       INIT_c_1,
       term_cnt,
       INIT_c_0
    );
output [18:0] rom_addr;
input  SCK_c;
input  SCK_c_1;
input  SCK_c_0;
output load;
input  INIT_c;
input  INIT_c_1;
output term_cnt;
input  INIT_c_0;

    wire \DWACT_ADD_CI_0_g_array_10[0] , \DWACT_ADD_CI_0_g_array_3[0] , 
        \DWACT_ADD_CI_0_pog_array_2_1[0] , 
        \DWACT_ADD_CI_0_g_array_2[0] , \DWACT_ADD_CI_0_pog_array_2[0] , 
        \DWACT_ADD_CI_0_g_array_1[0] , \DWACT_ADD_CI_0_pog_array_1[0] , 
        \DWACT_ADD_CI_0_g_array_11_2[0] , 
        \DWACT_ADD_CI_0_pog_array_1_5[0] , \DWACT_ADD_CI_0_TMP[0] , 
        I_91, un1_cnt_net_1, \cnt[1]_net_1 , \cnt[2]_net_1 , 
        \cnt[0]_net_1 , \address_4[15]_net_1 , I_78, 
        \DWACT_ADD_CI_0_g_array_4[0] , \DWACT_ADD_CI_0_pog_array_3[0] , 
        \DWACT_ADD_CI_0_g_array_11_1[0] , 
        \DWACT_ADD_CI_0_pog_array_1_3[0] , 
        \DWACT_ADD_CI_0_g_array_11[0] , 
        \DWACT_ADD_CI_0_pog_array_1_1[0] , 
        \DWACT_ADD_CI_0_g_array_1_0[0] , \DWACT_ADD_CI_0_TMP_0[0] , 
        \DWACT_ADD_CI_0_g_array_11_3[0] , 
        \DWACT_ADD_CI_0_pog_array_1_7[0] , 
        \DWACT_ADD_CI_0_g_array_12_1[0] , 
        \DWACT_ADD_CI_0_g_array_12_2[0] , 
        \DWACT_ADD_CI_0_g_array_12_3[0] , 
        \DWACT_ADD_CI_0_g_array_12_4[0] , 
        \DWACT_ADD_CI_0_g_array_12_5[0] , 
        \DWACT_ADD_CI_0_g_array_12[0] , 
        \DWACT_ADD_CI_0_g_array_12_7[0] , term_cnt_16_net_1, 
        term_cnt_9_net_1, term_cnt_10_net_1, term_cnt_13_net_1, 
        term_cnt_14_net_1, term_cnt_1_net_1, term_cnt_2_net_1, 
        term_cnt_11_net_1, term_cnt_3_net_1, term_cnt_5_net_1, 
        term_cnt_7_net_1, \address_4[18]_net_1 , I_69, 
        \address_4[17]_net_1 , I_70, \address_4[16]_net_1 , I_63, 
        \address_4[14]_net_1 , I_76, \address_4[13]_net_1 , I_66, 
        \address_4[12]_net_1 , I_60, \address_4[11]_net_1 , I_72, 
        \address_4[10]_net_1 , I_74, \address_4[9]_net_1 , I_65, 
        \address_4[8]_net_1 , I_64, \address_4[7]_net_1 , I_62, 
        \address_4[6]_net_1 , I_77, \address_4[5]_net_1 , I_75, 
        \address_4[4]_net_1 , I_71, \address_4[3]_net_1 , I_73, 
        \address_4[2]_net_1 , I_67, \address_4[1]_net_1 , I_61, 
        \address_4[0]_net_1 , \DWACT_ADD_CI_0_partial_sum[0] , 
        \cnt_4[2]_net_1 , I_14, \cnt_4[1]_net_1 , I_13, 
        \cnt_4[0]_net_1 , \DWACT_ADD_CI_0_partial_sum_0[0] , 
        load_5_net_1, \DWACT_ADD_CI_0_pog_array_1_6[0] , 
        \DWACT_ADD_CI_0_pog_array_1_2[0] , 
        \DWACT_ADD_CI_0_pog_array_2_2[0] , 
        \DWACT_ADD_CI_0_pog_array_1_4[0] , VCC, GND, GND_net_1, 
        VCC_net_1;
    
    NOR2B un1_address_I_108 (.A(\DWACT_ADD_CI_0_g_array_10[0] ), .B(
        \DWACT_ADD_CI_0_pog_array_1_5[0] ), .Y(
        \DWACT_ADD_CI_0_g_array_11_2[0] ));
    NOR2B un1_address_I_100 (.A(\DWACT_ADD_CI_0_g_array_1[0] ), .B(
        \DWACT_ADD_CI_0_pog_array_1[0] ), .Y(
        \DWACT_ADD_CI_0_g_array_2[0] ));
    NOR3C term_cnt_14 (.A(term_cnt_1_net_1), .B(term_cnt_2_net_1), .C(
        term_cnt_11_net_1), .Y(term_cnt_14_net_1));
    NOR3C term_cnt_10 (.A(rom_addr[4]), .B(rom_addr[5]), .C(
        term_cnt_5_net_1), .Y(term_cnt_10_net_1));
    DFN0 \address[2]  (.D(\address_4[2]_net_1 ), .CLK(SCK_c_0), .Q(
        rom_addr[2]));
    NOR2B \address_4[13]  (.A(I_66), .B(INIT_c_0), .Y(
        \address_4[13]_net_1 ));
    DFN1 \cnt[2]  (.D(\cnt_4[2]_net_1 ), .CLK(SCK_c_0), .Q(
        \cnt[2]_net_1 ));
    NOR2B \address_4[5]  (.A(I_75), .B(INIT_c_1), .Y(
        \address_4[5]_net_1 ));
    DFN1 \cnt[1]  (.D(\cnt_4[1]_net_1 ), .CLK(SCK_c_0), .Q(
        \cnt[1]_net_1 ));
    AND2 un1_address_I_117 (.A(rom_addr[12]), .B(rom_addr[13]), .Y(
        \DWACT_ADD_CI_0_pog_array_1_5[0] ));
    XOR2 un1_address_I_73 (.A(rom_addr[3]), .B(
        \DWACT_ADD_CI_0_g_array_12[0] ), .Y(I_73));
    NOR2B \address_4[2]  (.A(I_67), .B(INIT_c_1), .Y(
        \address_4[2]_net_1 ));
    DFN0 \address[16]  (.D(\address_4[16]_net_1 ), .CLK(SCK_c), .Q(
        rom_addr[16]));
    NOR2B un1_address_I_87 (.A(\DWACT_ADD_CI_0_g_array_2[0] ), .B(
        \DWACT_ADD_CI_0_pog_array_2[0] ), .Y(
        \DWACT_ADD_CI_0_g_array_3[0] ));
    NOR2B \address_4[8]  (.A(I_64), .B(INIT_c_1), .Y(
        \address_4[8]_net_1 ));
    XOR2 un1_address_I_65 (.A(rom_addr[9]), .B(
        \DWACT_ADD_CI_0_g_array_12_3[0] ), .Y(I_65));
    AND2 un1_address_I_111 (.A(rom_addr[4]), .B(rom_addr[5]), .Y(
        \DWACT_ADD_CI_0_pog_array_1_1[0] ));
    XOR2 un1_address_I_67 (.A(rom_addr[2]), .B(
        \DWACT_ADD_CI_0_g_array_1[0] ), .Y(I_67));
    NOR3C term_cnt_16 (.A(term_cnt_9_net_1), .B(term_cnt_10_net_1), .C(
        term_cnt_13_net_1), .Y(term_cnt_16_net_1));
    DFN0 \address[12]  (.D(\address_4[12]_net_1 ), .CLK(SCK_c_1), .Q(
        rom_addr[12]));
    AND2 un1_address_I_113 (.A(\DWACT_ADD_CI_0_pog_array_1_1[0] ), .B(
        \DWACT_ADD_CI_0_pog_array_1_2[0] ), .Y(
        \DWACT_ADD_CI_0_pog_array_2[0] ));
    NOR2B \address_4[6]  (.A(I_77), .B(INIT_c_1), .Y(
        \address_4[6]_net_1 ));
    VCC VCC_i (.Y(VCC));
    AND2 un1_address_I_116 (.A(rom_addr[8]), .B(rom_addr[9]), .Y(
        \DWACT_ADD_CI_0_pog_array_1_3[0] ));
    AND2 un1_address_I_114 (.A(\DWACT_ADD_CI_0_pog_array_1_3[0] ), .B(
        \DWACT_ADD_CI_0_pog_array_1_4[0] ), .Y(
        \DWACT_ADD_CI_0_pog_array_2_1[0] ));
    NOR3C un1_cnt (.A(\cnt[1]_net_1 ), .B(\cnt[2]_net_1 ), .C(
        \cnt[0]_net_1 ), .Y(un1_cnt_net_1));
    NOR2B un1_address_I_86 (.A(\DWACT_ADD_CI_0_g_array_3[0] ), .B(
        \DWACT_ADD_CI_0_pog_array_1_3[0] ), .Y(
        \DWACT_ADD_CI_0_g_array_11_1[0] ));
    XOR2 un1_address_I_72 (.A(rom_addr[11]), .B(
        \DWACT_ADD_CI_0_g_array_12_4[0] ), .Y(I_72));
    DFN0 \address[13]  (.D(\address_4[13]_net_1 ), .CLK(SCK_c_1), .Q(
        rom_addr[13]));
    XOR2 un1_address_I_66 (.A(rom_addr[13]), .B(
        \DWACT_ADD_CI_0_g_array_12_5[0] ), .Y(I_66));
    XOR2 un1_address_I_69 (.A(rom_addr[18]), .B(
        \DWACT_ADD_CI_0_g_array_11_3[0] ), .Y(I_69));
    XOR2 un1_address_I_70 (.A(rom_addr[17]), .B(
        \DWACT_ADD_CI_0_g_array_12_7[0] ), .Y(I_70));
    AND2 un1_cnt_1_I_1 (.A(\cnt[0]_net_1 ), .B(term_cnt), .Y(
        \DWACT_ADD_CI_0_TMP_0[0] ));
    NOR3C term_cnt_11 (.A(rom_addr[8]), .B(rom_addr[9]), .C(
        term_cnt_3_net_1), .Y(term_cnt_11_net_1));
    NOR2B un1_address_I_90 (.A(\DWACT_ADD_CI_0_g_array_4[0] ), .B(
        \DWACT_ADD_CI_0_pog_array_1_7[0] ), .Y(
        \DWACT_ADD_CI_0_g_array_11_3[0] ));
    AND2 un1_address_I_119 (.A(rom_addr[14]), .B(rom_addr[15]), .Y(
        \DWACT_ADD_CI_0_pog_array_1_6[0] ));
    NOR2B un1_cnt_1_I_15 (.A(\DWACT_ADD_CI_0_TMP_0[0] ), .B(
        \cnt[1]_net_1 ), .Y(\DWACT_ADD_CI_0_g_array_1_0[0] ));
    DFN0 \address[7]  (.D(\address_4[7]_net_1 ), .CLK(SCK_c_1), .Q(
        rom_addr[7]));
    NOR2B \address_4[17]  (.A(I_70), .B(INIT_c_0), .Y(
        \address_4[17]_net_1 ));
    DFN0 \address[1]  (.D(\address_4[1]_net_1 ), .CLK(SCK_c_0), .Q(
        rom_addr[1]));
    XOR2 un1_cnt_1_I_9 (.A(\cnt[0]_net_1 ), .B(term_cnt), .Y(
        \DWACT_ADD_CI_0_partial_sum_0[0] ));
    DFN1 \cnt[0]  (.D(\cnt_4[0]_net_1 ), .CLK(SCK_c_0), .Q(
        \cnt[0]_net_1 ));
    DFN0 \address[0]  (.D(\address_4[0]_net_1 ), .CLK(SCK_c_0), .Q(
        rom_addr[0]));
    DFN0 load_inst_1 (.D(load_5_net_1), .CLK(SCK_c_0), .Q(load));
    NOR2B un1_address_I_105 (.A(\DWACT_ADD_CI_0_g_array_1[0] ), .B(
        rom_addr[2]), .Y(\DWACT_ADD_CI_0_g_array_12[0] ));
    NOR2B \address_4[14]  (.A(I_76), .B(INIT_c_0), .Y(
        \address_4[14]_net_1 ));
    NOR3C term_cnt_9 (.A(rom_addr[0]), .B(rom_addr[1]), .C(
        term_cnt_7_net_1), .Y(term_cnt_9_net_1));
    NOR2B \address_4[11]  (.A(I_72), .B(INIT_c_0), .Y(
        \address_4[11]_net_1 ));
    DFN0 \address[10]  (.D(\address_4[10]_net_1 ), .CLK(SCK_c_1), .Q(
        rom_addr[10]));
    NOR2B \cnt_4[1]  (.A(I_13), .B(INIT_c), .Y(\cnt_4[1]_net_1 ));
    NOR2B term_cnt_2 (.A(rom_addr[13]), .B(rom_addr[12]), .Y(
        term_cnt_2_net_1));
    XOR2 un1_address_I_75 (.A(rom_addr[5]), .B(
        \DWACT_ADD_CI_0_g_array_12_1[0] ), .Y(I_75));
    DFN0 \address[4]  (.D(\address_4[4]_net_1 ), .CLK(SCK_c_0), .Q(
        rom_addr[4]));
    XOR2 un1_cnt_1_I_14 (.A(\cnt[2]_net_1 ), .B(
        \DWACT_ADD_CI_0_g_array_1_0[0] ), .Y(I_14));
    XOR2 un1_address_I_77 (.A(rom_addr[6]), .B(
        \DWACT_ADD_CI_0_g_array_11[0] ), .Y(I_77));
    XOR2 un1_address_I_61 (.A(rom_addr[1]), .B(\DWACT_ADD_CI_0_TMP[0] )
        , .Y(I_61));
    NOR2B un1_address_I_97 (.A(\DWACT_ADD_CI_0_g_array_11[0] ), .B(
        rom_addr[6]), .Y(\DWACT_ADD_CI_0_g_array_12_2[0] ));
    GND GND_i (.Y(GND));
    XOR2 un1_address_I_64 (.A(rom_addr[8]), .B(
        \DWACT_ADD_CI_0_g_array_3[0] ), .Y(I_64));
    AND2 un1_address_I_112 (.A(rom_addr[10]), .B(rom_addr[11]), .Y(
        \DWACT_ADD_CI_0_pog_array_1_4[0] ));
    NOR2B \address_4[4]  (.A(I_71), .B(INIT_c_1), .Y(
        \address_4[4]_net_1 ));
    DFN0 \address[5]  (.D(\address_4[5]_net_1 ), .CLK(SCK_c_0), .Q(
        rom_addr[5]));
    AND2 un1_address_I_118 (.A(rom_addr[6]), .B(rom_addr[7]), .Y(
        \DWACT_ADD_CI_0_pog_array_1_2[0] ));
    AND2 un1_address_I_110 (.A(\DWACT_ADD_CI_0_pog_array_2_1[0] ), .B(
        \DWACT_ADD_CI_0_pog_array_2_2[0] ), .Y(
        \DWACT_ADD_CI_0_pog_array_3[0] ));
    NOR2B un1_address_I_107 (.A(\DWACT_ADD_CI_0_g_array_4[0] ), .B(
        rom_addr[16]), .Y(\DWACT_ADD_CI_0_g_array_12_7[0] ));
    NOR2B term_cnt_1 (.A(rom_addr[15]), .B(rom_addr[14]), .Y(
        term_cnt_1_net_1));
    NOR2B \address_4[18]  (.A(I_69), .B(INIT_c_0), .Y(
        \address_4[18]_net_1 ));
    DFN0 \address[9]  (.D(\address_4[9]_net_1 ), .CLK(SCK_c_1), .Q(
        rom_addr[9]));
    DFN0 \address[11]  (.D(\address_4[11]_net_1 ), .CLK(SCK_c_1), .Q(
        rom_addr[11]));
    NOR2B term_cnt_7 (.A(rom_addr[3]), .B(rom_addr[2]), .Y(
        term_cnt_7_net_1));
    DFN0 \address[3]  (.D(\address_4[3]_net_1 ), .CLK(SCK_c_0), .Q(
        rom_addr[3]));
    XOR2 un1_address_I_76 (.A(rom_addr[14]), .B(
        \DWACT_ADD_CI_0_g_array_11_2[0] ), .Y(I_76));
    NOR2B un1_address_I_101 (.A(\DWACT_ADD_CI_0_g_array_11_1[0] ), .B(
        rom_addr[10]), .Y(\DWACT_ADD_CI_0_g_array_12_4[0] ));
    NOR2B un1_address_I_79 (.A(\DWACT_ADD_CI_0_TMP[0] ), .B(
        rom_addr[1]), .Y(\DWACT_ADD_CI_0_g_array_1[0] ));
    DFN0 \address[15]  (.D(\address_4[15]_net_1 ), .CLK(SCK_c_1), .Q(
        rom_addr[15]));
    NOR2B \address_4[3]  (.A(I_73), .B(INIT_c_1), .Y(
        \address_4[3]_net_1 ));
    NOR2B un1_address_I_103 (.A(\DWACT_ADD_CI_0_g_array_3[0] ), .B(
        \DWACT_ADD_CI_0_pog_array_3[0] ), .Y(
        \DWACT_ADD_CI_0_g_array_4[0] ));
    NOR2B \address_4[12]  (.A(I_60), .B(INIT_c_0), .Y(
        \address_4[12]_net_1 ));
    NOR2B un1_address_I_106 (.A(\DWACT_ADD_CI_0_g_array_2[0] ), .B(
        \DWACT_ADD_CI_0_pog_array_1_1[0] ), .Y(
        \DWACT_ADD_CI_0_g_array_11[0] ));
    NOR2B un1_address_I_104 (.A(\DWACT_ADD_CI_0_g_array_10[0] ), .B(
        rom_addr[12]), .Y(\DWACT_ADD_CI_0_g_array_12_5[0] ));
    AND2 un1_address_I_1 (.A(rom_addr[0]), .B(un1_cnt_net_1), .Y(
        \DWACT_ADD_CI_0_TMP[0] ));
    NOR2B \address_4[16]  (.A(I_63), .B(INIT_c_0), .Y(
        \address_4[16]_net_1 ));
    DFN0 \address[14]  (.D(\address_4[14]_net_1 ), .CLK(SCK_c_1), .Q(
        rom_addr[14]));
    NOR3C term_cnt_13 (.A(rom_addr[16]), .B(rom_addr[17]), .C(
        rom_addr[18]), .Y(term_cnt_13_net_1));
    NOR2B \cnt_4[0]  (.A(\DWACT_ADD_CI_0_partial_sum_0[0] ), .B(INIT_c)
        , .Y(\cnt_4[0]_net_1 ));
    XOR2 un1_address_I_78 (.A(rom_addr[15]), .B(I_91), .Y(I_78));
    XOR2 un1_cnt_1_I_13 (.A(\cnt[1]_net_1 ), .B(
        \DWACT_ADD_CI_0_TMP_0[0] ), .Y(I_13));
    NOR2B \address_4[9]  (.A(I_65), .B(INIT_c_1), .Y(
        \address_4[9]_net_1 ));
    NOR2B \address_4[7]  (.A(I_62), .B(INIT_c_1), .Y(
        \address_4[7]_net_1 ));
    DFN0 \address[17]  (.D(\address_4[17]_net_1 ), .CLK(SCK_c), .Q(
        rom_addr[17]));
    NOR2B un1_address_I_98 (.A(\DWACT_ADD_CI_0_g_array_3[0] ), .B(
        rom_addr[8]), .Y(\DWACT_ADD_CI_0_g_array_12_3[0] ));
    XOR2 un1_address_I_63 (.A(rom_addr[16]), .B(
        \DWACT_ADD_CI_0_g_array_4[0] ), .Y(I_63));
    AND2 un1_address_I_109 (.A(rom_addr[2]), .B(rom_addr[3]), .Y(
        \DWACT_ADD_CI_0_pog_array_1[0] ));
    NOR2B term_cnt_5 (.A(rom_addr[7]), .B(rom_addr[6]), .Y(
        term_cnt_5_net_1));
    DFN0 \address[18]  (.D(\address_4[18]_net_1 ), .CLK(SCK_c), .Q(
        rom_addr[18]));
    NOR2B \address_4[15]  (.A(I_78), .B(INIT_c_0), .Y(
        \address_4[15]_net_1 ));
    OR2B term_cnt_inst_1 (.A(term_cnt_16_net_1), .B(term_cnt_14_net_1), 
        .Y(term_cnt));
    NOR2B \address_4[0]  (.A(\DWACT_ADD_CI_0_partial_sum[0] ), .B(
        INIT_c), .Y(\address_4[0]_net_1 ));
    XOR2 un1_address_I_71 (.A(rom_addr[4]), .B(
        \DWACT_ADD_CI_0_g_array_2[0] ), .Y(I_71));
    NOR2B \address_4[1]  (.A(I_61), .B(INIT_c), .Y(
        \address_4[1]_net_1 ));
    NOR2B un1_address_I_82 (.A(\DWACT_ADD_CI_0_g_array_3[0] ), .B(
        \DWACT_ADD_CI_0_pog_array_2_1[0] ), .Y(
        \DWACT_ADD_CI_0_g_array_10[0] ));
    XOR2 un1_address_I_74 (.A(rom_addr[10]), .B(
        \DWACT_ADD_CI_0_g_array_11_1[0] ), .Y(I_74));
    NOR2B \cnt_4[2]  (.A(I_14), .B(INIT_c), .Y(\cnt_4[2]_net_1 ));
    NOR2B \address_4[10]  (.A(I_74), .B(INIT_c_1), .Y(
        \address_4[10]_net_1 ));
    NOR2B un1_address_I_91 (.A(\DWACT_ADD_CI_0_g_array_11_2[0] ), .B(
        rom_addr[14]), .Y(I_91));
    NOR2B term_cnt_3 (.A(rom_addr[11]), .B(rom_addr[10]), .Y(
        term_cnt_3_net_1));
    OR2A load_5 (.A(INIT_c), .B(un1_cnt_net_1), .Y(load_5_net_1));
    DFN0 \address[8]  (.D(\address_4[8]_net_1 ), .CLK(SCK_c_1), .Q(
        rom_addr[8]));
    NOR2B un1_address_I_94 (.A(\DWACT_ADD_CI_0_g_array_2[0] ), .B(
        rom_addr[4]), .Y(\DWACT_ADD_CI_0_g_array_12_1[0] ));
    XOR2 un1_address_I_62 (.A(rom_addr[7]), .B(
        \DWACT_ADD_CI_0_g_array_12_2[0] ), .Y(I_62));
    AND2 un1_address_I_120 (.A(rom_addr[16]), .B(rom_addr[17]), .Y(
        \DWACT_ADD_CI_0_pog_array_1_7[0] ));
    DFN0 \address[6]  (.D(\address_4[6]_net_1 ), .CLK(SCK_c_1), .Q(
        rom_addr[6]));
    AND2 un1_address_I_115 (.A(\DWACT_ADD_CI_0_pog_array_1_5[0] ), .B(
        \DWACT_ADD_CI_0_pog_array_1_6[0] ), .Y(
        \DWACT_ADD_CI_0_pog_array_2_2[0] ));
    XOR2 un1_address_I_60 (.A(rom_addr[12]), .B(
        \DWACT_ADD_CI_0_g_array_10[0] ), .Y(I_60));
    XOR2 un1_address_I_41 (.A(rom_addr[0]), .B(un1_cnt_net_1), .Y(
        \DWACT_ADD_CI_0_partial_sum[0] ));
    VCC VCC_i_0 (.Y(VCC_net_1));
    GND GND_i_0 (.Y(GND_net_1));
    
endmodule


module PLL_100_60(
       INIT_c,
       VCC,
       GND,
       CLK100MHz,
       CLK60MHz
    );
input  INIT_c;
input  VCC;
input  GND;
input  CLK100MHz;
output CLK60MHz;

    wire Core_GLB, Core_GLC, Core_LOCK, Core_YB, Core_YC, GND_net_1, 
        VCC_net_1;
    
    VCC VCC_i_0 (.Y(VCC_net_1));
    PLL #( .VCOFREQUENCY(60.000000) )  Core (.CLKA(CLK100MHz), .EXTFB(
        GND), .POWERDOWN(VCC), .GLA(CLK60MHz), .LOCK(Core_LOCK), .GLB(
        Core_GLB), .YB(Core_YB), .GLC(Core_GLC), .YC(Core_YC), .OADIV0(
        GND), .OADIV1(GND), .OADIV2(GND), .OADIV3(GND), .OADIV4(GND), 
        .OADIVHALF(GND), .OADIVRST(INIT_c), .OAMUX0(GND), .OAMUX1(GND), 
        .OAMUX2(VCC), .DLYGLA0(GND), .DLYGLA1(GND), .DLYGLA2(GND), 
        .DLYGLA3(GND), .DLYGLA4(GND), .OBDIV0(GND), .OBDIV1(GND), 
        .OBDIV2(GND), .OBDIV3(GND), .OBDIV4(GND), .OBMUX0(GND), 
        .OBMUX1(GND), .OBMUX2(GND), .DLYYB0(GND), .DLYYB1(GND), 
        .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND), .DLYGLB0(GND), 
        .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND), .DLYGLB4(GND), 
        .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(GND), .OCDIV3(GND), 
        .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(GND), .OCMUX2(GND), 
        .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND), .DLYYC3(GND), 
        .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND), .DLYGLC2(GND), 
        .DLYGLC3(GND), .DLYGLC4(GND), .FINDIV0(VCC), .FINDIV1(VCC), 
        .FINDIV2(GND), .FINDIV3(GND), .FINDIV4(VCC), .FINDIV5(GND), 
        .FINDIV6(GND), .FBDIV0(VCC), .FBDIV1(VCC), .FBDIV2(GND), 
        .FBDIV3(VCC), .FBDIV4(GND), .FBDIV5(GND), .FBDIV6(GND), 
        .FBDLY0(GND), .FBDLY1(GND), .FBDLY2(GND), .FBDLY3(GND), 
        .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1(GND), .XDLYSEL(GND), 
        .VCOSEL0(GND), .VCOSEL1(VCC), .VCOSEL2(GND));
    GND GND_i_0 (.Y(GND_net_1));
    VCC VCC_i (.Y(VCC));
    GND GND_i (.Y(GND));
    
endmodule


module RC_Oscillator(
       CLK100MHz
    );
output CLK100MHz;

    wire VCC, GND, GND_net_1, VCC_net_1;
    
    VCC VCC_i_0 (.Y(VCC_net_1));
    RCOSC RCOSC1 (.CLKOUT(CLK100MHz));
    GND GND_i_0 (.Y(GND_net_1));
    VCC VCC_i (.Y(VCC));
    GND GND_i (.Y(GND));
    
endmodule


module NVM2(
       rom_data_o,
       rom_addr,
       rom_data_2,
       term_cnt,
       VCC,
       CLK60MHz,
       GND
    );
input  [7:0] rom_data_o;
input  [17:0] rom_addr;
output [7:0] rom_data_2;
input  term_cnt;
input  VCC;
input  CLK60MHz;
input  GND;

    wire NVM_INST_BUSY, \NVM_INST_RD[8] , \NVM_INST_RD[9] , 
        \NVM_INST_RD[10] , \NVM_INST_RD[11] , \NVM_INST_RD[12] , 
        \NVM_INST_RD[13] , \NVM_INST_RD[14] , \NVM_INST_RD[15] , 
        \NVM_INST_RD[16] , \NVM_INST_RD[17] , \NVM_INST_RD[18] , 
        \NVM_INST_RD[19] , \NVM_INST_RD[20] , \NVM_INST_RD[21] , 
        \NVM_INST_RD[22] , \NVM_INST_RD[23] , \NVM_INST_RD[24] , 
        \NVM_INST_RD[25] , \NVM_INST_RD[26] , \NVM_INST_RD[27] , 
        \NVM_INST_RD[28] , \NVM_INST_RD[29] , \NVM_INST_RD[30] , 
        \NVM_INST_RD[31] , \NVM_INST_STATUS[0] , \NVM_INST_STATUS[1] , 
        GND_net_1, VCC_net_1;
    
    VCC VCC_i_0 (.Y(VCC_net_1));
    GND GND_i_0 (.Y(GND_net_1));
    NVM #( .MEMORYFILE("NVM2.mem") )  NVM_INST (.RD({\NVM_INST_RD[31] , 
        \NVM_INST_RD[30] , \NVM_INST_RD[29] , \NVM_INST_RD[28] , 
        \NVM_INST_RD[27] , \NVM_INST_RD[26] , \NVM_INST_RD[25] , 
        \NVM_INST_RD[24] , \NVM_INST_RD[23] , \NVM_INST_RD[22] , 
        \NVM_INST_RD[21] , \NVM_INST_RD[20] , \NVM_INST_RD[19] , 
        \NVM_INST_RD[18] , \NVM_INST_RD[17] , \NVM_INST_RD[16] , 
        \NVM_INST_RD[15] , \NVM_INST_RD[14] , \NVM_INST_RD[13] , 
        \NVM_INST_RD[12] , \NVM_INST_RD[11] , \NVM_INST_RD[10] , 
        \NVM_INST_RD[9] , \NVM_INST_RD[8] , rom_data_2[7], 
        rom_data_2[6], rom_data_2[5], rom_data_2[4], rom_data_2[3], 
        rom_data_2[2], rom_data_2[1], rom_data_2[0]}), .BUSY(
        NVM_INST_BUSY), .STATUS({\NVM_INST_STATUS[1] , 
        \NVM_INST_STATUS[0] }), .ADDR({rom_addr[17], rom_addr[16], 
        rom_addr[15], rom_addr[14], rom_addr[13], rom_addr[12], 
        rom_addr[11], rom_addr[10], rom_addr[9], rom_addr[8], 
        rom_addr[7], rom_addr[6], rom_addr[5], rom_addr[4], 
        rom_addr[3], rom_addr[2], rom_addr[1], rom_addr[0]}), .WD({GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        rom_data_o[7], rom_data_o[6], rom_data_o[5], rom_data_o[4], 
        rom_data_o[3], rom_data_o[2], rom_data_o[1], rom_data_o[0]}), 
        .DATAWIDTH({GND, GND}), .REN(VCC), .WEN(GND), .PROGRAM(GND), 
        .SPAREPAGE(GND), .AUXBLOCK(GND), .READNEXT(GND), .ERASEPAGE(
        GND), .UNPROTECTPAGE(GND), .DISCARDPAGE(GND), 
        .OVERWRITEPROTECT(GND), .PAGELOSSPROTECT(GND), .CLK(CLK60MHz), 
        .RESET(term_cnt), .PAGESTATUS(GND), .OVERWRITEPAGE(GND), .PIPE(
        GND), .LOCKREQUEST(GND));
    VCC VCC_i (.Y(VCC));
    GND GND_i (.Y(GND));
    
endmodule


module MasterSerial(
       SCK,
       INIT,
       DONE,
       SDO
    );
input  SCK;
input  INIT;
input  DONE;
output SDO;

    wire SCK_c_1, SCK_c, SCK_c_0, INIT_c_1, INIT_c, INIT_c_0, 
        SDO_buf_net_1, \u2.d_reg , \rom_data_o[7]_net_1 , 
        \rom_data_1[7] , \rom_data_2[7] , \rom_addr[18] , 
        \rom_data_o[6]_net_1 , \rom_data_1[6] , \rom_data_2[6] , 
        \rom_data_o[5]_net_1 , \rom_data_1[5] , \rom_data_2[5] , 
        \rom_data_o[4]_net_1 , \rom_data_1[4] , \rom_data_2[4] , 
        \rom_data_o[3]_net_1 , \rom_data_1[3] , \rom_data_2[3] , 
        \rom_data_o[2]_net_1 , \rom_data_1[2] , \rom_data_2[2] , 
        \rom_data_o[1]_net_1 , \rom_data_1[1] , \rom_data_2[1] , 
        \rom_data_o[0]_net_1 , \rom_data_1[0] , \rom_data_2[0] , 
        SDO6_net_1, term_cnt, DONE_c, \rom_addr[0] , \rom_addr[1] , 
        \rom_addr[2] , \rom_addr[3] , \rom_addr[4] , \rom_addr[5] , 
        \rom_addr[6] , \rom_addr[7] , \rom_addr[8] , \rom_addr[9] , 
        \rom_addr[10] , \rom_addr[11] , \rom_addr[12] , \rom_addr[13] , 
        \rom_addr[14] , \rom_addr[15] , \rom_addr[16] , \rom_addr[17] , 
        load, CLK100MHz, VCC, GND, CLK60MHz, GND_net_1, VCC_net_1;
    
    ShiftReg u2 (.rom_data_o({\rom_data_o[7]_net_1 , 
        \rom_data_o[6]_net_1 , \rom_data_o[5]_net_1 , 
        \rom_data_o[4]_net_1 , \rom_data_o[3]_net_1 , 
        \rom_data_o[2]_net_1 }), .SCK_c(SCK_c), .d_reg(\u2.d_reg ), 
        .load(load));
    INBUF INIT_pad (.PAD(INIT), .Y(INIT_c));
    NOR2B SDO_buf (.A(\u2.d_reg ), .B(INIT_c_0), .Y(SDO_buf_net_1));
    MX2 \rom_data_o[1]  (.A(\rom_data_1[1] ), .B(\rom_data_2[1] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[1]_net_1 ));
    MX2 \rom_data_o[0]  (.A(\rom_data_1[0] ), .B(\rom_data_2[0] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[0]_net_1 ));
    GND GND_i_0 (.Y(GND_net_1));
    MX2 \rom_data_o[3]  (.A(\rom_data_1[3] ), .B(\rom_data_2[3] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[3]_net_1 ));
    NVM1 mFlashMemory1 (.rom_data_o({\rom_data_o[7]_net_1 , 
        \rom_data_o[6]_net_1 , \rom_data_o[5]_net_1 , 
        \rom_data_o[4]_net_1 , \rom_data_o[3]_net_1 , 
        \rom_data_o[2]_net_1 , \rom_data_o[1]_net_1 , 
        \rom_data_o[0]_net_1 }), .rom_addr({\rom_addr[17] , 
        \rom_addr[16] , \rom_addr[15] , \rom_addr[14] , \rom_addr[13] , 
        \rom_addr[12] , \rom_addr[11] , \rom_addr[10] , \rom_addr[9] , 
        \rom_addr[8] , \rom_addr[7] , \rom_addr[6] , \rom_addr[5] , 
        \rom_addr[4] , \rom_addr[3] , \rom_addr[2] , \rom_addr[1] , 
        \rom_addr[0] }), .rom_data_1({\rom_data_1[7] , \rom_data_1[6] , 
        \rom_data_1[5] , \rom_data_1[4] , \rom_data_1[3] , 
        \rom_data_1[2] , \rom_data_1[1] , \rom_data_1[0] }), .term_cnt(
        term_cnt), .VCC(VCC), .CLK60MHz(CLK60MHz), .GND(GND));
    TRIBUFF SDO_pad (.D(SDO_buf_net_1), .E(SDO6_net_1), .PAD(SDO));
    VCC VCC_i (.Y(VCC));
    counter u1 (.rom_addr({\rom_addr[18] , \rom_addr[17] , 
        \rom_addr[16] , \rom_addr[15] , \rom_addr[14] , \rom_addr[13] , 
        \rom_addr[12] , \rom_addr[11] , \rom_addr[10] , \rom_addr[9] , 
        \rom_addr[8] , \rom_addr[7] , \rom_addr[6] , \rom_addr[5] , 
        \rom_addr[4] , \rom_addr[3] , \rom_addr[2] , \rom_addr[1] , 
        \rom_addr[0] }), .SCK_c(SCK_c), .SCK_c_1(SCK_c_1), .SCK_c_0(
        SCK_c_0), .load(load), .INIT_c(INIT_c), .INIT_c_1(INIT_c_1), 
        .term_cnt(term_cnt), .INIT_c_0(INIT_c_0));
    INBUF SCK_pad (.PAD(SCK), .Y(SCK_c));
    PLL_100_60 myPLL (.INIT_c(INIT_c), .VCC(VCC), .GND(GND), 
        .CLK100MHz(CLK100MHz), .CLK60MHz(CLK60MHz));
    BUFF SCK_pad_0 (.A(SCK_c), .Y(SCK_c_0));
    BUFF SCK_pad_1 (.A(SCK_c), .Y(SCK_c_1));
    RC_Oscillator RC (.CLK100MHz(CLK100MHz));
    NVM2 mFlashMemory2 (.rom_data_o({\rom_data_o[7]_net_1 , 
        \rom_data_o[6]_net_1 , \rom_data_o[5]_net_1 , 
        \rom_data_o[4]_net_1 , \rom_data_o[3]_net_1 , 
        \rom_data_o[2]_net_1 , \rom_data_o[1]_net_1 , 
        \rom_data_o[0]_net_1 }), .rom_addr({\rom_addr[17] , 
        \rom_addr[16] , \rom_addr[15] , \rom_addr[14] , \rom_addr[13] , 
        \rom_addr[12] , \rom_addr[11] , \rom_addr[10] , \rom_addr[9] , 
        \rom_addr[8] , \rom_addr[7] , \rom_addr[6] , \rom_addr[5] , 
        \rom_addr[4] , \rom_addr[3] , \rom_addr[2] , \rom_addr[1] , 
        \rom_addr[0] }), .rom_data_2({\rom_data_2[7] , \rom_data_2[6] , 
        \rom_data_2[5] , \rom_data_2[4] , \rom_data_2[3] , 
        \rom_data_2[2] , \rom_data_2[1] , \rom_data_2[0] }), .term_cnt(
        term_cnt), .VCC(VCC), .CLK60MHz(CLK60MHz), .GND(GND));
    GND GND_i (.Y(GND));
    VCC VCC_i_0 (.Y(VCC_net_1));
    MX2 \rom_data_o[7]  (.A(\rom_data_1[7] ), .B(\rom_data_2[7] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[7]_net_1 ));
    INBUF DONE_pad (.PAD(DONE), .Y(DONE_c));
    MX2 \rom_data_o[5]  (.A(\rom_data_1[5] ), .B(\rom_data_2[5] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[5]_net_1 ));
    MX2 \rom_data_o[4]  (.A(\rom_data_1[4] ), .B(\rom_data_2[4] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[4]_net_1 ));
    BUFF INIT_pad_0 (.A(INIT_c), .Y(INIT_c_0));
    NOR2A SDO6 (.A(term_cnt), .B(DONE_c), .Y(SDO6_net_1));
    MX2 \rom_data_o[2]  (.A(\rom_data_1[2] ), .B(\rom_data_2[2] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[2]_net_1 ));
    BUFF INIT_pad_1 (.A(INIT_c), .Y(INIT_c_1));
    MX2 \rom_data_o[6]  (.A(\rom_data_1[6] ), .B(\rom_data_2[6] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[6]_net_1 ));
    
endmodule
