`timescale 1 ns/100 ps
// Version: 7.3 SP1 7.3.1.9
// File used only for Simulation


module MasterSerial(
       SCK,
       INIT,
       DONE,
       SDO
    );
input  SCK;
input  INIT;
input  DONE;
output SDO;

    wire SCK_c_1, SCK_c, SCK_c_0, INIT_c_1, INIT_c, INIT_c_0, 
        SDO_buf_net_1, \u2.d_reg , \rom_data_o[7]_net_1 , 
        \rom_data_1[7] , \rom_data_2[7] , \rom_addr[18] , 
        \rom_data_o[6]_net_1 , \rom_data_1[6] , \rom_data_2[6] , 
        \rom_data_o[5]_net_1 , \rom_data_1[5] , \rom_data_2[5] , 
        \rom_data_o[4]_net_1 , \rom_data_1[4] , \rom_data_2[4] , 
        \rom_data_o[3]_net_1 , \rom_data_1[3] , \rom_data_2[3] , 
        \rom_data_o[2]_net_1 , \rom_data_1[2] , \rom_data_2[2] , 
        \rom_data_o[1]_net_1 , \rom_data_1[1] , \rom_data_2[1] , 
        \rom_data_o[0]_net_1 , \rom_data_1[0] , \rom_data_2[0] , 
        SDO6_net_1, term_cnt, DONE_c, \rom_addr[0] , \rom_addr[1] , 
        \rom_addr[2] , \rom_addr[3] , \rom_addr[4] , \rom_addr[5] , 
        \rom_addr[6] , \rom_addr[7] , \rom_addr[8] , \rom_addr[9] , 
        \rom_addr[10] , \rom_addr[11] , \rom_addr[12] , \rom_addr[13] , 
        \rom_addr[14] , \rom_addr[15] , \rom_addr[16] , \rom_addr[17] , 
        load, CLK100MHz, VCC, CLK60MHz, \u2/d_latch_10[6]_net_1 , 
        \u2/d_latch[5]_net_1 , \u2/d_latch_10[5]_net_1 , 
        \u2/d_latch[4]_net_1 , \u2/d_latch_10[4]_net_1 , 
        \u2/d_latch[3]_net_1 , \u2/d_latch_10[3]_net_1 , 
        \u2/d_latch[2]_net_1 , \u2/d_reg_4_net_1 , 
        \u2/d_latch[6]_net_1 , \u1/DWACT_ADD_CI_0_g_array_10[0] , 
        \u1/DWACT_ADD_CI_0_g_array_3[0] , 
        \u1/DWACT_ADD_CI_0_pog_array_2_1[0] , 
        \u1/DWACT_ADD_CI_0_g_array_2[0] , 
        \u1/DWACT_ADD_CI_0_pog_array_2[0] , 
        \u1/DWACT_ADD_CI_0_g_array_1[0] , 
        \u1/DWACT_ADD_CI_0_g_array_11_2[0] , 
        \u1/DWACT_ADD_CI_0_pog_array_1_5[0] , 
        \u1/DWACT_ADD_CI_0_TMP[0] , \u1/un1_cnt_net_1 , 
        \u1/cnt[1]_net_1 , \u1/cnt[2]_net_1 , \u1/cnt[0]_net_1 , 
        \u1/address_4[15]_net_1 , \u1/I_78 , 
        \u1/DWACT_ADD_CI_0_g_array_4[0] , 
        \u1/DWACT_ADD_CI_0_pog_array_3[0] , 
        \u1/DWACT_ADD_CI_0_g_array_11_1[0] , 
        \u1/DWACT_ADD_CI_0_pog_array_1_3[0] , 
        \u1/DWACT_ADD_CI_0_g_array_11[0] , 
        \u1/DWACT_ADD_CI_0_pog_array_1_1[0] , 
        \u1/DWACT_ADD_CI_0_g_array_1_0[0] , 
        \u1/DWACT_ADD_CI_0_TMP_0[0] , 
        \u1/DWACT_ADD_CI_0_pog_array_1_7[0] , 
        \u1/DWACT_ADD_CI_0_g_array_12_2[0] , 
        \u1/DWACT_ADD_CI_0_g_array_12_3[0] , 
        \u1/DWACT_ADD_CI_0_g_array_12[0] , 
        \u1/DWACT_ADD_CI_0_g_array_12_7[0] , \u1/term_cnt_16_net_1 , 
        \u1/term_cnt_9_net_1 , \u1/term_cnt_10_net_1 , 
        \u1/term_cnt_13_net_1 , \u1/term_cnt_14_net_1 , 
        \u1/term_cnt_1_net_1 , \u1/term_cnt_2_net_1 , 
        \u1/term_cnt_11_net_1 , \u1/term_cnt_3_net_1 , 
        \u1/term_cnt_5_net_1 , \u1/term_cnt_7_net_1 , 
        \u1/address_4[18]_net_1 , \u1/I_69 , \u1/address_4[17]_net_1 , 
        \u1/address_4[16]_net_1 , \u1/address_4[14]_net_1 , 
        \u1/address_4[13]_net_1 , \u1/I_66 , \u1/address_4[12]_net_1 , 
        \u1/address_4[11]_net_1 , \u1/I_72 , \u1/address_4[10]_net_1 , 
        \u1/address_4[9]_net_1 , \u1/address_4[8]_net_1 , 
        \u1/address_4[7]_net_1 , \u1/address_4[6]_net_1 , 
        \u1/address_4[5]_net_1 , \u1/I_75 , \u1/address_4[4]_net_1 , 
        \u1/address_4[3]_net_1 , \u1/address_4[2]_net_1 , 
        \u1/address_4[1]_net_1 , \u1/address_4[0]_net_1 , 
        \u1/cnt_4[2]_net_1 , \u1/cnt_4[1]_net_1 , \u1/cnt_4[0]_net_1 , 
        \u1/load_5_net_1 , \u1/DWACT_ADD_CI_0_pog_array_1_6[0] , 
        \SCK_pad/U0/NET1 , \INIT_pad/U0/NET1 , \SDO_pad/U0/NET1 , 
        \SDO_pad/U0/NET2 , \DONE_pad/U0/NET1 , GND, AFLSDF_VCC, 
        AFLSDF_GND;
    wire GND_power_net1;
    wire VCC_power_net1;
    assign GND = GND_power_net1;
    assign AFLSDF_GND = GND_power_net1;
    assign VCC = VCC_power_net1;
    assign AFLSDF_VCC = VCC_power_net1;
    
    NOR2B \u1/address_4[13]  (.A(\u1/I_66 ), .B(INIT_c_0), .Y(
        \u1/address_4[13]_net_1 ));
    AX1C \u1/un1_address_I_75  (.A(\u1/DWACT_ADD_CI_0_g_array_2[0] ), 
        .B(\rom_addr[4] ), .C(\rom_addr[5] ), .Y(\u1/I_75 ));
    NOR2B \u1/un1_address_I_103  (.A(\u1/DWACT_ADD_CI_0_g_array_3[0] ), 
        .B(\u1/DWACT_ADD_CI_0_pog_array_3[0] ), .Y(
        \u1/DWACT_ADD_CI_0_g_array_4[0] ));
    DFN0 \u1/address[6]  (.D(\u1/address_4[6]_net_1 ), .CLK(SCK_c_1), 
        .Q(\rom_addr[6] ));
    NOR2B \u1/term_cnt_2  (.A(\rom_addr[13] ), .B(\rom_addr[12] ), .Y(
        \u1/term_cnt_2_net_1 ));
    MX2 \rom_data_o[0]  (.A(\rom_data_1[0] ), .B(\rom_data_2[0] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[0]_net_1 ));
    AX1C \u1/un1_address_I_66  (.A(\u1/DWACT_ADD_CI_0_g_array_10[0] ), 
        .B(\rom_addr[12] ), .C(\rom_addr[13] ), .Y(\u1/I_66 ));
    MX2 \u2/d_latch_10[5]  (.A(\u2/d_latch[4]_net_1 ), .B(
        \rom_data_o[5]_net_1 ), .S(load), .Y(\u2/d_latch_10[5]_net_1 ));
    NOR3C \u1/term_cnt_14  (.A(\u1/term_cnt_1_net_1 ), .B(
        \u1/term_cnt_2_net_1 ), .C(\u1/term_cnt_11_net_1 ), .Y(
        \u1/term_cnt_14_net_1 ));
    DFN1 \u1/cnt[1]  (.D(\u1/cnt_4[1]_net_1 ), .CLK(SCK_c_0), .Q(
        \u1/cnt[1]_net_1 ));
    MX2 \rom_data_o[3]  (.A(\rom_data_1[3] ), .B(\rom_data_2[3] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[3]_net_1 ));
    XA1 \u1/address_4[0]  (.A(\rom_addr[0] ), .B(\u1/un1_cnt_net_1 ), 
        .C(INIT_c), .Y(\u1/address_4[0]_net_1 ));
    MX2 \u2/d_latch_10[4]  (.A(\u2/d_latch[3]_net_1 ), .B(
        \rom_data_o[4]_net_1 ), .S(load), .Y(\u2/d_latch_10[4]_net_1 ));
    NOR2B \u1/term_cnt_7  (.A(\rom_addr[3] ), .B(\rom_addr[2] ), .Y(
        \u1/term_cnt_7_net_1 ));
    OR2A \u1/load_5  (.A(INIT_c), .B(\u1/un1_cnt_net_1 ), .Y(
        \u1/load_5_net_1 ));
    NVM #( .MEMORYFILE("NVM1.mem") )  \mFlashMemory1/NVM_INST  (.RD({
        nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9, nc10, nc11, 
        nc12, nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20, nc21, 
        nc22, nc23, \rom_data_1[7] , \rom_data_1[6] , \rom_data_1[5] , 
        \rom_data_1[4] , \rom_data_1[3] , \rom_data_1[2] , 
        \rom_data_1[1] , \rom_data_1[0] }), .BUSY(), .STATUS({nc24, 
        nc25}), .ADDR({\rom_addr[17] , \rom_addr[16] , \rom_addr[15] , 
        \rom_addr[14] , \rom_addr[13] , \rom_addr[12] , \rom_addr[11] , 
        \rom_addr[10] , \rom_addr[9] , \rom_addr[8] , \rom_addr[7] , 
        \rom_addr[6] , \rom_addr[5] , \rom_addr[4] , \rom_addr[3] , 
        \rom_addr[2] , \rom_addr[1] , \rom_addr[0] }), .WD({GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        \rom_data_o[7]_net_1 , \rom_data_o[6]_net_1 , 
        \rom_data_o[5]_net_1 , \rom_data_o[4]_net_1 , 
        \rom_data_o[3]_net_1 , \rom_data_o[2]_net_1 , 
        \rom_data_o[1]_net_1 , \rom_data_o[0]_net_1 }), .DATAWIDTH({
        GND, GND}), .REN(VCC), .WEN(GND), .PROGRAM(GND), .SPAREPAGE(
        GND), .AUXBLOCK(GND), .READNEXT(GND), .ERASEPAGE(GND), 
        .UNPROTECTPAGE(GND), .DISCARDPAGE(GND), .OVERWRITEPROTECT(GND), 
        .PAGELOSSPROTECT(GND), .CLK(CLK60MHz), .RESET(term_cnt), 
        .PAGESTATUS(GND), .OVERWRITEPAGE(GND), .PIPE(GND), 
        .LOCKREQUEST(GND));
    XA1 \u1/cnt_4[0]  (.A(\u1/cnt[0]_net_1 ), .B(term_cnt), .C(INIT_c), 
        .Y(\u1/cnt_4[0]_net_1 ));
    IOIN_IB \SCK_pad/U0/U1  (.YIN(\SCK_pad/U0/NET1 ), .Y(SCK_c));
    AND2 \u1/un1_address_I_119  (.A(\rom_addr[14] ), .B(\rom_addr[15] )
        , .Y(\u1/DWACT_ADD_CI_0_pog_array_1_6[0] ));
    NOR3C \u1/un1_address_I_114  (.A(\rom_addr[10] ), .B(
        \rom_addr[11] ), .C(\u1/DWACT_ADD_CI_0_pog_array_1_3[0] ), .Y(
        \u1/DWACT_ADD_CI_0_pog_array_2_1[0] ));
    NOR2B \u1/un1_address_I_108  (.A(\u1/DWACT_ADD_CI_0_g_array_10[0] )
        , .B(\u1/DWACT_ADD_CI_0_pog_array_1_5[0] ), .Y(
        \u1/DWACT_ADD_CI_0_g_array_11_2[0] ));
    DFN0 \u1/address[11]  (.D(\u1/address_4[11]_net_1 ), .CLK(SCK_c_1), 
        .Q(\rom_addr[11] ));
    DFN0 \u1/address[12]  (.D(\u1/address_4[12]_net_1 ), .CLK(SCK_c_1), 
        .Q(\rom_addr[12] ));
    MX2 \rom_data_o[7]  (.A(\rom_data_1[7] ), .B(\rom_data_2[7] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[7]_net_1 ));
    MX2 \u2/d_reg_4  (.A(\u2/d_latch[6]_net_1 ), .B(
        \rom_data_o[7]_net_1 ), .S(load), .Y(\u2/d_reg_4_net_1 ));
    AX1C \u1/un1_address_I_72  (.A(\u1/DWACT_ADD_CI_0_g_array_11_1[0] )
        , .B(\rom_addr[10] ), .C(\rom_addr[11] ), .Y(\u1/I_72 ));
    AX1C \u1/un1_address_I_69  (.A(\u1/DWACT_ADD_CI_0_g_array_4[0] ), 
        .B(\u1/DWACT_ADD_CI_0_pog_array_1_7[0] ), .C(\rom_addr[18] ), 
        .Y(\u1/I_69 ));
    NOR2B \u1/un1_address_I_98  (.A(\u1/DWACT_ADD_CI_0_g_array_3[0] ), 
        .B(\rom_addr[8] ), .Y(\u1/DWACT_ADD_CI_0_g_array_12_3[0] ));
    XA1 \u1/cnt_4[1]  (.A(\u1/cnt[1]_net_1 ), .B(
        \u1/DWACT_ADD_CI_0_TMP_0[0] ), .C(INIT_c), .Y(
        \u1/cnt_4[1]_net_1 ));
    DFN0 \u1/address[18]  (.D(\u1/address_4[18]_net_1 ), .CLK(SCK_c), 
        .Q(\rom_addr[18] ));
    NOR3C \u1/term_cnt_11  (.A(\rom_addr[8] ), .B(\rom_addr[9] ), .C(
        \u1/term_cnt_3_net_1 ), .Y(\u1/term_cnt_11_net_1 ));
    AND2 \u1/un1_address_I_117  (.A(\rom_addr[12] ), .B(\rom_addr[13] )
        , .Y(\u1/DWACT_ADD_CI_0_pog_array_1_5[0] ));
    XA1 \u1/cnt_4[2]  (.A(\u1/cnt[2]_net_1 ), .B(
        \u1/DWACT_ADD_CI_0_g_array_1_0[0] ), .C(INIT_c), .Y(
        \u1/cnt_4[2]_net_1 ));
    BUFF SCK_pad_0 (.A(SCK_c), .Y(SCK_c_0));
    MX2 \rom_data_o[5]  (.A(\rom_data_1[5] ), .B(\rom_data_2[5] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[5]_net_1 ));
    RCOSC \RC/RCOSC1  (.CLKOUT(CLK100MHz));
    MX2 \rom_data_o[2]  (.A(\rom_data_1[2] ), .B(\rom_data_2[2] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[2]_net_1 ));
    NOR3C \u1/un1_cnt  (.A(\u1/cnt[1]_net_1 ), .B(\u1/cnt[2]_net_1 ), 
        .C(\u1/cnt[0]_net_1 ), .Y(\u1/un1_cnt_net_1 ));
    NOR3C \u1/un1_address_I_100  (.A(\rom_addr[2] ), .B(\rom_addr[3] ), 
        .C(\u1/DWACT_ADD_CI_0_g_array_1[0] ), .Y(
        \u1/DWACT_ADD_CI_0_g_array_2[0] ));
    NOR2B \u1/un1_address_I_105  (.A(\u1/DWACT_ADD_CI_0_g_array_1[0] ), 
        .B(\rom_addr[2] ), .Y(\u1/DWACT_ADD_CI_0_g_array_12[0] ));
    DFN0 \u2/d_latch[6]  (.D(\u2/d_latch_10[6]_net_1 ), .CLK(SCK_c), 
        .Q(\u2/d_latch[6]_net_1 ));
    NOR2B \u1/term_cnt_1  (.A(\rom_addr[15] ), .B(\rom_addr[14] ), .Y(
        \u1/term_cnt_1_net_1 ));
    NOR3C \u1/term_cnt_16  (.A(\u1/term_cnt_9_net_1 ), .B(
        \u1/term_cnt_10_net_1 ), .C(\u1/term_cnt_13_net_1 ), .Y(
        \u1/term_cnt_16_net_1 ));
    DFN0 \u1/address[5]  (.D(\u1/address_4[5]_net_1 ), .CLK(SCK_c_0), 
        .Q(\rom_addr[5] ));
    BUFF SCK_pad_1 (.A(SCK_c), .Y(SCK_c_1));
    DFN0 \u2/d_reg  (.D(\u2/d_reg_4_net_1 ), .CLK(SCK_c), .Q(
        \u2.d_reg ));
    XA1 \u1/address_4[14]  (.A(\rom_addr[14] ), .B(
        \u1/DWACT_ADD_CI_0_g_array_11_2[0] ), .C(INIT_c_0), .Y(
        \u1/address_4[14]_net_1 ));
    XA1 \u1/address_4[8]  (.A(\rom_addr[8] ), .B(
        \u1/DWACT_ADD_CI_0_g_array_3[0] ), .C(INIT_c_1), .Y(
        \u1/address_4[8]_net_1 ));
    AND2 \u1/un1_address_I_1  (.A(\rom_addr[0] ), .B(
        \u1/un1_cnt_net_1 ), .Y(\u1/DWACT_ADD_CI_0_TMP[0] ));
    XA1 \u1/address_4[3]  (.A(\rom_addr[3] ), .B(
        \u1/DWACT_ADD_CI_0_g_array_12[0] ), .C(INIT_c_1), .Y(
        \u1/address_4[3]_net_1 ));
    XA1 \u1/address_4[2]  (.A(\rom_addr[2] ), .B(
        \u1/DWACT_ADD_CI_0_g_array_1[0] ), .C(INIT_c_1), .Y(
        \u1/address_4[2]_net_1 ));
    XA1 \u1/address_4[7]  (.A(\rom_addr[7] ), .B(
        \u1/DWACT_ADD_CI_0_g_array_12_2[0] ), .C(INIT_c_1), .Y(
        \u1/address_4[7]_net_1 ));
    DFN0 \u1/address[10]  (.D(\u1/address_4[10]_net_1 ), .CLK(SCK_c_1), 
        .Q(\rom_addr[10] ));
    AX1C \u1/un1_address_I_78  (.A(\u1/DWACT_ADD_CI_0_g_array_11_2[0] )
        , .B(\rom_addr[14] ), .C(\rom_addr[15] ), .Y(\u1/I_78 ));
    DFN0 \u1/address[15]  (.D(\u1/address_4[15]_net_1 ), .CLK(SCK_c_1), 
        .Q(\rom_addr[15] ));
    NOR2B \u1/un1_address_I_82  (.A(\u1/DWACT_ADD_CI_0_g_array_3[0] ), 
        .B(\u1/DWACT_ADD_CI_0_pog_array_2_1[0] ), .Y(
        \u1/DWACT_ADD_CI_0_g_array_10[0] ));
    NOR2B \u1/un1_address_I_97  (.A(\u1/DWACT_ADD_CI_0_g_array_11[0] ), 
        .B(\rom_addr[6] ), .Y(\u1/DWACT_ADD_CI_0_g_array_12_2[0] ));
    AND2 \u1/un1_address_I_116  (.A(\rom_addr[8] ), .B(\rom_addr[9] ), 
        .Y(\u1/DWACT_ADD_CI_0_pog_array_1_3[0] ));
    XA1 \u1/address_4[6]  (.A(\rom_addr[6] ), .B(
        \u1/DWACT_ADD_CI_0_g_array_11[0] ), .C(INIT_c_1), .Y(
        \u1/address_4[6]_net_1 ));
    NOR2B \u1/address_4[15]  (.A(\u1/I_78 ), .B(INIT_c_0), .Y(
        \u1/address_4[15]_net_1 ));
    DFN0 \u2/d_latch[5]  (.D(\u2/d_latch_10[5]_net_1 ), .CLK(SCK_c), 
        .Q(\u2/d_latch[5]_net_1 ));
    DFN0 \u1/address[2]  (.D(\u1/address_4[2]_net_1 ), .CLK(SCK_c_0), 
        .Q(\rom_addr[2] ));
    DFN0 \u2/d_latch[4]  (.D(\u2/d_latch_10[4]_net_1 ), .CLK(SCK_c), 
        .Q(\u2/d_latch[4]_net_1 ));
    BUFF INIT_pad_0 (.A(INIT_c), .Y(INIT_c_0));
    DFN1 \u1/cnt[2]  (.D(\u1/cnt_4[2]_net_1 ), .CLK(SCK_c_0), .Q(
        \u1/cnt[2]_net_1 ));
    XA1 \u1/address_4[17]  (.A(\rom_addr[17] ), .B(
        \u1/DWACT_ADD_CI_0_g_array_12_7[0] ), .C(INIT_c_0), .Y(
        \u1/address_4[17]_net_1 ));
    AND2 \u1/un1_address_I_111  (.A(\rom_addr[4] ), .B(\rom_addr[5] ), 
        .Y(\u1/DWACT_ADD_CI_0_pog_array_1_1[0] ));
    DFN0 \u1/address[13]  (.D(\u1/address_4[13]_net_1 ), .CLK(SCK_c_1), 
        .Q(\rom_addr[13] ));
    MX2 \u2/d_latch_10[6]  (.A(\u2/d_latch[5]_net_1 ), .B(
        \rom_data_o[6]_net_1 ), .S(load), .Y(\u2/d_latch_10[6]_net_1 ));
    AND2 \u1/un1_address_I_120  (.A(\rom_addr[16] ), .B(\rom_addr[17] )
        , .Y(\u1/DWACT_ADD_CI_0_pog_array_1_7[0] ));
    BUFF INIT_pad_1 (.A(INIT_c), .Y(INIT_c_1));
    IOIN_IB \DONE_pad/U0/U1  (.YIN(\DONE_pad/U0/NET1 ), .Y(DONE_c));
    MX2 \rom_data_o[1]  (.A(\rom_data_1[1] ), .B(\rom_data_2[1] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[1]_net_1 ));
    NOR2B \u1/un1_address_I_79  (.A(\u1/DWACT_ADD_CI_0_TMP[0] ), .B(
        \rom_addr[1] ), .Y(\u1/DWACT_ADD_CI_0_g_array_1[0] ));
    NOR2B \u1/address_4[5]  (.A(\u1/I_75 ), .B(INIT_c_1), .Y(
        \u1/address_4[5]_net_1 ));
    IOTRI_OB_EB \SDO_pad/U0/U1  (.D(SDO_buf_net_1), .E(SDO6_net_1), 
        .DOUT(\SDO_pad/U0/NET1 ), .EOUT(\SDO_pad/U0/NET2 ));
    NOR2B \u1/un1_cnt_1_I_15  (.A(\u1/DWACT_ADD_CI_0_TMP_0[0] ), .B(
        \u1/cnt[1]_net_1 ), .Y(\u1/DWACT_ADD_CI_0_g_array_1_0[0] ));
    DFN0 \u1/address[14]  (.D(\u1/address_4[14]_net_1 ), .CLK(SCK_c_1), 
        .Q(\rom_addr[14] ));
    NOR2B \u1/un1_address_I_107  (.A(\u1/DWACT_ADD_CI_0_g_array_4[0] ), 
        .B(\rom_addr[16] ), .Y(\u1/DWACT_ADD_CI_0_g_array_12_7[0] ));
    NOR2B \u1/address_4[11]  (.A(\u1/I_72 ), .B(INIT_c_0), .Y(
        \u1/address_4[11]_net_1 ));
    DFN0 \u1/address[16]  (.D(\u1/address_4[16]_net_1 ), .CLK(SCK_c), 
        .Q(\rom_addr[16] ));
    IOPAD_TRI \SDO_pad/U0/U0  (.D(\SDO_pad/U0/NET1 ), .E(
        \SDO_pad/U0/NET2 ), .PAD(SDO));
    DFN0 \u1/address[9]  (.D(\u1/address_4[9]_net_1 ), .CLK(SCK_c_1), 
        .Q(\rom_addr[9] ));
    DFN0 \u1/address[4]  (.D(\u1/address_4[4]_net_1 ), .CLK(SCK_c_0), 
        .Q(\rom_addr[4] ));
    XA1 \u1/address_4[1]  (.A(\rom_addr[1] ), .B(
        \u1/DWACT_ADD_CI_0_TMP[0] ), .C(INIT_c), .Y(
        \u1/address_4[1]_net_1 ));
    NOR2B \u1/un1_address_I_86  (.A(\u1/DWACT_ADD_CI_0_g_array_3[0] ), 
        .B(\u1/DWACT_ADD_CI_0_pog_array_1_3[0] ), .Y(
        \u1/DWACT_ADD_CI_0_g_array_11_1[0] ));
    MX2 \rom_data_o[4]  (.A(\rom_data_1[4] ), .B(\rom_data_2[4] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[4]_net_1 ));
    XA1 \u1/address_4[9]  (.A(\rom_addr[9] ), .B(
        \u1/DWACT_ADD_CI_0_g_array_12_3[0] ), .C(INIT_c_1), .Y(
        \u1/address_4[9]_net_1 ));
    MX2 \u2/d_latch_10[3]  (.A(\u2/d_latch[2]_net_1 ), .B(
        \rom_data_o[3]_net_1 ), .S(load), .Y(\u2/d_latch_10[3]_net_1 ));
    DFN0 \u2/d_latch[3]  (.D(\u2/d_latch_10[3]_net_1 ), .CLK(SCK_c), 
        .Q(\u2/d_latch[3]_net_1 ));
    IOPAD_IN \SCK_pad/U0/U0  (.PAD(SCK), .Y(\SCK_pad/U0/NET1 ));
    NOR3C \u1/term_cnt_13  (.A(\rom_addr[16] ), .B(\rom_addr[17] ), .C(
        \rom_addr[18] ), .Y(\u1/term_cnt_13_net_1 ));
    NVM #( .MEMORYFILE("NVM2.mem") )  \mFlashMemory2/NVM_INST  (.RD({
        nc26, nc27, nc28, nc29, nc30, nc31, nc32, nc33, nc34, nc35, 
        nc36, nc37, nc38, nc39, nc40, nc41, nc42, nc43, nc44, nc45, 
        nc46, nc47, nc48, nc49, \rom_data_2[7] , \rom_data_2[6] , 
        \rom_data_2[5] , \rom_data_2[4] , \rom_data_2[3] , 
        \rom_data_2[2] , \rom_data_2[1] , \rom_data_2[0] }), .BUSY(), 
        .STATUS({nc50, nc51}), .ADDR({\rom_addr[17] , \rom_addr[16] , 
        \rom_addr[15] , \rom_addr[14] , \rom_addr[13] , \rom_addr[12] , 
        \rom_addr[11] , \rom_addr[10] , \rom_addr[9] , \rom_addr[8] , 
        \rom_addr[7] , \rom_addr[6] , \rom_addr[5] , \rom_addr[4] , 
        \rom_addr[3] , \rom_addr[2] , \rom_addr[1] , \rom_addr[0] }), 
        .WD({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, \rom_data_o[7]_net_1 , \rom_data_o[6]_net_1 , 
        \rom_data_o[5]_net_1 , \rom_data_o[4]_net_1 , 
        \rom_data_o[3]_net_1 , \rom_data_o[2]_net_1 , 
        \rom_data_o[1]_net_1 , \rom_data_o[0]_net_1 }), .DATAWIDTH({
        GND, GND}), .REN(VCC), .WEN(GND), .PROGRAM(GND), .SPAREPAGE(
        GND), .AUXBLOCK(GND), .READNEXT(GND), .ERASEPAGE(GND), 
        .UNPROTECTPAGE(GND), .DISCARDPAGE(GND), .OVERWRITEPROTECT(GND), 
        .PAGELOSSPROTECT(GND), .CLK(CLK60MHz), .RESET(term_cnt), 
        .PAGESTATUS(GND), .OVERWRITEPAGE(GND), .PIPE(GND), 
        .LOCKREQUEST(GND));
    NOR3C \u1/un1_address_I_113  (.A(\rom_addr[6] ), .B(\rom_addr[7] ), 
        .C(\u1/DWACT_ADD_CI_0_pog_array_1_1[0] ), .Y(
        \u1/DWACT_ADD_CI_0_pog_array_2[0] ));
    NOR2B \u1/term_cnt_3  (.A(\rom_addr[11] ), .B(\rom_addr[10] ), .Y(
        \u1/term_cnt_3_net_1 ));
    DFN0 \u1/address[3]  (.D(\u1/address_4[3]_net_1 ), .CLK(SCK_c_0), 
        .Q(\rom_addr[3] ));
    MX2 \rom_data_o[6]  (.A(\rom_data_1[6] ), .B(\rom_data_2[6] ), .S(
        \rom_addr[18] ), .Y(\rom_data_o[6]_net_1 ));
    DFN0 \u1/address[7]  (.D(\u1/address_4[7]_net_1 ), .CLK(SCK_c_1), 
        .Q(\rom_addr[7] ));
    DFN1 \u1/cnt[0]  (.D(\u1/cnt_4[0]_net_1 ), .CLK(SCK_c_0), .Q(
        \u1/cnt[0]_net_1 ));
    NOR3C \u1/term_cnt_9  (.A(\rom_addr[0] ), .B(\rom_addr[1] ), .C(
        \u1/term_cnt_7_net_1 ), .Y(\u1/term_cnt_9_net_1 ));
    NOR2B \u1/term_cnt_5  (.A(\rom_addr[7] ), .B(\rom_addr[6] ), .Y(
        \u1/term_cnt_5_net_1 ));
    NOR2B \u1/un1_address_I_106  (.A(\u1/DWACT_ADD_CI_0_g_array_2[0] ), 
        .B(\u1/DWACT_ADD_CI_0_pog_array_1_1[0] ), .Y(
        \u1/DWACT_ADD_CI_0_g_array_11[0] ));
    IOIN_IB \INIT_pad/U0/U1  (.YIN(\INIT_pad/U0/NET1 ), .Y(INIT_c));
    XA1 \u1/address_4[12]  (.A(\rom_addr[12] ), .B(
        \u1/DWACT_ADD_CI_0_g_array_10[0] ), .C(INIT_c_0), .Y(
        \u1/address_4[12]_net_1 ));
    NOR2A SDO6 (.A(term_cnt), .B(DONE_c), .Y(SDO6_net_1));
    DFN0 \u1/address[1]  (.D(\u1/address_4[1]_net_1 ), .CLK(SCK_c_0), 
        .Q(\rom_addr[1] ));
    XA1 \u1/address_4[4]  (.A(\rom_addr[4] ), .B(
        \u1/DWACT_ADD_CI_0_g_array_2[0] ), .C(INIT_c_1), .Y(
        \u1/address_4[4]_net_1 ));
    DFN0 \u1/load  (.D(\u1/load_5_net_1 ), .CLK(SCK_c_0), .Q(load));
    NOR2B SDO_buf (.A(\u2.d_reg ), .B(INIT_c_0), .Y(SDO_buf_net_1));
    DFN0 \u1/address[8]  (.D(\u1/address_4[8]_net_1 ), .CLK(SCK_c_1), 
        .Q(\rom_addr[8] ));
    DFN0E1 \u2/d_latch[2]  (.D(\rom_data_o[2]_net_1 ), .CLK(SCK_c), .E(
        load), .Q(\u2/d_latch[2]_net_1 ));
    XA1 \u1/address_4[16]  (.A(\rom_addr[16] ), .B(
        \u1/DWACT_ADD_CI_0_g_array_4[0] ), .C(INIT_c_0), .Y(
        \u1/address_4[16]_net_1 ));
    IOPAD_IN \INIT_pad/U0/U0  (.PAD(INIT), .Y(\INIT_pad/U0/NET1 ));
    XA1 \u1/address_4[10]  (.A(\rom_addr[10] ), .B(
        \u1/DWACT_ADD_CI_0_g_array_11_1[0] ), .C(INIT_c_1), .Y(
        \u1/address_4[10]_net_1 ));
    PLL #( .VCOFREQUENCY(60.000000) )  \myPLL/Core  (.CLKA(CLK100MHz), 
        .EXTFB(GND), .POWERDOWN(VCC), .GLA(CLK60MHz), .LOCK(), .GLB(), 
        .YB(), .GLC(), .YC(), .OADIV0(GND), .OADIV1(GND), .OADIV2(GND), 
        .OADIV3(GND), .OADIV4(GND), .OADIVHALF(GND), .OADIVRST(INIT_c), 
        .OAMUX0(GND), .OAMUX1(GND), .OAMUX2(VCC), .DLYGLA0(GND), 
        .DLYGLA1(GND), .DLYGLA2(GND), .DLYGLA3(GND), .DLYGLA4(GND), 
        .OBDIV0(AFLSDF_GND), .OBDIV1(AFLSDF_GND), .OBDIV2(AFLSDF_GND), 
        .OBDIV3(AFLSDF_GND), .OBDIV4(AFLSDF_GND), .OBMUX0(AFLSDF_GND), 
        .OBMUX1(AFLSDF_GND), .OBMUX2(AFLSDF_GND), .DLYYB0(AFLSDF_GND), 
        .DLYYB1(AFLSDF_GND), .DLYYB2(AFLSDF_GND), .DLYYB3(AFLSDF_GND), 
        .DLYYB4(AFLSDF_GND), .DLYGLB0(AFLSDF_GND), .DLYGLB1(AFLSDF_GND)
        , .DLYGLB2(AFLSDF_GND), .DLYGLB3(AFLSDF_GND), .DLYGLB4(
        AFLSDF_GND), .OCDIV0(AFLSDF_GND), .OCDIV1(AFLSDF_GND), .OCDIV2(
        AFLSDF_GND), .OCDIV3(AFLSDF_GND), .OCDIV4(AFLSDF_GND), .OCMUX0(
        AFLSDF_GND), .OCMUX1(AFLSDF_GND), .OCMUX2(AFLSDF_GND), .DLYYC0(
        AFLSDF_GND), .DLYYC1(AFLSDF_GND), .DLYYC2(AFLSDF_GND), .DLYYC3(
        AFLSDF_GND), .DLYYC4(AFLSDF_GND), .DLYGLC0(AFLSDF_GND), 
        .DLYGLC1(AFLSDF_GND), .DLYGLC2(AFLSDF_GND), .DLYGLC3(
        AFLSDF_GND), .DLYGLC4(AFLSDF_GND), .FINDIV0(VCC), .FINDIV1(VCC)
        , .FINDIV2(GND), .FINDIV3(GND), .FINDIV4(VCC), .FINDIV5(GND), 
        .FINDIV6(GND), .FBDIV0(VCC), .FBDIV1(VCC), .FBDIV2(GND), 
        .FBDIV3(VCC), .FBDIV4(GND), .FBDIV5(GND), .FBDIV6(GND), 
        .FBDLY0(GND), .FBDLY1(GND), .FBDLY2(GND), .FBDLY3(GND), 
        .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1(GND), .XDLYSEL(GND), 
        .VCOSEL0(GND), .VCOSEL1(VCC), .VCOSEL2(GND));
    DFN0 \u1/address[17]  (.D(\u1/address_4[17]_net_1 ), .CLK(SCK_c), 
        .Q(\rom_addr[17] ));
    NOR3C \u1/term_cnt_10  (.A(\rom_addr[4] ), .B(\rom_addr[5] ), .C(
        \u1/term_cnt_5_net_1 ), .Y(\u1/term_cnt_10_net_1 ));
    NOR2B \u1/un1_address_I_87  (.A(\u1/DWACT_ADD_CI_0_g_array_2[0] ), 
        .B(\u1/DWACT_ADD_CI_0_pog_array_2[0] ), .Y(
        \u1/DWACT_ADD_CI_0_g_array_3[0] ));
    OR2B \u1/term_cnt  (.A(\u1/term_cnt_16_net_1 ), .B(
        \u1/term_cnt_14_net_1 ), .Y(term_cnt));
    DFN0 \u1/address[0]  (.D(\u1/address_4[0]_net_1 ), .CLK(SCK_c_0), 
        .Q(\rom_addr[0] ));
    NOR2B \u1/address_4[18]  (.A(\u1/I_69 ), .B(INIT_c_0), .Y(
        \u1/address_4[18]_net_1 ));
    NOR3C \u1/un1_address_I_110  (.A(
        \u1/DWACT_ADD_CI_0_pog_array_1_5[0] ), .B(
        \u1/DWACT_ADD_CI_0_pog_array_1_6[0] ), .C(
        \u1/DWACT_ADD_CI_0_pog_array_2_1[0] ), .Y(
        \u1/DWACT_ADD_CI_0_pog_array_3[0] ));
    AND2 \u1/un1_cnt_1_I_1  (.A(\u1/cnt[0]_net_1 ), .B(term_cnt), .Y(
        \u1/DWACT_ADD_CI_0_TMP_0[0] ));
    IOPAD_IN \DONE_pad/U0/U0  (.PAD(DONE), .Y(\DONE_pad/U0/NET1 ));
    GND GND_power_inst1 (.Y(GND_power_net1));
    VCC VCC_power_inst1 (.Y(VCC_power_net1));
    
endmodule
