`timescale 1 ns/100 ps
// Version: 7.2 SP2 7.2.3.2


module RC_Oscillator(CLKOUT);
output CLKOUT;

    
    RCOSC RCOSC1(.CLKOUT(CLKOUT));
    
endmodule

// _Disclaimer: Please leave the following comments in the file, they are for internal purposes only._


// _GEN_File_Contents_

// Version:7.2.3.2
// ACTGENU_CALL:1
// BATCH:T
// FAM:Fusion
// OUTFORMAT:Verilog
// LPMTYPE:LPM_CCC_RCOSC
// LPM_HINT:NONE
// INSERT_PAD:NO
// INSERT_IOREG:NO
// GEN_BHV_VHDL_VAL:F
// GEN_BHV_VERILOG_VAL:F
// MGNTIMER:F
// MGNCMPL:F
// "DESDIR:D:/Actelprj/SPIFlashMemory/smartgen\RC_Oscillator"
// GEN_BEHV_MODULE:T
// SMARTGEN_DIE:IR6X6M2
// SMARTGEN_PACKAGE:fg256
// DRIVE_MODE:1

// _End_Comments_

