library verilog;
use verilog.vl_types.all;
entity PLL_100_60 is
    port(
        POWERDOWN       : in     vl_logic;
        CLKA            : in     vl_logic;
        LOCK            : out    vl_logic;
        GLA             : out    vl_logic;
        OADIVRST        : in     vl_logic
    );
end PLL_100_60;
