library verilog;
use verilog.vl_types.all;
entity vsprom is
    port(
        clk_in          : in     vl_logic;
        init            : in     vl_logic;
        ldc_done        : in     vl_logic;
        d_out           : out    vl_logic;
        reset_n         : in     vl_logic
    );
end vsprom;
