`timescale 1 ns/100 ps
// Version: 7.3 SP1 7.3.1.9


module NVM2(
       USER_CLK,
       USER_RESET,
       USER_ADD,
       USER_AUX_BLOCK,
       USER_DATA,
       USER_DISCARD_PAGE,
       USER_ERASE_PAGE,
       USER_OVERWRITE_PAGE,
       USER_OVERWRITE_PROT,
       USER_PAGELOSS_PROT,
       USER_PROGRAM,
       USER_READ,
       USER_READ_NEXT,
       USER_LOCK,
       USER_SPARE_PAGE,
       USER_UNPROT_PAGE,
       USER_WIDTH,
       USER_WRITE,
       USER_DOUT,
       USER_PAGE_STATUS,
       USER_NVM_STATUS,
       USER_NVM_BUSY
    );
input  USER_CLK;
input  USER_RESET;
input  [17:0] USER_ADD;
input  USER_AUX_BLOCK;
input  [31:0] USER_DATA;
input  USER_DISCARD_PAGE;
input  USER_ERASE_PAGE;
input  USER_OVERWRITE_PAGE;
input  USER_OVERWRITE_PROT;
input  USER_PAGELOSS_PROT;
input  USER_PROGRAM;
input  USER_READ;
input  USER_READ_NEXT;
input  USER_LOCK;
input  USER_SPARE_PAGE;
input  USER_UNPROT_PAGE;
input  [1:0] USER_WIDTH;
input  USER_WRITE;
output [31:0] USER_DOUT;
input  USER_PAGE_STATUS;
output [1:0] USER_NVM_STATUS;
output USER_NVM_BUSY;

    wire GND_net, VCC_net;
    wire GND_power_net1;
    wire VCC_power_net1;
    assign GND_net = GND_power_net1;
    assign VCC_net = VCC_power_net1;
    
    NVM #( .MEMORYFILE("NVM2.mem") )  NVM_INST (.RD({USER_DOUT[31], 
        USER_DOUT[30], USER_DOUT[29], USER_DOUT[28], USER_DOUT[27], 
        USER_DOUT[26], USER_DOUT[25], USER_DOUT[24], USER_DOUT[23], 
        USER_DOUT[22], USER_DOUT[21], USER_DOUT[20], USER_DOUT[19], 
        USER_DOUT[18], USER_DOUT[17], USER_DOUT[16], USER_DOUT[15], 
        USER_DOUT[14], USER_DOUT[13], USER_DOUT[12], USER_DOUT[11], 
        USER_DOUT[10], USER_DOUT[9], USER_DOUT[8], USER_DOUT[7], 
        USER_DOUT[6], USER_DOUT[5], USER_DOUT[4], USER_DOUT[3], 
        USER_DOUT[2], USER_DOUT[1], USER_DOUT[0]}), .BUSY(
        USER_NVM_BUSY), .STATUS({USER_NVM_STATUS[1], 
        USER_NVM_STATUS[0]}), .ADDR({USER_ADD[17], USER_ADD[16], 
        USER_ADD[15], USER_ADD[14], USER_ADD[13], USER_ADD[12], 
        USER_ADD[11], USER_ADD[10], USER_ADD[9], USER_ADD[8], 
        USER_ADD[7], USER_ADD[6], USER_ADD[5], USER_ADD[4], 
        USER_ADD[3], USER_ADD[2], USER_ADD[1], USER_ADD[0]}), .WD({
        USER_DATA[31], USER_DATA[30], USER_DATA[29], USER_DATA[28], 
        USER_DATA[27], USER_DATA[26], USER_DATA[25], USER_DATA[24], 
        USER_DATA[23], USER_DATA[22], USER_DATA[21], USER_DATA[20], 
        USER_DATA[19], USER_DATA[18], USER_DATA[17], USER_DATA[16], 
        USER_DATA[15], USER_DATA[14], USER_DATA[13], USER_DATA[12], 
        USER_DATA[11], USER_DATA[10], USER_DATA[9], USER_DATA[8], 
        USER_DATA[7], USER_DATA[6], USER_DATA[5], USER_DATA[4], 
        USER_DATA[3], USER_DATA[2], USER_DATA[1], USER_DATA[0]}), 
        .DATAWIDTH({USER_WIDTH[1], USER_WIDTH[0]}), .REN(USER_READ), 
        .WEN(USER_WRITE), .PROGRAM(USER_PROGRAM), .SPAREPAGE(
        USER_SPARE_PAGE), .AUXBLOCK(USER_AUX_BLOCK), .READNEXT(
        USER_READ_NEXT), .ERASEPAGE(USER_ERASE_PAGE), .UNPROTECTPAGE(
        USER_UNPROT_PAGE), .DISCARDPAGE(USER_DISCARD_PAGE), 
        .OVERWRITEPROTECT(USER_OVERWRITE_PROT), .PAGELOSSPROTECT(
        USER_PAGELOSS_PROT), .CLK(USER_CLK), .RESET(USER_RESET), 
        .PAGESTATUS(USER_PAGE_STATUS), .OVERWRITEPAGE(
        USER_OVERWRITE_PAGE), .PIPE(GND_net), .LOCKREQUEST(USER_LOCK));
    GND GND_power_inst1 (.Y(GND_power_net1));
    VCC VCC_power_inst1 (.Y(VCC_power_net1));
    
endmodule

// _Disclaimer: Please leave the following comments in the file, they are for internal purposes only._

// _CFG_File_Contents_

// nvm_set_engine \
//    -toplevel "NVM2" \
//    -HDL Verilog \
//    -die AFS600 \
//    -package "256 FBGA" \
//    -workdir {.} \
//    -commondir {./common} \
//    -verbosity 0
// nvm_set_system \
//    -pipe 0
// nvm_set_data_storage_client \
//    -client_name "NVM2" \
//    -base_address 0 \
//    -number_of_words 262144 \
//    -word_size 8 \
//    -memory_file_format "INTELHEX" \
//    -memory_file {D:\ProgrammingSRAM\hextools\TEST_TWO.HEX} \
//    -jtag_read 0\
//    -jtag_write 0\
//    -lock_address 1

// _GEN_File_Contents_

// DESIGN:NVM2
// DESDIR:D:/Actelprj/MasterSerial/smartgen\.\NVM2
// FAM:Fusion
// MGNCMPL:F
// MGNTIMER:F
// OUTFORMAT:Verilog
// LPMTYPE:LPM_NVM
// LPMHINT:NONE
// CONFIGFILE:NVM2.cfg

// _End_Comments_

