library verilog;
use verilog.vl_types.all;
entity ShiftReg is
    port(
        d_in            : in     vl_logic_vector(7 downto 0);
        init            : in     vl_logic;
        load            : in     vl_logic;
        clk             : in     vl_logic;
        d_out           : out    vl_logic
    );
end ShiftReg;
