library verilog;
use verilog.vl_types.all;
entity SRAM_Config is
    port(
        USER_CLK        : in     vl_logic;
        USER_RESET      : in     vl_logic;
        USER_ADD        : in     vl_logic_vector(17 downto 0);
        USER_AUX_BLOCK  : in     vl_logic;
        USER_DATA       : in     vl_logic_vector(31 downto 0);
        USER_DISCARD_PAGE: in     vl_logic;
        USER_ERASE_PAGE : in     vl_logic;
        USER_OVERWRITE_PAGE: in     vl_logic;
        USER_OVERWRITE_PROT: in     vl_logic;
        USER_PAGELOSS_PROT: in     vl_logic;
        USER_PROGRAM    : in     vl_logic;
        USER_READ       : in     vl_logic;
        USER_READ_NEXT  : in     vl_logic;
        USER_LOCK       : in     vl_logic;
        USER_SPARE_PAGE : in     vl_logic;
        USER_UNPROT_PAGE: in     vl_logic;
        USER_WIDTH      : in     vl_logic_vector(1 downto 0);
        USER_WRITE      : in     vl_logic;
        USER_DOUT       : out    vl_logic_vector(31 downto 0);
        USER_PAGE_STATUS: in     vl_logic;
        USER_NVM_STATUS : out    vl_logic_vector(1 downto 0);
        USER_NVM_BUSY   : out    vl_logic
    );
end SRAM_Config;
