library verilog;
use verilog.vl_types.all;
entity counter is
    generic(
        term_cnt_int    : integer := 524287
    );
    port(
        clk             : in     vl_logic;
        init            : in     vl_logic;
        load            : out    vl_logic;
        term_cnt        : out    vl_logic;
        Q               : out    vl_logic_vector(18 downto 0)
    );
end counter;
