Version:8.2.2.2
ACTGENU_CALL:1
BATCH:T
FAM:Fusion
OUTFORMAT:Verilog
LPMTYPE:LPM_PLL_STATIC
LPM_HINT:NONE
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:T
"DESDIR:G:/Data/Designs/ClosedLoopTrimDemo/smartgen\pll_main"
GEN_BEHV_MODULE:T
SMARTGEN_DIE:M7IR6X6M2
SMARTGEN_PACKAGE:fg484
FIN:100.000000
CLKASRC:4
FBDLY:1
FBMUX:1
XDLYSEL:0
PRIMFREQ:18.423000
PPHASESHIFT:0
DLYAVAL:1
OAMUX:4
SEC1FREQ:9.216000
UGLB:1
UYB:0
GLBDLYVAL:1
YBDLYVAL:1
S1PHASESHIFT:0
OBMUX:2
SEC2FREQ:36.864000
UGLC:1
UYC:0
GLCDLYVAL:1
YCDLYVAL:1
S2PHASESHIFT:0
OCMUX:2
POWERDOWN_POLARITY:0
LOCK_POLARITY:1
LOCK_CTL:0
