 ** Message System Log
 ** Database: 
 ** Date:   Mon Mar 24 12:32:45 2008


****************
Macro Parameters
****************

Name                            : pll_main
Family                          : Fusion
Output Format                   : VERILOG
Type                            : Static PLL
PowerDown                       : Active Low
Lock                            : Active High
Input Freq(Mhz)                 : 100.000000
CLKA Source                     : RC Oscillator
Feedback Delay Value Index      : 1
Feedback Mux Select             : 1
XDLY Mux Select                 : No
Primary Freq(Mhz)               : 18.423000
Primary PhaseShift              : 0
Primary Delay Value Index       : 1
Primary Mux Select              : 4
Secondary1 Freq(Mhz)            : 9.216000
Use GLB                         : YES
Use YB                          : NO
GLB Delay Value Index           : 1
YB Delay Value Index            : 1
Secondary1 PhaseShift           : 0
Secondary1 Mux Select           : 2
Secondary2 Freq(Mhz)            : 36.864000
Use GLC                         : YES
Use YC                          : NO
GLC Delay Value Index           : 1
YC Delay Value Index            : 1
Secondary2 PhaseShift           : 0
Secondary2 Mux Select           : 2
Lock Control                    : No

Configuration Bits:
FINDIV[6:0]     0111010
FBDIV[6:0]      1010110
OADIV[4:0]      00111
OADIVHALF       0
OBDIV[4:0]      01111
OCDIV[4:0]      00011
OAMUX[2:0]      100
OBMUX[2:0]      010
OCMUX[2:0]      010
FBSEL[1:0]      01
FBDLY[4:0]      00000
XDLYSEL         0
DLYGLA[4:0]     00000
DLYGLB[4:0]     00000
DLYGLC[4:0]     00000
DLYYB[4:0]      00000
DLYYC[4:0]      00000
VCOSEL[2:0]     100


Primary Clock Frequency 18.432
Primary Clock Phase Shift 0.000
Primary Clock Output Delay from CLKA 1.695

Secondary1 Clock Frequency 9.216
Secondary1 Clock Phase Shift 0.000
Secondary1 Clock Global Output Delay from CLKA 2.230

Secondary2 Clock Frequency 36.864
Secondary2 Clock Phase Shift 0.000
Secondary2 Clock Global Output Delay from CLKA 2.230


**************
Compile Report
**************


Netlist Resource Report
=======================

    CORE                     Used:      0  Total:  13968   (0.00%)
    IO (W/ clocks)           Used:      0  Total:    172   (0.00%)
    Differential IO          Used:      0  Total:     86   (0.00%)
    GLOBAL (Chip+Quadrant)   Used:      3  Total:     18   (16.67%)
    PLL                      Used:      1  Total:      2   (50.00%)
    RAM/FIFO                 Used:      0  Total:     24   (0.00%)
    Low Static ICC           Used:      0  Total:      1   (0.00%)
    FlashROM                 Used:      0  Total:      1   (0.00%)
    User JTAG                Used:      0  Total:      1   (0.00%)
    RC oscillator            Used:      0  Total:      1   (0.00%)
    XTL oscillator           Used:      0  Total:      1   (0.00%)
    NVM                      Used:      0  Total:      2   (0.00%)
    AB                       Used:      0  Total:      1   (0.00%)
    AnalogIO                 Used:      0  Total:     46   (0.00%)
    VRPSM                    Used:      0  Total:      1   (0.00%)
    No-Glitch MUX            Used:      0  Total:      2   (0.00%)

Written Verilog netlist to
G:/Data/Designs/ClosedLoopTrimDemo/smartgen\pll_main\pll_main.v.

 ** Log Ended:   Mon Mar 24 12:32:47 2008

