KEY LIBERO "8.2"
KEY CAPTURE "8.2.2.2"
KEY DEFAULT_IMPORT_LOC "C:\data\Designs\ClosedLoopTrimDemo\hdl"
KEY DEFAULT_OPEN_LOC "C:\data\Designs\ClosedLoopTrim81\synthesis"
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "Fusion"
KEY VendorTechnology_Die "M7IR6X6M2"
KEY VendorTechnology_Package "fg484"
KEY ProjectLocation "C:\data\Designs\ClosedLoopTrimDemo"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "ClosedLoopTrimDemo::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST LIBRARIES
COREUARTAPB_LIB
ENDLIST
LIST LIBRARY_COREUARTAPB_LIB
ALIAS=..\coreconsole\common\CoreUARTapb\mti\lib_vlog_obs\COREUARTAPB_LIB
COMPILE_OPTION=COMPILE
ENDLIST
LIST FileManager
VALUE "<project>\coreconsole\common\CORE8051S\bfm\compiler\simSelect.do,do"
STATE="utd"
TIME="1206375276"
SIZE="4678"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\CORE8051S.cxf,actgen_cxf"
STATE="utd"
TIME="1206375312"
SIZE="98310"
PARENT="<project>\coreconsole\ProcessorSystem\ProcessorSystem.cxf"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="62672"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\clkctrl.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="24967"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="10573"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s_globs_fusion.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="1048"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\cpu.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="52258"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\debug.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="6374"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\instrdec.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="70929"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="46571"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\jtag.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="14499"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\jtagfusion.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="12417"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\main8051.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="40039"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="57634"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\oci.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="24970"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\ocia51.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="13357"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\pmu.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="24384"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\RAM256X20.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="4201"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\RAM256X8.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="2684"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\ramsfrctrl.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="52348"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\rstctrl.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="26490"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\trace.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="11327"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\trigger.v,hdl"
STATE="utd"
TIME="1206375312"
SIZE="27426"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\verification\sim\run_8051s_verif.do,do"
STATE="utd"
TIME="1206375276"
SIZE="12129"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\extacs.v,tb_hdl"
STATE="utd"
TIME="1206375312"
SIZE="7820"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\extclock.v,tb_hdl"
STATE="utd"
TIME="1206375312"
SIZE="1335"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\jtagdef.v,tb_hdl"
STATE="utd"
TIME="1206375310"
SIZE="3069"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
IS_INCLUDED="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\oci_sys.v,tb_hdl"
STATE="utd"
TIME="1206375312"
SIZE="7689"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\tb_oci_sys.v,tb_hdl"
STATE="utd"
TIME="1206375312"
SIZE="65532"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\tb_verif.v,tb_hdl"
STATE="utd"
TIME="1206375312"
SIZE="9111"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\user_ram.v,tb_hdl"
STATE="utd"
TIME="1206375312"
SIZE="1866"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\user_rom.v,tb_hdl"
STATE="utd"
TIME="1206375312"
SIZE="5882"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CoreAPB3\CoreAPB3.cxf,actgen_cxf"
STATE="utd"
TIME="1206375314"
SIZE="714"
PARENT="<project>\coreconsole\ProcessorSystem\ProcessorSystem.cxf"
ENDFILE
VALUE "<project>\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v,hdl"
STATE="utd"
TIME="1206375314"
SIZE="17722"
PARENT="<project>\coreconsole\common\CoreAPB3\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CoreAPB3\rtl\verilog\o\MuxPtoB3.v,hdl"
STATE="utd"
TIME="1206375314"
SIZE="8690"
PARENT="<project>\coreconsole\common\CoreAPB3\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CoreGPIO\CoreGPIO.cxf,actgen_cxf"
STATE="utd"
TIME="1206375274"
SIZE="859"
PARENT="<project>\coreconsole\ProcessorSystem\ProcessorSystem.cxf"
ENDFILE
VALUE "<project>\coreconsole\common\CoreGPIO\rtl\verilog\o\CoreGPIO.v,hdl"
STATE="utd"
TIME="1206375274"
SIZE="1836"
PARENT="<project>\coreconsole\common\CoreGPIO\CoreGPIO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CoreUARTapb\coreparameters.v,hdl"
STATE="utd"
TIME="1206375276"
SIZE="280"
PARENT="<project>\coreconsole\common\CoreUARTapb\CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\common\CoreUARTapb\CoreUARTapb.cxf,actgen_cxf"
STATE="utd"
TIME="1206375276"
SIZE="1606"
PARENT="<project>\coreconsole\ProcessorSystem\ProcessorSystem.cxf"
ENDFILE
VALUE "<project>\coreconsole\common\CoreUARTapb\rtl\verilog\o\Clock_gen.v,hdl"
STATE="utd"
TIME="1206375274"
SIZE="1720"
PARENT="<project>\coreconsole\common\CoreUARTapb\CoreUARTapb.cxf"
ENDFILE
VALUE "<project>\coreconsole\common\CoreUARTapb\rtl\verilog\o\CoreUARTapb.v,hdl"
STATE="utd"
TIME="1206375274"
SIZE="4573"
PARENT="<project>\coreconsole\common\CoreUARTapb\CoreUARTapb.cxf"
ENDFILE
VALUE "<project>\coreconsole\common\CoreUARTapb\rtl\verilog\o\fifo_256x8.v,hdl"
STATE="utd"
TIME="1206375274"
SIZE="4315"
PARENT="<project>\coreconsole\common\CoreUARTapb\CoreUARTapb.cxf"
ENDFILE
VALUE "<project>\coreconsole\common\CoreUARTapb\rtl\verilog\o\Rx_async.v,hdl"
STATE="utd"
TIME="1206375274"
SIZE="9505"
PARENT="<project>\coreconsole\common\CoreUARTapb\CoreUARTapb.cxf"
ENDFILE
VALUE "<project>\coreconsole\common\CoreUARTapb\rtl\verilog\o\Rx_sync.v,hdl"
STATE="utd"
TIME="1206375276"
SIZE="7337"
PARENT="<project>\coreconsole\common\CoreUARTapb\CoreUARTapb.cxf"
ENDFILE
VALUE "<project>\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_async.v,hdl"
STATE="utd"
TIME="1206375276"
SIZE="6099"
PARENT="<project>\coreconsole\common\CoreUARTapb\CoreUARTapb.cxf"
ENDFILE
VALUE "<project>\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_sync.v,hdl"
STATE="utd"
TIME="1206375276"
SIZE="6136"
PARENT="<project>\coreconsole\common\CoreUARTapb\CoreUARTapb.cxf"
ENDFILE
VALUE "<project>\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v,hdl"
STATE="utd"
TIME="1206375276"
SIZE="10183"
PARENT="<project>\coreconsole\common\CoreUARTapb\CoreUARTapb.cxf"
ENDFILE
VALUE "<project>\coreconsole\ProcessorSystem\ProcessorSystem.cxf,actgen_cxf"
STATE="utd"
TIME="1206375314"
SIZE="3851"
ENDFILE
VALUE "<project>\coreconsole\ProcessorSystem\ProcessorSystem.v,hdl"
STATE="utd"
TIME="1206375314"
SIZE="8778"
PARENT="<project>\coreconsole\ProcessorSystem\ProcessorSystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\coreconsole\ProcessorSystem\testbench.v,tb_hdl"
STATE="utd"
TIME="1206375314"
SIZE="1142"
PARENT="<project>\coreconsole\ProcessorSystem\ProcessorSystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\designer\impl1\ClosedLoopTrimDemo.adb,adb"
STATE="utd"
TIME="1206715048"
SIZE="4368896"
ENDFILE
VALUE "<project>\designer\impl1\ClosedLoopTrimDemo.pdb,pdb"
STATE="utd"
TIME="1206714844"
SIZE="911360"
ENDFILE
VALUE "<project>\designer\impl1\ClosedLoopTrimDemo_CodeOnly.pdb,pdb"
STATE="utd"
TIME="1206714746"
SIZE="8704"
ENDFILE
VALUE "<project>\designer\impl1\ClosedLoopTrimDemo_fp\ClosedLoopTrimDemo.pro,pro"
STATE="utd"
TIME="1206714774"
SIZE="1641"
ENDFILE
VALUE "<project>\hdl\ClosedLoopTrimDemo.v,hdl"
STATE="utd"
TIME="1206645818"
SIZE="8973"
ENDFILE
VALUE "<project>\hdl\CoreDAC.v,hdl"
STATE="utd"
TIME="1206363476"
SIZE="10499"
ENDFILE
VALUE "<project>\simulation\bfmCompile.log,log"
STATE="utd"
TIME="1206538598"
SIZE="61"
ENDFILE
VALUE "<project>\simulation\bfmCompile.tcl,sim"
STATE="utd"
TIME="1206375316"
SIZE="25427"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
ENDFILE
VALUE "<project>\simulation\CoreGPIO_scriptlet.bfm,sim"
STATE="utd"
TIME="1206375316"
SIZE="567"
PARENT="<project>\coreconsole\common\CoreGPIO\CoreGPIO.cxf"
ENDFILE
VALUE "<project>\simulation\CoreUARTapb_scriptlet.bfm,sim"
STATE="utd"
TIME="1206375316"
SIZE="614"
PARENT="<project>\coreconsole\common\CoreUARTapb\CoreUARTapb.cxf"
ENDFILE
VALUE "<project>\simulation\run.do,do"
STATE="utd"
TIME="1206538590"
SIZE="5162"
ENDFILE
VALUE "<project>\simulation\subsystem.bfm,sim"
STATE="utd"
TIME="1206375316"
SIZE="833"
PARENT="<project>\coreconsole\common\CORE8051S\CORE8051S.cxf"
ENDFILE
VALUE "<project>\simulation\subsystem_i.bfm,sim"
STATE="utd"
TIME="1206538598"
SIZE="1297"
ENDFILE
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem.cxf,actgen_cxf"
STATE="utd"
TIME="1206645832"
SIZE="7863"
ENDFILE
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem.gen,gen"
STATE="utd"
TIME="1206645832"
SIZE="207"
PARENT="<project>\smartgen\AnalogSystem\AnalogSystem.cxf"
ENDFILE
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem.log,log"
STATE="utd"
TIME="1206645832"
SIZE="8069"
PARENT="<project>\smartgen\AnalogSystem\AnalogSystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem.v,hdl"
STATE="utd"
TIME="1206645833"
SIZE="16167"
PARENT="<project>\smartgen\AnalogSystem\AnalogSystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem_acm_ram_R0C0.mem,sim"
STATE="utd"
TIME="1206645830"
SIZE="5120"
PARENT="<project>\smartgen\AnalogSystem\AnalogSystem.cxf"
ENDFILE
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem_assc_ram.v,hdl"
STATE="utd"
TIME="1206645831"
SIZE="1993"
PARENT="<project>\smartgen\AnalogSystem\AnalogSystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem_assc_ram_R0C0.mem,sim"
STATE="utd"
TIME="1206645832"
SIZE="5632"
PARENT="<project>\smartgen\AnalogSystem\AnalogSystem.cxf"
ENDFILE
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem_assc_wrapper.v,hdl"
STATE="utd"
TIME="1206645832"
SIZE="6394"
PARENT="<project>\smartgen\AnalogSystem\AnalogSystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem_calibip_wrapper.v,hdl"
STATE="utd"
TIME="1206641112"
SIZE="2338"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem_calibip_wrapper_R0C0.mem,sim"
STATE="utd"
TIME="1206641112"
SIZE="4224"
ENDFILE
VALUE "<project>\smartgen\common\verilog\assc.v,hdl"
STATE="utd"
TIME="1201043758"
SIZE="28127"
PARENT="<project>\smartgen\AnalogSystem\AnalogSystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\calibip.v,hdl"
STATE="utd"
TIME="1202527746"
SIZE="4624"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\calibip_brentkung_24.v,hdl"
STATE="utd"
TIME="1202527746"
SIZE="22896"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\calibip_CLRAM.v,hdl"
STATE="utd"
TIME="1202527746"
SIZE="5606"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\calibip_compute_block.v,hdl"
STATE="utd"
TIME="1202527746"
SIZE="11878"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\calibip_ram512x9_afs.v,hdl"
STATE="utd"
TIME="1202527746"
SIZE="4057"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\calibip_ripple_24.v,hdl"
STATE="utd"
TIME="1202527746"
SIZE="8261"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\initcfg.v,hdl"
STATE="utd"
TIME="1201043758"
SIZE="54019"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\initcfg_xa.v,hdl"
STATE="utd"
TIME="1201043758"
SIZE="3934"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\initcfg_xb.v,hdl"
STATE="utd"
TIME="1201043758"
SIZE="5021"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\initcfg_xc.v,hdl"
STATE="utd"
TIME="1201043758"
SIZE="13785"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\initcfg_xd.v,hdl"
STATE="utd"
TIME="1201043758"
SIZE="4064"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\initcfg_xe.v,hdl"
STATE="utd"
TIME="1201043758"
SIZE="1876"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\common\verilog\initcfg_xf.v,hdl"
STATE="utd"
TIME="1201043758"
SIZE="2844"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf,actgen_cxf"
STATE="utd"
TIME="1206714792"
SIZE="11148"
ENDFILE
VALUE "<project>\smartgen\FlashMemorySystem\FlashMemorySystem.efc,???"
STATE="utd"
TIME="1206714790"
SIZE="26645"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\FlashMemorySystem\FlashMemorySystem.gen,gen"
STATE="utd"
TIME="1206714792"
SIZE="217"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
ENDFILE
VALUE "<project>\smartgen\FlashMemorySystem\FlashMemorySystem.log,log"
STATE="utd"
TIME="1206714792"
SIZE="2936"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\FlashMemorySystem\FlashMemorySystem.mem,sim"
STATE="utd"
TIME="1206714792"
SIZE="30340"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
ENDFILE
VALUE "<project>\smartgen\FlashMemorySystem\FlashMemorySystem.v,hdl"
STATE="utd"
TIME="1206714792"
SIZE="12367"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\FlashMemorySystem\FlashMemorySystem_init_wrapper.v,hdl"
STATE="utd"
TIME="1206714792"
SIZE="28259"
PARENT="<project>\smartgen\FlashMemorySystem\FlashMemorySystem.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\InternalOscillator\InternalOscillator.cxf,actgen_cxf"
STATE="utd"
TIME="1205947389"
SIZE="1400"
ENDFILE
VALUE "<project>\smartgen\InternalOscillator\InternalOscillator.gen,gen"
STATE="utd"
TIME="1205947384"
SIZE="361"
PARENT="<project>\smartgen\InternalOscillator\InternalOscillator.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\InternalOscillator\InternalOscillator.log,log"
STATE="utd"
TIME="1205947389"
SIZE="1734"
PARENT="<project>\smartgen\InternalOscillator\InternalOscillator.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\InternalOscillator\InternalOscillator.v,hdl"
STATE="utd"
TIME="1205947389"
SIZE="744"
PARENT="<project>\smartgen\InternalOscillator\InternalOscillator.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\pll_main\pll_main.cxf,actgen_cxf"
STATE="utd"
TIME="1206376368"
SIZE="2253"
ENDFILE
VALUE "<project>\smartgen\pll_main\pll_main.gen,gen"
STATE="utd"
TIME="1206376366"
SIZE="671"
PARENT="<project>\smartgen\pll_main\pll_main.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\pll_main\pll_main.log,log"
STATE="utd"
TIME="1206376368"
SIZE="3475"
PARENT="<project>\smartgen\pll_main\pll_main.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\pll_main\pll_main.v,hdl"
STATE="utd"
TIME="1206376368"
SIZE="2714"
PARENT="<project>\smartgen\pll_main\pll_main.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\synthesis\ClosedLoopTrimDemo.edn,syn_edn"
STATE="utd"
TIME="1206645897"
SIZE="2509198"
ENDFILE
VALUE "<project>\synthesis\ClosedLoopTrimDemo_drc.rpt,log"
STATE="utd"
TIME="1206645955"
SIZE="15585"
ENDFILE
VALUE "<project>\synthesis\ClosedLoopTrimDemo_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1206645896"
SIZE="310"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "AnalogSystem::work"
FILE "<project>\smartgen\AnalogSystem\AnalogSystem.v,hdl"
LIST Other_Association
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem_acm_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem_assc_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem_calibip_wrapper_R0C0.mem,sim"
ENDLIST
ENDLIST
LIST "ClosedLoopTrimDemo::work"
FILE "<project>\hdl\ClosedLoopTrimDemo.v,hdl"
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Layout
ideSYNTHESIS(<project>\synthesis\ClosedLoopTrimDemo.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl1\ClosedLoopTrimDemo.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\ClosedLoopTrimDemo.edn,syn_edn"
VALUE "<project>\synthesis\ClosedLoopTrimDemo_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\ClosedLoopTrimDemo.v,syn_hdl"
VALUE "<project>\phy_synthesis\ClosedLoopTrimDemo_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\ClosedLoopTrimDemo_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\ClosedLoopTrimDemo_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\ClosedLoopTrimDemo_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\ClosedLoopTrimDemo_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\ClosedLoopTrimDemo.adb,adb"
VALUE "<project>\designer\impl1\ClosedLoopTrimDemo.prb,prb"
VALUE "<project>\designer\impl1\ClosedLoopTrimDemo.stp,stp"
VALUE "<project>\designer\impl1\ClosedLoopTrimDemo_fp\ClosedLoopTrimDemo.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "CORE8051S::work"
FILE "<project>\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\bfmCompile.tcl,sim"
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\coreconsole\common\CORE8051S\bfm\compiler\simSelect.do,do"
VALUE "<project>\coreconsole\common\CORE8051S\verification\sim\run_8051s_verif.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\jtagdef.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\extacs.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\extclock.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\user_ram.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\user_rom.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\oci_sys.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\tb_oci_sys.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\tb_verif.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
ideSTIMULUSEDITOR=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "CoreGPIO::work"
FILE "<project>\coreconsole\common\CoreGPIO\rtl\verilog\o\CoreGPIO.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\CoreGPIO_scriptlet.bfm,sim"
ENDLIST
ENDLIST
LIST "CoreUARTapb::work"
FILE "<project>\coreconsole\common\CoreUARTapb\rtl\verilog\o\CoreUARTapb.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\CoreUARTapb_scriptlet.bfm,sim"
VALUE "<project>\coreconsole\common\CoreUARTapb\mti\scripts\wave_vlog.do,do"
ENDLIST
ENDLIST
LIST "FlashMemorySystem::work"
FILE "<project>\smartgen\FlashMemorySystem\FlashMemorySystem.v,hdl"
LIST Other_Association
VALUE "<project>\smartgen\FlashMemorySystem\FlashMemorySystem.mem,sim"
ENDLIST
ENDLIST
LIST "ProcessorSystem::work"
FILE "<project>\coreconsole\ProcessorSystem\ProcessorSystem.v,hdl"
LIST AssociatedStimulus
VALUE "<project>\coreconsole\ProcessorSystem\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
ideSTIMULUSEDITOR=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST ProcessorSystem
VALUE "<project>\coreconsole\ProcessorSystem\testbench.v,tb_hdl"
ENDLIST
LIST CORE8051S
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\jtagdef.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\extacs.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\extclock.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\user_ram.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\user_rom.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\oci_sys.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\tb_oci_sys.v,tb_hdl"
VALUE "<project>\coreconsole\common\CORE8051S\verification\verilog\tb_verif.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST CORE8051S
VALUE "<project>\simulation\bfmCompile.tcl,sim"
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\coreconsole\common\CORE8051S\bfm\compiler\simSelect.do,do"
VALUE "<project>\coreconsole\common\CORE8051S\verification\sim\run_8051s_verif.do,do"
ENDLIST
LIST CoreGPIO
VALUE "<project>\simulation\CoreGPIO_scriptlet.bfm,sim"
ENDLIST
LIST CoreUARTapb
VALUE "<project>\simulation\CoreUARTapb_scriptlet.bfm,sim"
VALUE "<project>\coreconsole\common\CoreUARTapb\mti\scripts\wave_vlog.do,do"
ENDLIST
LIST AnalogSystem
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem_acm_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem_assc_ram_R0C0.mem,sim"
VALUE "<project>\smartgen\AnalogSystem\AnalogSystem_calibip_wrapper_R0C0.mem,sim"
ENDLIST
LIST FlashMemorySystem
VALUE "<project>\smartgen\FlashMemorySystem\FlashMemorySystem.mem,sim"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=TRUE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
Type=CoreConfigurator
Profile=CoreConsole v1.4
Tool=CoreConsole v1.3 or later
Location=C:\ProgramFiles\CoreConsole_v1.4\bin\CoreConsole.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Synthesis
Profile=Synplify pro 9.0a1
Tool=Synplify
Location=C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\bin\Synplify_pro.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Simulation
Profile=ModelSim
Tool=ModelSim
Location=C:\ProgramFiles\Libero81\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Stimulus
Profile=WFL
Tool=WFL
Location=C:\ProgramFiles\Libero81\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=false
EndProfile
Type=PhySynthesis
Profile=
Tool=
Location=
AdditionalParameter=
Batch=false
EndProfile
Type=Program
Profile=FlashPro
Tool=FlashPro
Location=C:\ProgramFiles\Libero81\FlashPro\bin\FlashPro.exe
AdditionalParameter=
Batch=false
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "ClosedLoopTrimDemo::work"
LIST Impl1
LiberoState=Post_Layout
ideSYNTHESIS(<project>\synthesis\ClosedLoopTrimDemo.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl1\ClosedLoopTrimDemo.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\ClosedLoopTrimDemo.edn,syn_edn"
VALUE "<project>\synthesis\ClosedLoopTrimDemo_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\ClosedLoopTrimDemo.v,syn_hdl"
VALUE "<project>\phy_synthesis\ClosedLoopTrimDemo_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\ClosedLoopTrimDemo_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\ClosedLoopTrimDemo_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\ClosedLoopTrimDemo_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\ClosedLoopTrimDemo_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\ClosedLoopTrimDemo.adb,adb"
VALUE "<project>\designer\impl1\ClosedLoopTrimDemo.prb,prb"
VALUE "<project>\designer\impl1\ClosedLoopTrimDemo.stp,stp"
VALUE "<project>\designer\impl1\ClosedLoopTrimDemo_fp\ClosedLoopTrimDemo.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "CORE8051S::work"
LIST Impl1
ideSTIMULUS=StateSuccess
ideSTIMULUSEDITOR=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "ProcessorSystem::work"
LIST Impl1
ideSTIMULUS=StateSuccess
ideSTIMULUSEDITOR=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
ACTIVE_VIEW:0
ENDLIST
