@TM:1206641056
@N: BN225 :"":0:0:0:-1|Writing default property annotation file C:\data\Designs\ClosedLoopTrimDemo\synthesis\ClosedLoopTrimDemo.map.
@TM:1206375610
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF176 :"":0:0:0:-1|Default generator successful 
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@N: MF258 :"":0:0:0:-1|Gated clock conversion disabled 
@W: MO111 :"":0:0:0:-1|tristate driver CORE8051S_IO0II_t on net CORE8051S_IO0II has its enable tied to GND (module CORE8051S_Z9) 
@W: MO111 :"":0:0:0:-1|tristate driver un1_Core8051s_00_4_t on net un1_Core8051s_00_4 has its enable tied to GND (module ProcessorSystem) 
@TM:1206641056
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":2:0:2:12|Synthesizing module CORE8051S_llI
@W: CL209 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4252:0:4252:12|M
@W: CL234 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4252:0:4252:12|M
@W: CL234 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4252:0:4252:12|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4264:0:4264:12|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4448:0:4448:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4456:0:4456:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4464:0:4464:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4472:0:4472:14|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4507:0:4507:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4638:0:4638:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4646:0:4646:14|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4657:0:4657:14|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\alu.v":4665:0:4665:14|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\clkctrl.v":2:0:2:14|Synthesizing module CORE8051S_O1III
@W: CL234 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\clkctrl.v":4181:0:4181:12|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\clkctrl.v":4249:0:4249:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\clkctrl.v":4252:0:4252:14|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\clkctrl.v":4272:0:4272:5|M
@W: CL170 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\clkctrl.v":4272:0:4272:5|M
@W: CL171 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\clkctrl.v":4410:0:4410:5|M
@W: CL190 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\clkctrl.v":4410:0:4410:5|M
@W: MO129 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\clkctrl.v":4410:0:4410:5|M
@W: MO129 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\clkctrl.v":4410:0:4410:5|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":2:0:2:8|Synthesizing module CORE8051S
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":257:0:257:6|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":263:0:263:2|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":266:0:266:2|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":269:0:269:2|M
@W: CL157 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":269:0:269:2|M
@W: MO111 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\core8051s.v":269:0:269:2|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":272:0:272:4|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":286:0:286:6|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":301:0:301:14|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":304:0:304:14|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":370:0:370:14|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":378:0:378:12|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":381:0:381:12|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":384:0:384:14|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s.v":431:0:431:14|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s_globs_fusion.v":2:0:2:14|Synthesizing module CORE8051S_lllII
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s_globs_fusion.v":54:0:54:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s_globs_fusion.v":60:0:60:2|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s_globs_fusion.v":63:0:63:14|M
@W: CL157 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\core8051s_globs_fusion.v":63:0:63:14|M
@W: MO111 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\core8051s_globs_fusion.v":63:0:63:14|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\cpu.v":2:0:2:14|Synthesizing module CORE8051S_I00lI
@W: CL209 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\cpu.v":4307:0:4307:12|M
@W: CL234 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\cpu.v":4307:0:4307:12|M
@W: CL234 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\cpu.v":4307:0:4307:12|M
@N: MF179 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\cpu.v":4613:0:4616:0|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\cpu.v":4661:0:4661:5|M
@N: MF179 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\cpu.v":4877:0:4880:0|M
@N:  :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\cpu.v":5035:0:5035:5|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\cpu.v":5171:0:5171:5|M
@N: MO106 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\cpu.v":5231:0:5231:3|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\instrdec.v":2:0:2:14|Synthesizing module CORE8051S_OOO1I
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":2:0:2:14|Synthesizing module CORE8051S_lOO1I
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4208:0:4208:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4214:0:4214:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4220:0:4220:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4223:0:4223:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4226:0:4226:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4229:0:4229:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4232:0:4232:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4235:0:4235:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4238:0:4238:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4241:0:4241:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4244:0:4244:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4247:0:4247:14|M
@W: CL209 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4317:0:4317:12|M
@W: CL234 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4317:0:4317:12|M
@W: CL234 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4346:0:4346:12|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4762:0:4762:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4765:0:4765:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4768:0:4768:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4771:0:4771:14|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\isr.v":4941:0:4941:5|M
@W: CL170 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":4941:0:4941:5|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":5098:0:5098:5|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\isr.v":5255:0:5255:5|M
@W: CL170 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":5255:0:5255:5|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\isr.v":5412:0:5412:5|M
@W: CL170 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":5412:0:5412:5|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":5460:0:5460:5|M
@W: CL171 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":6853:0:6853:5|M
@W: CL171 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":6853:0:6853:5|M
@W: CL190 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":6853:0:6853:5|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":7139:0:7139:5|M
@W: CL190 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":7139:0:7139:5|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\isr.v":7422:0:7422:5|M
@W: CL171 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":7422:0:7422:5|M
@W: CL190 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":7422:0:7422:5|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":7533:0:7533:5|M
@W: CL190 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\isr.v":7533:0:7533:5|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\isr.v":7596:0:7596:5|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\isr.v":7659:0:7659:5|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\main8051.v":2:0:2:14|Synthesizing module CORE8051S_OIIlI
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":2:0:2:14|Synthesizing module CORE8051S_OI1Il
@W: CL234 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":4240:0:4240:14|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":4296:0:4296:14|M
@W: CL234 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":4414:0:4414:12|M
@W: CL234 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":4463:0:4463:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":4599:0:4599:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":4607:0:4607:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":4615:0:4615:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":4623:0:4623:14|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":4724:0:4724:14|M
@N: CL201 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":5045:0:5045:5|M
@W: BN132 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\memctrl.v":5070:0:5070:5|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\memctrl.v":5502:0:5502:5|M
@N: MF238 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\memctrl.v":6478:0:6483:0|M
@N: MF238 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\memctrl.v":6661:0:6666:0|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\memctrl.v":8372:0:8372:5|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\memctrl.v":8551:0:8551:5|M
@W: CL207 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":8912:0:8912:5|M
@W: CL207 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\memctrl.v":9304:0:9304:5|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\oci.v":2:0:2:14|Synthesizing module CORE8051S_IIOll
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\oci.v":4277:0:4277:5|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\pmu.v":2:0:2:14|Synthesizing module CORE8051S_Il1Il
@W: CL234 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\pmu.v":4154:0:4154:12|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\pmu.v":4296:0:4296:5|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\pmu.v":4350:0:4350:5|M
@W: BN132 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\pmu.v":4394:0:4394:5|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\RAM256X8.v":3:0:3:12|Synthesizing module CORE8051S_lII
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\ramsfrctrl.v":2:0:2:14|Synthesizing module CORE8051S_I11Il
@W: CL234 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\ramsfrctrl.v":4397:0:4397:12|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\ramsfrctrl.v":6273:0:6273:5|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CORE8051S\rtl\verilog\o\rstctrl.v":2:0:2:14|Synthesizing module CORE8051S_O01Il
@W: MO129 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\rstctrl.v":4731:0:4731:5|M
@W: BN132 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\core8051s\rtl\verilog\o\rstctrl.v":4814:0:4814:5|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":3:0:3:7|Synthesizing module CoreAPB3
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":358:0:358:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":366:0:366:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":374:0:374:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":382:0:382:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":398:0:398:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":414:0:414:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":422:0:422:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":430:0:430:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":438:0:438:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":446:0:446:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":454:0:454:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":462:0:462:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":470:0:470:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":478:0:478:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":481:0:481:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":484:0:484:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":487:0:487:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":490:0:490:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":496:0:496:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":502:0:502:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":505:0:505:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":508:0:508:7|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":511:0:511:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":514:0:514:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":517:0:517:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":520:0:520:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":523:0:523:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":526:0:526:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":529:0:529:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":532:0:532:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":535:0:535:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":538:0:538:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":544:0:544:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":550:0:550:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":553:0:553:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":556:0:556:8|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":559:0:559:9|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":562:0:562:9|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":565:0:565:9|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":568:0:568:9|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":571:0:571:9|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\CoreAPB3.v":574:0:574:9|M
@N: MO106 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\coreapb3\rtl\verilog\o\coreapb3.v":1393:0:1393:3|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreAPB3\rtl\verilog\o\MuxPtoB3.v":3:0:3:11|Synthesizing module CoreAPB3_ll0
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreGPIO\rtl\verilog\o\CoreGPIO.v":3:0:3:7|Synthesizing module CoreGPIO
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreGPIO\rtl\verilog\o\CoreGPIO.v":54:0:54:4|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\coregpio\rtl\verilog\o\coregpio.v":208:0:208:5|M
@W: MO129 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\coregpio\rtl\verilog\o\coregpio.v":282:0:282:5|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Clock_gen.v":19:0:19:13|Synthesizing module CoreUARTapb_II
@N:  :"c:\data\designs\closedlooptrimdemo\coreconsole\common\coreuartapb\rtl\verilog\o\clock_gen.v":80:0:80:5|M
@N:  :"c:\data\designs\closedlooptrimdemo\coreconsole\common\coreuartapb\rtl\verilog\o\clock_gen.v":155:0:155:5|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\CoreUARTapb.v":3:0:3:10|Synthesizing module CoreUARTapb
@N: CG179 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\CoreUARTapb.v":503:0:503:14|M
@N: CG179 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\CoreUARTapb.v":566:0:566:14|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Rx_async.v":3:0:3:14|Synthesizing module CoreUARTapb_OI1
@N:  :"c:\data\designs\closedlooptrimdemo\coreconsole\common\coreuartapb\rtl\verilog\o\rx_async.v":374:0:374:5|M
@N: CL201 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Rx_async.v":584:0:584:5|M
@N:  :"c:\data\designs\closedlooptrimdemo\coreconsole\common\coreuartapb\rtl\verilog\o\rx_async.v":771:0:771:5|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\coreconsole\common\coreuartapb\rtl\verilog\o\rx_async.v":1218:0:1218:5|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_async.v":3:0:3:15|Synthesizing module CoreUARTapb_OIII
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_async.v":65:0:65:15|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_async.v":68:0:68:15|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_async.v":71:0:71:15|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_async.v":170:0:170:14|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_async.v":251:0:251:5|M
@W: CL190 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_async.v":251:0:251:5|M
@N: CL201 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_async.v":251:0:251:5|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_async.v":524:0:524:5|M
@W: CL190 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_async.v":524:0:524:5|M
@N:  :"c:\data\designs\closedlooptrimdemo\coreconsole\common\coreuartapb\rtl\verilog\o\tx_async.v":595:0:595:5|M
@N: CG179 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\Tx_async.v":821:0:821:15|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":3:0:3:14|Synthesizing module CoreUARTapb_I0l
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":195:0:195:15|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":203:0:203:15|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":233:0:233:15|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":236:0:236:15|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":248:0:248:15|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":251:0:251:15|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":254:0:254:15|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":269:0:269:15|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":272:0:272:15|M
@W: CG133 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":278:0:278:15|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":299:0:299:5|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":569:0:569:5|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":607:0:607:5|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":725:0:725:5|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":774:0:774:5|M
@W: CL156 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\common\CoreUARTapb\rtl\verilog\o\UART.v":930:0:930:15|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\ProcessorSystem\ProcessorSystem.v":7:7:7:21|Synthesizing module ProcessorSystem
@W: CS149 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\ProcessorSystem\ProcessorSystem.v":250:16:250:34|M
@W: CS149 :"C:\data\Designs\ClosedLoopTrimDemo\coreconsole\ProcessorSystem\ProcessorSystem.v":254:16:254:43|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\hdl\ClosedLoopTrimDemo.v":11:7:11:24|Synthesizing module ClosedLoopTrimDemo
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\hdl\ClosedLoopTrimDemo.v":53:7:53:19|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\hdl\ClosedLoopTrimDemo.v":54:11:54:22|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\hdl\ClosedLoopTrimDemo.v":55:7:55:16|M
@TM:1206645898
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\hdl\ClosedLoopTrimDemo.v":61:16:61:32|M
@W: CG360 :"C:\data\Designs\ClosedLoopTrimDemo\hdl\ClosedLoopTrimDemo.v":62:16:62:34|M
@TM:1206641056
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\hdl\CoreDAC.v":12:7:12:13|Synthesizing module CoreDAC
@W: CL168 :"C:\data\Designs\ClosedLoopTrimDemo\hdl\CoreDAC.v":443:6:443:10|M
@W: CL168 :"C:\data\Designs\ClosedLoopTrimDemo\hdl\CoreDAC.v":446:6:446:10|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\AnalogSystem\AnalogSystem.v":5:7:5:18|Synthesizing module AnalogSystem
@TM:1206645898
@W: CL168 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\AnalogSystem\AnalogSystem.v":239:8:239:22|M
@TM:1206641056
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\AnalogSystem\AnalogSystem_assc_ram.v":5:7:5:27|Synthesizing module AnalogSystem_assc_ram
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\AnalogSystem\AnalogSystem_assc_wrapper.v":1:7:1:31|Synthesizing module AnalogSystem_assc_wrapper
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\assc.v":10:7:10:17|Synthesizing module fmvgpwbdcxs
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\assc.v":26:52:26:62|M
@W: CL159 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\assc.v":27:0:27:10|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\smartgen\common\verilog\assc.v":169:37:169:42|M
@W: BN116 :"c:\data\designs\closedlooptrimdemo\smartgen\common\verilog\assc.v":187:54:187:59|M
@N: CL201 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\assc.v":243:12:243:17|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\assc.v":250:33:250:38|M
@W: CL169 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\assc.v":266:50:266:55|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\assc.v":333:7:333:10|Synthesizing module ASSC
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg.v":10:7:10:17|Synthesizing module grwzcnqmqzm
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg.v":447:7:447:13|Synthesizing module INITCFG
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xa.v":10:7:10:17|Synthesizing module stnpfdkggvx
@N: CL201 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xa.v":37:64:37:69|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xa.v":51:7:51:16|Synthesizing module INITCFG_XA
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xb.v":10:7:10:17|Synthesizing module wbsfnwwctpn
@N: CL201 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xb.v":44:10:44:15|M
@W: MO129 :"c:\data\designs\closedlooptrimdemo\smartgen\common\verilog\initcfg_xb.v":56:0:56:10|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xb.v":65:7:65:16|Synthesizing module INITCFG_XB
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xc.v":10:7:10:17|Synthesizing module ffppvfwnggt
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xc.v":155:7:155:16|Synthesizing module INITCFG_XC
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xd.v":10:7:10:17|Synthesizing module dxwqxgdccxc
@N:  :"c:\data\designs\closedlooptrimdemo\smartgen\common\verilog\initcfg_xd.v":43:24:43:29|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xd.v":54:7:54:16|Synthesizing module INITCFG_XD
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xe.v":10:7:10:17|Synthesizing module gpbdjfttbjd
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xe.v":26:7:26:16|Synthesizing module INITCFG_XE
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xf.v":10:7:10:17|Synthesizing module jhmkpjjmdkx
@W: MO129 :"c:\data\designs\closedlooptrimdemo\smartgen\common\verilog\initcfg_xf.v":28:55:28:60|M
@W: MO129 :"c:\data\designs\closedlooptrimdemo\smartgen\common\verilog\initcfg_xf.v":31:33:31:38|M
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\common\verilog\initcfg_xf.v":38:7:38:16|Synthesizing module INITCFG_XF
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\FlashMemorySystem\FlashMemorySystem.v":5:7:5:23|Synthesizing module FlashMemorySystem
@TM:1206645898
@W: CL168 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\FlashMemorySystem\FlashMemorySystem.v":218:8:218:22|M
@TM:1206641056
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\FlashMemorySystem\FlashMemorySystem_init_wrapper.v":1:7:1:36|Synthesizing module FlashMemorySystem_init_wrapper
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\InternalOscillator\InternalOscillator.v":5:7:5:24|Synthesizing module InternalOscillator
@N: CG364 :"C:\data\Designs\ClosedLoopTrimDemo\smartgen\pll_main\pll_main.v":5:7:5:14|Synthesizing module pll_main
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":43:7:43:10|Synthesizing module AO13
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":79:7:79:9|Synthesizing module AO1
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":91:7:91:10|Synthesizing module AO1B
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":126:7:126:11|Synthesizing module AOI1B
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":167:7:167:10|Synthesizing module AX1D
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":992:7:992:12|Synthesizing module DFN1C0
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":1064:7:1064:12|Synthesizing module DFN1P0
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":1224:7:1224:9|Synthesizing module GND
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":1394:7:1394:9|Synthesizing module INV
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":1399:7:1399:10|Synthesizing module MAJ3
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":1417:7:1417:10|Synthesizing module MIN3
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":1499:7:1499:11|Synthesizing module NOR2A
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":1505:7:1505:11|Synthesizing module NOR2B
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":1561:7:1561:9|Synthesizing module OR2
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":2043:7:2043:9|Synthesizing module VCC
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":2047:7:2047:9|Synthesizing module XA1
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":2053:7:2053:10|Synthesizing module XA1A
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":2083:7:2083:11|Synthesizing module XNOR2
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":2106:7:2106:10|Synthesizing module XOR2
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":2111:7:2111:10|Synthesizing module XOR3
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":2135:7:2135:12|Synthesizing module CLKINT
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":2267:8:2267:13|Synthesizing module RAM4K9
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":2935:7:2935:11|Synthesizing module RCOSC
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":2974:7:2974:9|Synthesizing module PLL
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":3147:7:3147:9|Synthesizing module NVM
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":3204:7:3204:8|Synthesizing module AB
@N: CG364 :"C:\ProgramFiles\Libero81\Synplify\Synplify_90A1\lib\proasic\fusion.v":3373:7:3373:13|Synthesizing module INBUF_A
