Version:8.2.2.2
ACTGENU_CALL:1
BATCH:T
FAM:Fusion
OUTFORMAT:Verilog
LPMTYPE:LPM_CCC_RCOSC
LPM_HINT:NONE
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:T
"DESDIR:C:/data/Designs/ClosedLoopTrimDemo/smartgen\InternalOscillator"
GEN_BEHV_MODULE:T
SMARTGEN_DIE:IR6X6M2
SMARTGEN_PACKAGE:fg256
DRIVE_MODE:1
