quietly set ACTELLIBNAME fusion
quietly set PROJECT_DIR "C:/data/Designs/ClosedLoopTrimDemo"
source "${PROJECT_DIR}/simulation/bfmCompile.tcl"

if {[file exists presynth/_info]} {
   puts "INFO: Simulation library presynth already exists"
} else {
   vlib presynth
}
vmap presynth presynth
vmap fusion "C:/ProgramFiles/Libero83/Designer/lib/modelsim/precompiled/vlog/fusion"
if {[file exists ../coreconsole/common/CoreUARTapb/mti/lib_vlog_obs/COREUARTAPB_LIB/_info]} {
   puts "INFO: Simulation library ../coreconsole/common/CoreUARTapb/mti/lib_vlog_obs/COREUARTAPB_LIB already exists"
} else {
   vlib ../coreconsole/common/CoreUARTapb/mti/lib_vlog_obs/COREUARTAPB_LIB
}
vmap COREUARTAPB_LIB "../coreconsole/common/CoreUARTapb/mti/lib_vlog_obs/COREUARTAPB_LIB"

vlog -work presynth "${PROJECT_DIR}/smartgen/InternalOscillator/InternalOscillator.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/pll_main/pll_main.v"
vlog -work presynth "${PROJECT_DIR}/hdl/CoreDAC.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/alu.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/clkctrl.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/cpu.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/isr.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/memctrl.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/pmu.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/rstctrl.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/ramsfrctrl.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/oci.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/instrdec.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/main8051.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/core8051s_globs_fusion.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/RAM256X8.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/jtagfusion.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/jtag.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/debug.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/trace.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/trigger.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/ocia51.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/RAM256X20.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CORE8051S/rtl/verilog/o/core8051s.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CoreAPB3/rtl/verilog/o/MuxPtoB3.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CoreAPB3/rtl/verilog/o/CoreAPB3.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CoreGPIO/rtl/verilog/o/CoreGPIO.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CoreUARTapb/rtl/verilog/o/Clock_gen.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CoreUARTapb/rtl/verilog/o/Tx_async.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CoreUARTapb/rtl/verilog/o/Tx_sync.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CoreUARTapb/rtl/verilog/o/Rx_async.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CoreUARTapb/rtl/verilog/o/Rx_sync.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CoreUARTapb/rtl/verilog/o/fifo_256x8.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CoreUARTapb/rtl/verilog/o/UART.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/common/CoreUARTapb/rtl/verilog/o/CoreUARTapb.v"
vlog -work presynth "${PROJECT_DIR}/coreconsole/ProcessorSystem/ProcessorSystem.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/common/verilog/assc.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/AnalogSystem/AnalogSystem_assc_wrapper.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/AnalogSystem/AnalogSystem_assc_ram.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/AnalogSystem/AnalogSystem.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/common/verilog/initcfg_xa.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/common/verilog/initcfg_xb.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/common/verilog/initcfg_xc.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/common/verilog/initcfg_xd.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/common/verilog/initcfg_xe.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/common/verilog/initcfg_xf.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/common/verilog/initcfg.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/FlashMemorySystem/FlashMemorySystem_init_wrapper.v"
vlog -work presynth "${PROJECT_DIR}/smartgen/FlashMemorySystem/FlashMemorySystem.v"
vlog -work presynth "${PROJECT_DIR}/hdl/ClosedLoopTrimDemo.v"
vlog "+incdir+${PROJECT_DIR}/stimulus" -work presynth "${PROJECT_DIR}/stimulus/ClosedLoopTrimDemo_tbench.v"

vsim -L fusion -L presynth -L COREUARTAPB_LIB  -t 1ps presynth.testbench
add wave /testbench/*
run 1000ns
