# Reading C:/ProgramFiles/Libero83/Model/tcl/vsim/pref.tcl 
# do run.do 
# CoreMP7 BFM Compiler v2.1
# BFM script compiled successfully
# INFO: Simulation library presynth already exists
# Modifying modelsim.ini
# Modifying modelsim.ini
# INFO: Simulation library ../coreconsole/common/CoreUARTapb/mti/lib_vlog_obs/COREUARTAPB_LIB already exists
# Modifying modelsim.ini
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module InternalOscillator
# 
# Top level modules:
# 	InternalOscillator
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module pll_main
# 
# Top level modules:
# 	pll_main
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CoreDAC
# 
# Top level modules:
# 	CoreDAC
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_llI
# 
# Top level modules:
# 	CORE8051S_llI
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_O1III
# 
# Top level modules:
# 	CORE8051S_O1III
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_I00lI
# 
# Top level modules:
# 	CORE8051S_I00lI
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_lOO1I
# 
# Top level modules:
# 	CORE8051S_lOO1I
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_OI1Il
# 
# Top level modules:
# 	CORE8051S_OI1Il
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_Il1Il
# 
# Top level modules:
# 	CORE8051S_Il1Il
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_O01Il
# 
# Top level modules:
# 	CORE8051S_O01Il
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_I11Il
# 
# Top level modules:
# 	CORE8051S_I11Il
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_IIOll
# 
# Top level modules:
# 	CORE8051S_IIOll
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_OOO1I
# 
# Top level modules:
# 	CORE8051S_OOO1I
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_OIIlI
# 
# Top level modules:
# 	CORE8051S_OIIlI
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_lllII
# 
# Top level modules:
# 	CORE8051S_lllII
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_lII
# 
# Top level modules:
# 	CORE8051S_lII
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_O1IIl
# 
# Top level modules:
# 	CORE8051S_O1IIl
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_O10Ol
# 
# Top level modules:
# 	CORE8051S_O10Ol
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_IOI0I
# 
# Top level modules:
# 	CORE8051S_IOI0I
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_lOI0l
# 
# Top level modules:
# 	CORE8051S_lOI0l
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_III0l
# 
# Top level modules:
# 	CORE8051S_III0l
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_I0llI
# 
# Top level modules:
# 	CORE8051S_I0llI
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S_O
# 
# Top level modules:
# 	CORE8051S_O
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CORE8051S
# 
# Top level modules:
# 	CORE8051S
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CoreAPB3_ll0
# 
# Top level modules:
# 	CoreAPB3_ll0
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CoreAPB3
# 
# Top level modules:
# 	CoreAPB3
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CoreGPIO
# 
# Top level modules:
# 	CoreGPIO
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CoreUARTapb_II
# 
# Top level modules:
# 	CoreUARTapb_II
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CoreUARTapb_OIII
# 
# Top level modules:
# 	CoreUARTapb_OIII
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CoreUARTapb_IO0I
# 
# Top level modules:
# 	CoreUARTapb_IO0I
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CoreUARTapb_OI1
# 
# Top level modules:
# 	CoreUARTapb_OI1
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CoreUARTapb_lOII
# 
# Top level modules:
# 	CoreUARTapb_lOII
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CoreUARTapb_O1l
# -- Compiling module CoreUARTapb_ll0
# 
# Top level modules:
# 	CoreUARTapb_O1l
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CoreUARTapb_I0l
# 
# Top level modules:
# 	CoreUARTapb_I0l
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module CoreUARTapb
# 
# Top level modules:
# 	CoreUARTapb
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module ProcessorSystem
# 
# Top level modules:
# 	ProcessorSystem
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module fmvgpwbdcxs
# -- Compiling module ASSC
# 
# Top level modules:
# 	ASSC
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module AnalogSystem_assc_wrapper
# 
# Top level modules:
# 	AnalogSystem_assc_wrapper
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module AnalogSystem_assc_ram
# 
# Top level modules:
# 	AnalogSystem_assc_ram
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module AnalogSystem
# 
# Top level modules:
# 	AnalogSystem
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module stnpfdkggvx
# -- Compiling module INITCFG_XA
# 
# Top level modules:
# 	INITCFG_XA
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module wbsfnwwctpn
# -- Compiling module INITCFG_XB
# 
# Top level modules:
# 	INITCFG_XB
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module ffppvfwnggt
# -- Compiling module INITCFG_XC
# 
# Top level modules:
# 	INITCFG_XC
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module dxwqxgdccxc
# -- Compiling module INITCFG_XD
# 
# Top level modules:
# 	INITCFG_XD
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module gpbdjfttbjd
# -- Compiling module INITCFG_XE
# 
# Top level modules:
# 	INITCFG_XE
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module jhmkpjjmdkx
# -- Compiling module INITCFG_XF
# 
# Top level modules:
# 	INITCFG_XF
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module grwzcnqmqzm
# -- Compiling module INITCFG
# 
# Top level modules:
# 	INITCFG
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module FlashMemorySystem_init_wrapper
# 
# Top level modules:
# 	FlashMemorySystem_init_wrapper
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module FlashMemorySystem
# 
# Top level modules:
# 	FlashMemorySystem
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module ClosedLoopTrimDemo
# 
# Top level modules:
# 	ClosedLoopTrimDemo
# Model Technology ModelSim ACTEL vlog 6.3c Compiler 2007.09 Sep 12 2007
# -- Compiling module stimulus
# -- Compiling module testbench
# 
# Top level modules:
# 	testbench
# vsim -L fusion -L presynth -L COREUARTAPB_LIB -t 1ps presynth.testbench 
# //  ModelSim ACTEL 6.3c Sep 12 2007 
# //
# //  Copyright 1991-2007 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading presynth.testbench
# Loading presynth.stimulus
# Loading presynth.ClosedLoopTrimDemo
# ** Warning: (vsim-3009) [TSCALE] - Module 'ClosedLoopTrimDemo' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0
# Loading presynth.InternalOscillator
# Loading fusion.RCOSC
# Loading presynth.pll_main
# Loading fusion.VCC
# Loading fusion.GND
# Loading fusion.PLL
# Loading fusion.PLLPRIM
# Loading fusion.CLKINT
# Loading presynth.CoreDAC
# ** Warning: (vsim-3009) [TSCALE] - Module 'CoreDAC' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/DAC_inst
# Loading fusion.AOI1B
# Loading fusion.MIN3
# Loading fusion.NOR2B
# Loading fusion.XA1
# Loading fusion.AO1B
# Loading fusion.MAJ3
# Loading fusion.XOR2
# Loading fusion.AX1D
# Loading fusion.XOR3
# Loading fusion.NOR2A
# Loading fusion.XA1A
# Loading fusion.AO1
# Loading fusion.AO13
# Loading fusion.XNOR2
# Loading fusion.DFN1C0
# Loading fusion.DFN1P0
# Loading presynth.ProcessorSystem
# Loading presynth.CORE8051S
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00
# Loading presynth.CORE8051S_OIIlI
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S_OIIlI' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00/CORE8051S_IIIlI
# Loading presynth.CORE8051S_llI
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S_llI' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00/CORE8051S_IIIlI/CORE8051S_l10Il
# Loading presynth.CORE8051S_O1III
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S_O1III' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00/CORE8051S_IIIlI/CORE8051S_OO1Il
# Loading presynth.CORE8051S_I00lI
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S_I00lI' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00/CORE8051S_IIIlI/CORE8051S_IO1Il
# Loading presynth.CORE8051S_lOO1I
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S_lOO1I' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00/CORE8051S_IIIlI/CORE8051S_lO1Il
# Loading presynth.CORE8051S_OI1Il
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S_OI1Il' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00/CORE8051S_IIIlI/CORE8051S_II1Il
# Loading presynth.CORE8051S_Il1Il
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S_Il1Il' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00/CORE8051S_IIIlI/CORE8051S_ll1Il
# Loading presynth.CORE8051S_O01Il
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S_O01Il' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00/CORE8051S_IIIlI/CORE8051S_I01Il
# Loading presynth.CORE8051S_I11Il
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S_I11Il' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00/CORE8051S_IIIlI/CORE8051S_l11Il
# Loading presynth.CORE8051S_IIOll
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S_IIOll' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00/CORE8051S_IIIlI/CORE8051S_lIOll
# Loading presynth.CORE8051S_OOO1I
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S_OOO1I' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00/CORE8051S_IIIlI/CORE8051S_OlOll
# Loading presynth.CORE8051S_lllII
# ** Warning: (vsim-3009) [TSCALE] - Module 'CORE8051S_lllII' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/Core8051s_00/CORE8051S_llllI
# Loading presynth.CORE8051S_lII
# Loading fusion.INV
# Loading fusion.RAM4K9
# Loading fusion.CORERAM4K9
# Loading presynth.CoreAPB3
# Loading presynth.CoreAPB3_ll0
# Loading presynth.CoreGPIO
# Loading presynth.CoreUARTapb
# Loading presynth.CoreUARTapb_I0l
# Loading presynth.AnalogSystem
# Loading fusion.OR2
# Loading fusion.AB
# Loading fusion.read_analog_io
# Loading fusion.drive_varef_out
# Loading fusion.INBUF_A
# Loading presynth.AnalogSystem_assc_wrapper
# ** Warning: (vsim-3009) [TSCALE] - Module 'AnalogSystem_assc_wrapper' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/backbone_inst/AnalogSystem_assc_wrapper_inst
# Loading presynth.ASSC
# Loading presynth.fmvgpwbdcxs
# Loading presynth.AnalogSystem_assc_ram
# Loading presynth.FlashMemorySystem
# Loading presynth.FlashMemorySystem_init_wrapper
# ** Warning: (vsim-3009) [TSCALE] - Module 'FlashMemorySystem_init_wrapper' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/ClosedLoopTrimDemo_0/FlashSys_inst/FlashMemorySystem_init_wrapper_inst
# Loading presynth.INITCFG
# Loading presynth.grwzcnqmqzm
# Loading presynth.INITCFG_XA
# Loading presynth.stnpfdkggvx
# Loading presynth.INITCFG_XB
# Loading presynth.wbsfnwwctpn
# Loading presynth.INITCFG_XC
# Loading presynth.ffppvfwnggt
# Loading presynth.INITCFG_XD
# Loading presynth.dxwqxgdccxc
# Loading presynth.INITCFG_XE
# Loading presynth.gpbdjfttbjd
# Loading presynth.INITCFG_XF
# Loading presynth.jhmkpjjmdkx
# Loading fusion.NVM
# Loading presynth.CoreUARTapb_II
# Loading presynth.CoreUARTapb_OIII
# Loading presynth.CoreUARTapb_OI1
# Loading fusion.UDP_MUX2
# Loading fusion.UDPN_MUX2
# Loading fusion.Dffpr
# ** Warning: (vsim-3015) C:/data/Designs/ClosedLoopTrimDemo/coreconsole/ProcessorSystem/ProcessorSystem.v(256): [PCDPC] - Port size (16 or 16) does not match connection size (32) for port 'PWDATA'.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/CoreGPIO_00
# ** Warning: (vsim-3015) C:/data/Designs/ClosedLoopTrimDemo/coreconsole/ProcessorSystem/ProcessorSystem.v(256): [PCDPC] - Port size (16 or 16) does not match connection size (32) for port 'PRDATA'.
#         Region: /testbench/ClosedLoopTrimDemo_0/ProcSys_inst/CoreGPIO_00
# ** Warning: (vsim-3017) C:/data/Designs/ClosedLoopTrimDemo/hdl/ClosedLoopTrimDemo.v(292): [TFMPC] - Too few port connections. Expected 31, found 29.
#         Region: /testbench/ClosedLoopTrimDemo_0/FlashSys_inst
# ** Warning: (vsim-3015) C:/data/Designs/ClosedLoopTrimDemo/hdl/ClosedLoopTrimDemo.v(292): [PCDPC] - Port size (11 or 11) does not match connection size (9) for port 'INIT_ADDR'.
#         Region: /testbench/ClosedLoopTrimDemo_0/FlashSys_inst
# ** Warning: (vsim-3722) C:/data/Designs/ClosedLoopTrimDemo/hdl/ClosedLoopTrimDemo.v(292): [TFMPC] - Missing connection for port 'INIT_CALIBROM_WEN'.
# ** Warning: (vsim-3722) C:/data/Designs/ClosedLoopTrimDemo/hdl/ClosedLoopTrimDemo.v(292): [TFMPC] - Missing connection for port 'INIT_CALIBCOEFF_WEN'.
#  Module testbench.ClosedLoopTrimDemo_0.FlashSys_inst.NVM_INST_CALIBRATIONDATA: Warning: BUSY SIGNAL DE-ASSERTION IN SIMULATION MAY NOT MATCH WITH SILICON BEHAVIOR
#  Module testbench.ClosedLoopTrimDemo_0.FlashSys_inst.NVM_INST_CALIBRATIONDATA: Warning: USER LOGIC SHOULD POLL FOR BUSY TO ENSURE BEHAVIOR CONSISTENT WITH SILICON
#  Note: Memory initialization file parameter MEMORYFILE not defined 
#  Time: 0.0 Instance: testbench.ClosedLoopTrimDemo_0.backbone_inst.AB_INST 
#  ** Warning: OCDIVHALF unknown.
#  Time: 0.0 Instance: testbench.ClosedLoopTrimDemo_0.u_pll_main.Core.P1 
#  ** Warning: OBDIVHALF unknown.
#  Time: 0.0 Instance: testbench.ClosedLoopTrimDemo_0.u_pll_main.Core.P1 
#  ** Warning: OADIVHALF unknown.
#  Time: 0.0 Instance: testbench.ClosedLoopTrimDemo_0.u_pll_main.Core.P1 
#  ** Warning: FBSEL is unknown.
#  Time: 0.0 Instance: testbench.ClosedLoopTrimDemo_0.u_pll_main.Core.P1 
#  ** Warning: FBSEL is unknown.
#  Time: 0.0 Instance: testbench.ClosedLoopTrimDemo_0.u_pll_main.Core.P1 
#  Warning : Reserved ADC mode 
#  Time: 0.0 Instance: testbench.ClosedLoopTrimDemo_0.backbone_inst.AB_INST 
#  Warning : Reserved ADC mode 
#  Time: 2800.0 Instance: testbench.ClosedLoopTrimDemo_0.backbone_inst.AB_INST 
#  ** Warning: RESET went unknown 
#  Time: 2.8 Instance: testbench.ClosedLoopTrimDemo_0.FlashSys_inst.NVM_INST_CALIBRATIONDATA 
run
#  Warning : Reserved ADC mode 
#  Time: 1192230.0 Instance: testbench.ClosedLoopTrimDemo_0.backbone_inst.AB_INST 
#  Warning : ACMWEN is unknown 
#  Time: 1192230.0 Instance: testbench.ClosedLoopTrimDemo_0.backbone_inst.AB_INST 
#  ** Warning: RESET went unknown 
#  Time: 1192.2 Instance: testbench.ClosedLoopTrimDemo_0.FlashSys_inst.NVM_INST_CALIBRATIONDATA 
#  Warning : Reserved ADC mode 
#  Time: 1192230.0 Instance: testbench.ClosedLoopTrimDemo_0.backbone_inst.AB_INST 
#  ** Warning: CLK went unknown 
#  Time: 1205.8 Instance: testbench.ClosedLoopTrimDemo_0.FlashSys_inst.NVM_INST_CALIBRATIONDATA 
#  ** Warning: CLK went unknown 
#  Time: 1219.4 Instance: testbench.ClosedLoopTrimDemo_0.FlashSys_inst.NVM_INST_CALIBRATIONDATA 
#  ** Warning: CLK went unknown 
#  Time: 1232.9 Instance: testbench.ClosedLoopTrimDemo_0.FlashSys_inst.NVM_INST_CALIBRATIONDATA 
#  Warning : Reserved ADC mode 
#  Time: 1246486.0 Instance: testbench.ClosedLoopTrimDemo_0.backbone_inst.AB_INST 
#  Warning : Reserved ADC mode 
#  Time: 1246486.0 Instance: testbench.ClosedLoopTrimDemo_0.backbone_inst.AB_INST 
