<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>InternalOscillator</name><vendor/><library/><version/><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>InternalOscillator.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="OTHER_FILESET"><file fileid="1"><name>InternalOscillator.gen</name><fileType><userFileType type="GEN"/></fileType></file><file fileid="2"><name>InternalOscillator.log</name><fileType><userFileType type="LOG"/></fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>OTHER_FILESET</fileSetRef><name>OTHER</name></view></views></hwModel><category>Clock Conditioning / PLL</category><function>RC Oscillator</function><variation>RC Oscillator</variation><vendor>Actel</vendor><version>2.1</version><busInterfaces><busInterface><name>RCOscClk_bif</name><busType library="busdef.clock" name="RCOscClk" vendor="Actel" version="1.0"/><master/><signalMap><signal><componentSignalName>CLKOUT</componentSignalName><busSignalName>RCCLKOUT</busSignalName></signal></signalMap></busInterface></busInterfaces><model><signals><signal><name>CLKOUT</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>