<?xml version="1.0" encoding="UTF-8"?>
<component>
<name>ProcessorSystem</name>
<views>
<view>
<name>HDL</name>
<fileSetRef>HDL_FILESET</fileSetRef>
<fileSetRef>STIMULUS_FILESET</fileSetRef>
</view>
<view>
<name>Components</name>
<fileSetRef>COMPONENT_FILESET</fileSetRef>
</view>
</views>
<fileSets>
<fileSet fileSetId="HDL_FILESET">
<file>
<name>ProcessorSystem.v</name>
<fileType>verilogSource</fileType>
</file>
</fileSet>
<fileSet fileSetId="STIMULUS_FILESET">
<file>
<name>testbench.v</name>
<fileType>verilogSource</fileType>
</file>
</fileSet>
<fileSet fileSetId="COMPONENT_FILESET">
<file>
<name>..\common\CoreGPIO\CoreGPIO.cxf</name>
<fileType>CXF</fileType>
</file>
<file>
<name>..\common\CoreUARTapb\CoreUARTapb.cxf</name>
<fileType>CXF</fileType>
</file>
<file>
<name>..\common\CORE8051S\CORE8051S.cxf</name>
<fileType>CXF</fileType>
</file>
<file>
<name>..\common\CoreAPB3\CoreAPB3.cxf</name>
<fileType>CXF</fileType>
</file>
</fileSet>
</fileSets>
<model>
<signals>
<signal>
<name>RESETN</name>
<direction>out</direction>
</signal>
<signal>
<name>SYSCLK</name>
<direction>in</direction>
</signal>
<signal>
<name>NSYSRESET</name>
<direction>in</direction>
</signal>
<signal>
<name>GP_IN</name>
<direction>in</direction>
<left>15</left>
<right>0</right>
</signal>
<signal>
<name>GP_OUT</name>
<direction>out</direction>
<left>15</left>
<right>0</right>
</signal>
<signal>
<name>TX</name>
<direction>out</direction>
</signal>
<signal>
<name>RX</name>
<direction>in</direction>
</signal>
<signal>

<name>ExternalMemIf_MEMPSACKI</name>

<direction>in</direction>

</signal>

<signal>

<name>ExternalMemIf_MEMACKI</name>

<direction>in</direction>

</signal>

<signal>

<name>ExternalMemIf_MEMDATAI</name>

<direction>in</direction>

<left>7</left>

<right>0</right>

</signal>

<signal>

<name>ExternalMemIf_MEMDATAO</name>

<direction>out</direction>

<left>7</left>

<right>0</right>

</signal>

<signal>

<name>ExternalMemIf_MEMADDR</name>

<direction>out</direction>

<left>15</left>

<right>0</right>

</signal>

<signal>

<name>ExternalMemIf_MEMPSRD</name>

<direction>out</direction>

</signal>

<signal>

<name>ExternalMemIf_MEMWR</name>

<direction>out</direction>

</signal>

<signal>

<name>ExternalMemIf_MEMRD</name>

<direction>out</direction>

</signal>

</signals>
</model>
<busInterfaces>
<busInterface>

<name>ExternalMemIf</name>

<busType library="System" name="Core8051sExternalMemIf" vendor="Actel" version="1.0"/>

<master/>

<signalMap>

<signal>

<componentSignalName>ExternalMemIf_MEMPSACKI</componentSignalName>

<busSignalName>MEMPSACKI</busSignalName>

</signal>

<signal>

<componentSignalName>ExternalMemIf_MEMACKI</componentSignalName>

<busSignalName>MEMACKI</busSignalName>

</signal>

<signal>

<componentSignalName>ExternalMemIf_MEMDATAI</componentSignalName>

<busSignalName>MEMDATAI</busSignalName>

</signal>

<signal>

<componentSignalName>ExternalMemIf_MEMDATAO</componentSignalName>

<busSignalName>MEMDATAO</busSignalName>

</signal>

<signal>

<componentSignalName>ExternalMemIf_MEMADDR</componentSignalName>

<busSignalName>MEMADDR</busSignalName>

</signal>

<signal>

<componentSignalName>ExternalMemIf_MEMPSRD</componentSignalName>

<busSignalName>MEMPSRD</busSignalName>

</signal>

<signal>

<componentSignalName>ExternalMemIf_MEMWR</componentSignalName>

<busSignalName>MEMWR</busSignalName>

</signal>

<signal>

<componentSignalName>ExternalMemIf_MEMRD</componentSignalName>

<busSignalName>MEMRD</busSignalName>

</signal>

</signalMap>

</busInterface>

</busInterfaces>
<vendorExtension>
<design>
<hdltype>VERILOG</hdltype>
<device family="Fusion"/>
</design>
<type>CORECONSOLE</type>
</vendorExtension>
</component>
