<?xml version="1.0" encoding="UTF-8" standalone="no" ?><commonFiles xmlns="http://actel.com/sweng/afi"><AnalogSystemBuilder commonFileVersion="1.3"><file>C:\data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/assc.v</file><file>C:\data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/calibip_CLRAM.v</file><file>C:\data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/calibip_brentkung_24.v</file><file>C:\data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/calibip_compute_block.v</file><file>C:\data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/calibip_ram512x9_afs.v</file><file>C:\data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/calibip_ripple_24.v</file><file>C:\data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/calibip.v</file><file>G:\Data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/assc.v</file><file>G:\Data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/calibip_CLRAM.v</file><file>G:\Data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/calibip_brentkung_24.v</file><file>G:\Data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/calibip_compute_block.v</file><file>G:\Data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/calibip_ram512x9_afs.v</file><file>G:\Data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/calibip_ripple_24.v</file><file>G:\Data\Designs\ClosedLoopTrimDemo\smartgen\./common\/verilog/calibip.v</file></AnalogSystemBuilder><FlashMemorySystemBuilder commonFileVersion="1.1"><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\common/verilog/initcfg_xa.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\common/verilog/initcfg_xb.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\common/verilog/initcfg_xc.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\common/verilog/initcfg_xd.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\common/verilog/initcfg_xe.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\common/verilog/initcfg_xf.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\common/verilog/initcfg.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg_xa.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg_xb.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg_xc.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg_xd.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg_xe.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg_xf.v</file><file>C:/data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg.v</file><file>G:/Data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg_xa.v</file><file>G:/Data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg_xb.v</file><file>G:/Data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg_xc.v</file><file>G:/Data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg_xd.v</file><file>G:/Data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg_xe.v</file><file>G:/Data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg_xf.v</file><file>G:/Data/Designs/ClosedLoopTrimDemo/smartgen\./common/verilog/initcfg.v</file></FlashMemorySystemBuilder></commonFiles>