#add_file options
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/InternalOscillator/InternalOscillator.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/pll_main/pll_main.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/hdl/LowRippleDAC.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/alu.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/clkctrl.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/cpu.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/isr.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/memctrl.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/pmu.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/rstctrl.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/ramsfrctrl.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/oci.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/instrdec.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/main8051.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/core8051s_globs_fusion.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/RAM256X8.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/jtagfusion.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/jtag.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/debug.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/trace.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/trigger.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/ocia51.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/RAM256X20.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CORE8051S/rtl/verilog/o/core8051s.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CoreAPB3/rtl/verilog/o/MuxPtoB3.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CoreAPB3/rtl/verilog/o/CoreAPB3.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CoreGPIO/rtl/verilog/o/CoreGPIO.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CoreUARTapb/rtl/verilog/o/Clock_gen.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CoreUARTapb/rtl/verilog/o/Tx_async.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CoreUARTapb/rtl/verilog/o/Tx_sync.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CoreUARTapb/rtl/verilog/o/Rx_async.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CoreUARTapb/rtl/verilog/o/Rx_sync.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CoreUARTapb/rtl/verilog/o/fifo_256x8.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CoreUARTapb/rtl/verilog/o/UART.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/common/CoreUARTapb/rtl/verilog/o/CoreUARTapb.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/coreconsole/ProcessorSystem/ProcessorSystem.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/assc.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/AnalogSystem/AnalogSystem_assc_wrapper.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/AnalogSystem/AnalogSystem_assc_ram.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/calibip_ram512x9_afs.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/calibip_CLRAM.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/calibip_brentkung_24.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/calibip_ripple_24.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/calibip_compute_block.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/calibip.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/AnalogSystem/AnalogSystem_calibip_wrapper.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/AnalogSystem/AnalogSystem.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/initcfg_xa.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/initcfg_xb.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/initcfg_xc.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/initcfg_xd.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/initcfg_xe.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/initcfg_xf.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/common/verilog/initcfg.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/FlashMemorySystem/FlashMemorySystem_init_wrapper.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/smartgen/FlashMemorySystem/FlashMemorySystem.v"
add_file -verilog "C:/data/Designs/ClosedLoopTrimDemo/hdl/ClosedLoopTrimDemo.v"
set_option -top_module ClosedLoopTrimDemo

#device options
set_option -technology Fusion
set_option -part M7AFS600
set_option -vlog_std v2001




#implementation: "synthesis"
impl -add synthesis -type fpga

set_option -speed_grade -1
#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1
#map options
set_option -frequency 40.000
set_option -run_prop_extract 1
set_option -fanout_limit 12
set_option -globalthreshold 50
set_option -maxfan_hard 0
set_option -retiming 0
set_option -report_path 4000
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0

#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_format "edif"

#
#implementation attributes

impl -active "synthesis"
project -result_file "C:/data/Designs/ClosedLoopTrimDemo/synthesis/ClosedLoopTrimDemo.edn"
