#===========================================================
#
# syntax:
# -------
#
# memmap    resource_name base_address;
#
# write     width resource_name byte_offset data;
# read      width resource_name byte_offset;
# readcheck width resource_name byte_offset data;
#
#===========================================================

#-----------------------------------------------------------
# memory map
# define name and base address of each resource.
#-----------------------------------------------------------

memmap coregpio_00 0x00000400;
memmap coreuartapb_00 0x00000600;

#-----------------------------------------------------------
# Include resource scriptlets
#-----------------------------------------------------------

 
#-----------------------------------------------------------
# resource: coregpio
# instance: CoreGPIO_00
#-----------------------------------------------------------
# write 0x99 to coregpio register (aliased throughout the full apb slot) - e.g. use offset 0x74
write   b   CoreGPIO_00    0x74 0x99;

# read the coregpio register (from any location in slot) - e.g use offset 0x82
# don't know what this read value will be - depends on what is connected
# to coregpio inputs. if nothing connected, then it will read zz.
read    b   CoreGPIO_00    0x80;
 
#-----------------------------------------------------------
# resource: coreuartapb
# instance: CoreUARTapb_00
#-----------------------------------------------------------
# write 0x41 to uart control reg 1 - gives baud rate of 9600 bps assuming clk is 10 mhz
write   b   CoreUARTapb_00    0x08 0x41;

# write 0x06 to uart control reg 2 - 8 bits data, parity enabled, even parity
write   b   CoreUARTapb_00    0x0c 0x06;

read    b   CoreUARTapb_00    0x08;
readcheck b CoreUARTapb_00    0x0c 0x06; # expect value 06

# write 0x43 (ascii "c") to uart transmit register
write   b   CoreUARTapb_00    0x00 0x43;
