## WDOG

This section provides information on the WDOG Module Instance. Each of the module registers is described below.

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## WDOG Register Mapping Summary

### WDOG Common Register Mapping Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset
WDOG_REFRESH | RW | 32 | 0x00FF FFF0 | 0x000
WDOG_CONTROL | RW | 32 | 0x0000 0002 | 0x004
WDOG_STATUS | RW | 32 | 0x0000 0000 | 0x008
WDOG_TIME | RW | 32 | 0x00FF FFF0 | 0x00C
MSVP | RW | 32 | 0x0098 9680 | 0x010
TRIGGER | RW | 32 | 0x0000 03E8 | 0x014
FORCE | RW | 32 | 0x0000 0000 | 0x018

## WDOG Instances Mapping Summary

### WDOG : WDOG0_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
WDOG_REFRESH | RW | 32 | 0x00FF FFF0 | 0x000 | 0x2000 1000
WDOG_CONTROL | RW | 32 | 0x0000 0002 | 0x004 | 0x2000 1004
WDOG_STATUS | RW | 32 | 0x0000 0000 | 0x008 | 0x2000 1008
WDOG_TIME | RW | 32 | 0x00FF FFF0 | 0x00C | 0x2000 100C
MSVP | RW | 32 | 0x0098 9680 | 0x010 | 0x2000 1010
TRIGGER | RW | 32 | 0x0000 03E8 | 0x014 | 0x2000 1014
FORCE | RW | 32 | 0x0000 0000 | 0x018 | 0x2000 1018

### WDOG : WDOG1_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
WDOG_REFRESH | RW | 32 | 0x00FF FFF0 | 0x000 | 0x2010 1000
WDOG_CONTROL | RW | 32 | 0x0000 0002 | 0x004 | 0x2010 1004
WDOG_STATUS | RW | 32 | 0x0000 0000 | 0x008 | 0x2010 1008
WDOG_TIME | RW | 32 | 0x00FF FFF0 | 0x00C | 0x2010 100C
MSVP | RW | 32 | 0x0098 9680 | 0x010 | 0x2010 1010
TRIGGER | RW | 32 | 0x0000 03E8 | 0x014 | 0x2010 1014
FORCE | RW | 32 | 0x0000 0000 | 0x018 | 0x2010 1018

### WDOG : WDOG2_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
WDOG_REFRESH | RW | 32 | 0x00FF FFF0 | 0x000 | 0x2010 3000
WDOG_CONTROL | RW | 32 | 0x0000 0002 | 0x004 | 0x2010 3004
WDOG_STATUS | RW | 32 | 0x0000 0000 | 0x008 | 0x2010 3008
WDOG_TIME | RW | 32 | 0x00FF FFF0 | 0x00C | 0x2010 300C
MSVP | RW | 32 | 0x0098 9680 | 0x010 | 0x2010 3010
TRIGGER | RW | 32 | 0x0000 03E8 | 0x014 | 0x2010 3014
FORCE | RW | 32 | 0x0000 0000 | 0x018 | 0x2010 3018

### WDOG : WDOG3_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
WDOG_REFRESH | RW | 32 | 0x00FF FFF0 | 0x000 | 0x2010 5000
WDOG_CONTROL | RW | 32 | 0x0000 0002 | 0x004 | 0x2010 5004
WDOG_STATUS | RW | 32 | 0x0000 0000 | 0x008 | 0x2010 5008
WDOG_TIME | RW | 32 | 0x00FF FFF0 | 0x00C | 0x2010 500C
MSVP | RW | 32 | 0x0098 9680 | 0x010 | 0x2010 5010
TRIGGER | RW | 32 | 0x0000 03E8 | 0x014 | 0x2010 5014
FORCE | RW | 32 | 0x0000 0000 | 0x018 | 0x2010 5018

### WDOG : WDOG4_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
WDOG_REFRESH | RW | 32 | 0x00FF FFF0 | 0x000 | 0x2010 7000
WDOG_CONTROL | RW | 32 | 0x0000 0002 | 0x004 | 0x2010 7004
WDOG_STATUS | RW | 32 | 0x0000 0000 | 0x008 | 0x2010 7008
WDOG_TIME | RW | 32 | 0x00FF FFF0 | 0x00C | 0x2010 700C
MSVP | RW | 32 | 0x0098 9680 | 0x010 | 0x2010 7010
TRIGGER | RW | 32 | 0x0000 03E8 | 0x014 | 0x2010 7014
FORCE | RW | 32 | 0x0000 0000 | 0x018 | 0x2010 7018

### WDOG : WDOG0_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
WDOG_REFRESH | RW | 32 | 0x00FF FFF0 | 0x000 | 0x2800 1000
WDOG_CONTROL | RW | 32 | 0x0000 0002 | 0x004 | 0x2800 1004
WDOG_STATUS | RW | 32 | 0x0000 0000 | 0x008 | 0x2800 1008
WDOG_TIME | RW | 32 | 0x00FF FFF0 | 0x00C | 0x2800 100C
MSVP | RW | 32 | 0x0098 9680 | 0x010 | 0x2800 1010
TRIGGER | RW | 32 | 0x0000 03E8 | 0x014 | 0x2800 1014
FORCE | RW | 32 | 0x0000 0000 | 0x018 | 0x2800 1018

### WDOG : WDOG1_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
WDOG_REFRESH | RW | 32 | 0x00FF FFF0 | 0x000 | 0x2810 1000
WDOG_CONTROL | RW | 32 | 0x0000 0002 | 0x004 | 0x2810 1004
WDOG_STATUS | RW | 32 | 0x0000 0000 | 0x008 | 0x2810 1008
WDOG_TIME | RW | 32 | 0x00FF FFF0 | 0x00C | 0x2810 100C
MSVP | RW | 32 | 0x0098 9680 | 0x010 | 0x2810 1010
TRIGGER | RW | 32 | 0x0000 03E8 | 0x014 | 0x2810 1014
FORCE | RW | 32 | 0x0000 0000 | 0x018 | 0x2810 1018

### WDOG : WDOG2_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
WDOG_REFRESH | RW | 32 | 0x00FF FFF0 | 0x000 | 0x2810 3000
WDOG_CONTROL | RW | 32 | 0x0000 0002 | 0x004 | 0x2810 3004
WDOG_STATUS | RW | 32 | 0x0000 0000 | 0x008 | 0x2810 3008
WDOG_TIME | RW | 32 | 0x00FF FFF0 | 0x00C | 0x2810 300C
MSVP | RW | 32 | 0x0098 9680 | 0x010 | 0x2810 3010
TRIGGER | RW | 32 | 0x0000 03E8 | 0x014 | 0x2810 3014
FORCE | RW | 32 | 0x0000 0000 | 0x018 | 0x2810 3018

### WDOG : WDOG3_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
WDOG_REFRESH | RW | 32 | 0x00FF FFF0 | 0x000 | 0x2810 5000
WDOG_CONTROL | RW | 32 | 0x0000 0002 | 0x004 | 0x2810 5004
WDOG_STATUS | RW | 32 | 0x0000 0000 | 0x008 | 0x2810 5008
WDOG_TIME | RW | 32 | 0x00FF FFF0 | 0x00C | 0x2810 500C
MSVP | RW | 32 | 0x0098 9680 | 0x010 | 0x2810 5010
TRIGGER | RW | 32 | 0x0000 03E8 | 0x014 | 0x2810 5014
FORCE | RW | 32 | 0x0000 0000 | 0x018 | 0x2810 5018

### WDOG : WDOG4_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
WDOG_REFRESH | RW | 32 | 0x00FF FFF0 | 0x000 | 0x2810 7000
WDOG_CONTROL | RW | 32 | 0x0000 0002 | 0x004 | 0x2810 7004
WDOG_STATUS | RW | 32 | 0x0000 0000 | 0x008 | 0x2810 7008
WDOG_TIME | RW | 32 | 0x00FF FFF0 | 0x00C | 0x2810 700C
MSVP | RW | 32 | 0x0098 9680 | 0x010 | 0x2810 7010
TRIGGER | RW | 32 | 0x0000 03E8 | 0x014 | 0x2810 7014
FORCE | RW | 32 | 0x0000 0000 | 0x018 | 0x2810 7018

## WDOG Register Descriptions

### WDOG : WDOG_REFRESH

Address offset | 0x000
Physical address | 0x2000 1000 | Instance | WDOG0_LO
| 0x2010 1000 |  | WDOG1_LO
| 0x2010 3000 |  | WDOG2_LO
| 0x2010 5000 |  | WDOG3_LO
| 0x2010 7000 |  | WDOG4_LO
| 0x2800 1000 |  | WDOG0_HI
| 0x2810 1000 |  | WDOG1_HI
| 0x2810 3000 |  | WDOG2_HI
| 0x2810 5000 |  | WDOG3_HI
| 0x2810 7000 |  | WDOG4_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | WDOGREFRESH | Writing pwdata=0xdeadc0de resets the watchdog timer to start counting down again when in the permitted refresh window. Writes of any other value will have no effect whilst in the permitted refresh window. Reads return the current timer value. A write to this will start the watchdog once started the watchdog cannot be stopped. | RW | 0x00FF FFF0

### WDOG : WDOG_CONTROL

Address offset | 0x004
Physical address | 0x2000 1004 | Instance | WDOG0_LO
| 0x2010 1004 |  | WDOG1_LO
| 0x2010 3004 |  | WDOG2_LO
| 0x2010 5004 |  | WDOG3_LO
| 0x2010 7004 |  | WDOG4_LO
| 0x2800 1004 |  | WDOG0_HI
| 0x2810 1004 |  | WDOG1_HI
| 0x2810 3004 |  | WDOG2_HI
| 0x2810 5004 |  | WDOG3_HI
| 0x2810 7004 |  | WDOG4_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | Reserved |  | RW | 0x000 0000
4 | ENABLE_FORBIDDEN | When set if a write occurs in the forbidden region the watchdog will trigger | RW | 0
3 | ACTIVE_SLEEP | When set the watchdog is operational, when the CPU is sleeping. | RW | 0
2 | INTEN_SLEEP | Enables the MVRP interrupt when the MVRP level is passed and the M3 is sleeping | RW | 0
1 | INTEN_TRIG | Enables the NMI interrupt when the TRIGGER level is passed. NOTE: This bit is permanently set and cannot be changed. | RW | 1
0 | INTEN_MSVP | Enables the MVRP interrupt when the MVRP level is passed | RW | 0

### WDOG : WDOG_STATUS

Address offset | 0x008
Physical address | 0x2000 1008 | Instance | WDOG0_LO
| 0x2010 1008 |  | WDOG1_LO
| 0x2010 3008 |  | WDOG2_LO
| 0x2010 5008 |  | WDOG3_LO
| 0x2010 7008 |  | WDOG4_LO
| 0x2800 1008 |  | WDOG0_HI
| 0x2810 1008 |  | WDOG1_HI
| 0x2810 3008 |  | WDOG2_HI
| 0x2810 5008 |  | WDOG3_HI
| 0x2810 7008 |  | WDOG4_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved |  | RO | 0x000 0000
5 | DEVRST | Indicates that the DEVRST caused the NMI. Will be cleared when the system resets | RO | 0
4 | LOCKED | Indicates that the following three registers are locked and cannot be changed | RO | 0
3 | TRIGGERED | Indicates that the watchdog has triggered. Will be cleared when the system resets | RO | 0
2 | FORBIDDEN | Indicates that the watchdog is currently in the forbidden range | RO | 0
1 | WDOG_TRIPPED | Indicates that the TRIGGER level has passed and that the NMI is asserted, Cleared by writing a '1' | RW W1toClr: WDOG_STATUS.MVRP_TRIPPED | 0
0 | MVRP_TRIPPED | Indicates that the MVRP level has passed. Cleared by writing a '1' | RW W1toClr: WDOG_STATUS.WDOG_TRIPPED | 0

### WDOG : WDOG_TIME

Address offset | 0x00C
Physical address | 0x2000 100C | Instance | WDOG0_LO
| 0x2010 100C |  | WDOG1_LO
| 0x2010 300C |  | WDOG2_LO
| 0x2010 500C |  | WDOG3_LO
| 0x2010 700C |  | WDOG4_LO
| 0x2800 100C |  | WDOG0_HI
| 0x2810 100C |  | WDOG1_HI
| 0x2810 300C |  | WDOG2_HI
| 0x2810 500C |  | WDOG3_HI
| 0x2810 700C |  | WDOG4_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | Reserved |  | RO | 0x00
23:0 | WDOGTIME | Sets the watchdog time value. Once written locks this and the following two registers | RW | 0xFF FFF0

### WDOG : MSVP

Address offset | 0x010
Physical address | 0x2000 1010 | Instance | WDOG0_LO
| 0x2010 1010 |  | WDOG1_LO
| 0x2010 3010 |  | WDOG2_LO
| 0x2010 5010 |  | WDOG3_LO
| 0x2010 7010 |  | WDOG4_LO
| 0x2800 1010 |  | WDOG0_HI
| 0x2810 1010 |  | WDOG1_HI
| 0x2810 3010 |  | WDOG2_HI
| 0x2810 5010 |  | WDOG3_HI
| 0x2810 7010 |  | WDOG4_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | Reserved |  | RO | 0x00
23:0 | WDOGMVRP | Sets the watchdog MVRP value. | RW | 0x98 9680

### WDOG : TRIGGER

Address offset | 0x014
Physical address | 0x2000 1014 | Instance | WDOG0_LO
| 0x2010 1014 |  | WDOG1_LO
| 0x2010 3014 |  | WDOG2_LO
| 0x2010 5014 |  | WDOG3_LO
| 0x2010 7014 |  | WDOG4_LO
| 0x2800 1014 |  | WDOG0_HI
| 0x2810 1014 |  | WDOG1_HI
| 0x2810 3014 |  | WDOG2_HI
| 0x2810 5014 |  | WDOG3_HI
| 0x2810 7014 |  | WDOG4_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved |  | RW | 0x0 0000
11:0 | WDOGTRIG | Sets the watchdog trigger value, 0-4095 u seconds | RW | 0x3E8

### WDOG : FORCE

Address offset | 0x018
Physical address | 0x2000 1018 | Instance | WDOG0_LO
| 0x2010 1018 |  | WDOG1_LO
| 0x2010 3018 |  | WDOG2_LO
| 0x2010 5018 |  | WDOG3_LO
| 0x2010 7018 |  | WDOG4_LO
| 0x2800 1018 |  | WDOG0_HI
| 0x2810 1018 |  | WDOG1_HI
| 0x2810 3018 |  | WDOG2_HI
| 0x2810 5018 |  | WDOG3_HI
| 0x2810 7018 |  | WDOG4_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved |  | RO | 0x0000
15:0 | WDOGVALUE | If the watchdog has triggered writing 0x0c will cause an immediate reset, any other value or write at other times will trigger the watchdog NMI sequence. | WO | 0x0000

WDOG has no common memories.