## IOSCB_BANK_CTLR

This section provides information on the IOSCB_BANK_CTLR Module Instance. Each of the module registers is described below.

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## IOSCB_BANK_CTLR Register Mapping Summary

### IOSCB_BANK_CTLR Common Register Mapping Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000
DPC_BITS | RW | 32 | 0x0000 0000 | 0x004
BANK_STATUS | RO | 32 | 0x0000 0000 | 0x008

## IOSCB_BANK_CTLR Instances Mapping Summary

### IOSCB_BANK_CTLR : bank_ctlr_9_sei Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0B00 1000
DPC_BITS | RW | 32 | 0x0000 0000 | 0x004 | 0x0B00 1004
BANK_STATUS | RO | 32 | 0x0000 0000 | 0x008 | 0x0B00 1008

### IOSCB_BANK_CTLR : bank_ctlr_0_nwi Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0B00 2000
DPC_BITS | RW | 32 | 0x0000 0000 | 0x004 | 0x0B00 2004
BANK_STATUS | RO | 32 | 0x0000 0000 | 0x008 | 0x0B00 2008

### IOSCB_BANK_CTLR : bank_ctlr_7_wi Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0B00 4000
DPC_BITS | RW | 32 | 0x0000 0000 | 0x004 | 0x0B00 4004
BANK_STATUS | RO | 32 | 0x0000 0000 | 0x008 | 0x0B00 4008

### IOSCB_BANK_CTLR : bank_ctlr_8_nei Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0B00 8000
DPC_BITS | RW | 32 | 0x0000 0000 | 0x004 | 0x0B00 8004
BANK_STATUS | RO | 32 | 0x0000 0000 | 0x008 | 0x0B00 8008

### IOSCB_BANK_CTLR : vref_gen_serdes_pma Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0B02 0000
DPC_BITS | RW | 32 | 0x0000 0000 | 0x004 | 0x0B02 0004
BANK_STATUS | RO | 32 | 0x0000 0000 | 0x008 | 0x0B02 0008

### IOSCB_BANK_CTLR : bank_ctlr_0_nec Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0B04 0000
DPC_BITS | RW | 32 | 0x0000 0000 | 0x004 | 0x0B04 0004
BANK_STATUS | RO | 32 | 0x0000 0000 | 0x008 | 0x0B04 0008

### IOSCB_BANK_CTLR : bank_ctlr_1_swc Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0B40 0000
DPC_BITS | RW | 32 | 0x0000 0000 | 0x004 | 0x0B40 0004
BANK_STATUS | RO | 32 | 0x0000 0000 | 0x008 | 0x0B40 0008

## IOSCB_BANK_CTLR Register Descriptions

### IOSCB_BANK_CTLR : SOFT_RESET

Address offset | 0x000
Physical address | 0x0B00 4000 | Instance | bank_ctlr_7_wi
| 0x0B00 1000 |  | bank_ctlr_9_sei
| 0x0B40 0000 |  | bank_ctlr_1_swc
| 0x0B04 0000 |  | bank_ctlr_0_nec
| 0x0B02 0000 |  | vref_gen_serdes_pma
| 0x0B00 2000 |  | bank_ctlr_0_nwi
| 0x0B00 8000 |  | bank_ctlr_8_nei
Description | This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | BLOCKID | This returns the block type and chip location. (IO SCB bus only) | RO | 0x0000
|  | Read 0x0000 | [block_address_IOSCB_BANK_CTLR] |  |
15:9 | Reserved |  | RO Rreturns0s | 0x00
8 | PERIPH | This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0. | WO | 0
|  | Write 0 | [scb_periph_not_in_soft_reset_IOSCB_BANK_CTLR] |  |
|  | Write 1 | [scb_periph_reset_IOSCB_BANK_CTLR] |  |
7:2 | Reserved |  | RO Rreturns0s | 0x00
1 | V_MAP | This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit | WO | 0
|  | Write 0 | [scb_v_regs_not_in_soft_reset_IOSCB_BANK_CTLR] |  |
|  | Write 1 | [scb_v_regs_reset_IOSCB_BANK_CTLR] |  |
0 | NV_MAP | This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit | WO | 0
|  | Write 0 | [scb_nv_regs_not_in_soft_reset_IOSCB_BANK_CTLR] |  |
|  | Write 1 | [scb_nv_regs_reset_IOSCB_BANK_CTLR] |  |

### IOSCB_BANK_CTLR : DPC_BITS

Address offset | 0x004
Physical address | 0x0B00 4004 | Instance | bank_ctlr_7_wi
| 0x0B00 1004 |  | bank_ctlr_9_sei
| 0x0B40 0004 |  | bank_ctlr_1_swc
| 0x0B04 0004 |  | bank_ctlr_0_nec
| 0x0B02 0004 |  | vref_gen_serdes_pma
| 0x0B00 2004 |  | bank_ctlr_0_nwi
| 0x0B00 8004 |  | bank_ctlr_8_nei
Description | DPC Bits Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved |  | RO | 0x0 0000
11 | dpc_move_en | enable dynamic control of vrgen circuit | RW | 0
10 | dpc_vrgen_en | enable vref generator | RW | 0
9:4 | dpc_vrgen | reference voltage ratio setting | RW | 0x00
3:0 | dpc_vs | bank voltage select for pvt calibration | RW | 0x0

### IOSCB_BANK_CTLR : BANK_STATUS

Address offset | 0x008
Physical address | 0x0B00 4008 | Instance | bank_ctlr_7_wi
| 0x0B00 1008 |  | bank_ctlr_9_sei
| 0x0B40 0008 |  | bank_ctlr_1_swc
| 0x0B04 0008 |  | bank_ctlr_0_nec
| 0x0B02 0008 |  | vref_gen_serdes_pma
| 0x0B00 2008 |  | bank_ctlr_0_nwi
| 0x0B00 8008 |  | bank_ctlr_8_nei
Description | Bank Complete Registers
Type | RO

Bits | Field Name | Description | Type | Reset
31:2 | Reserved |  | RO Rreturns0s | 0x0000 0000
1 | sro_ioen_bnk_b | Bank power on complete (active low for polling) | RO | 0
0 | sro_calib_status_b | Bank calibration complete (active low for polling) | RO | 0

IOSCB_BANK_CTLR has no common memories.