# ENVM Register Descriptions

This document presents a summary of the register interfaces for the ENVM product. Each module instance in the design is presented, together with its associated register map and bitfield definitions.

## ENVM

Auto-generated by Socrates-Bitwise 1.13
Generation timestamp: 2022-09-30 09:52:15

This section provides information on the ENVM Module Instance. Each of the module registers is described below.

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## ENVM Register Mapping Summary

### Common Register Mapping Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset
ENVM_Control_register | RW | 32 | 0x4005 000F | 0x000
ENVM_Power_control_register | RW | 32 | 0x0000 007F | 0x004

## ENVM Register Descriptions

### ENVM : ENVM_Control_register

Address offset | 0x000
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | timer | Sets the duration of the timer used to detect a non-response of slow response from the ENVM on C and R bus accesses. Timer Duration = (Value+1) * (128 * AHB Clock Period) 0x00: Timer disabled. If the timer expires the AHB cycle is terminates using the HRESP protocol. The time should be set. | RW | 0x40
23:19 | Reserved |  | RO Rreturns0s | 0x00
18 | interrupt_enable | Enable the ENVM interrupt | RW | 1
17 | slowread | When '1' the controller will initiate separate ENVM reads for all reads. No buffering or speculative operations will be carried out. When performing word reads incrementing through ENVM each location will be read twice | RW | 0
16 | readahead | Enables "readahead" on the ENVM controller. The controller will automatically read the next ENVM location as soon as possible ahead of the AHB request. This will improve read performance when incrementing though memory as the NVM reads and AHB cycles are pipelined. When set non incrementing accesses will take longer as the controller may be in the process of reading the next address and the ENVM cycle needs to complete prior to starting the required read | RW | 1
15:10 | Reserved |  | RO Rreturns0s | 0x00
9 | clock_suppress | When set suppresses clock edge between C-Bus access cycles so that they appear as consecutive access cycles. | RW | 0
8 | clock_continuous | When '1' the ENVM clock will be always generated, and not stopped between access cycles. Setting this will increase access latency but mean that the ENVM clock operates at a stable rate. | RW | 0
7:6 | Reserved |  | RO Rreturns0s | 0x0
5:0 | clock_period | Sets the number of AHB cycles used to generate the ENVM clock, Clock period = (Value+1) * 2.5ns (AHB clock at 400MHz). Value must be 1 to 63 (0 defaults to 15) e.g.15 will generate a 40ns period if the AHB clock is 400MHz | RW | 0x0F

### ENVM : ENVM_Power_control_register

Address offset | 0x004
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | Reserved |  | RO Rreturns0s | 0x00 0000
8 | override | Use the ENVM_CR here rather than the SYSREG one | RW | 0
7 | Reserved |  | RO Rreturns0s | 0
6 | sleep | sleep | RW | 1
5 | iso | iso (isolate) | RW | 1
4 | pd4 | pd4 (powerdown) | RW | 1
3 | pd3 | pd3 (powerdown) | RW | 1
2 | pd2 | pd2 (powerdown) | RW | 1
1 | pd1 | pd1 (powerdown) | RW | 1
0 | reset | reset | RW | 1

ENVM has no common memories.