## IOSCB_BANK_CTRL_DDR

This section provides information on the IOSCB_BANK_CTRL_DDR Module Instance. Each of the module registers is described below.

Return to mpfs_ioscb_memmap_dri

## IOSCB_BANK_CTRL_DDR Register Mapping Summary

### bc_ddr Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x0 | 0x0E02 0000
DPC_BITS | RW | 32 | 0x0000 0000 | 0x4 | 0x0E02 0004
BANK_STATUS | RO | 32 | 0x0000 0000 | 0x8 | 0x0E02 0008

## IOSCB_BANK_CTRL_DDR Register Descriptions

### IOSCB_BANK_CTRL_DDR : SOFT_RESET

Address offset | 0x0
Physical address | 0x0E02 0000 | Instance | bc_ddr
Description | This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | BLOCKID | This returns the block type and chip location. (IO SCB bus only) | RO | 0x0000
|  | Read 0x0000 | [block_address_IOSCB_BANK_CTRL_DDR] |  |
15:9 | Reserved |  | RO Rreturns0s | 0x00
8 | PERIPH | This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0. | WO | 0
|  | Write 0 | [scb_periph_not_in_soft_reset_IOSCB_BANK_CTRL_DDR] |  |
|  | Write 1 | [scb_periph_reset_IOSCB_BANK_CTRL_DDR] |  |
7:2 | Reserved |  | RO Rreturns0s | 0x00
1 | V_MAP | This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit | WO | 0
|  | Write 0 | [scb_v_regs_not_in_soft_reset_IOSCB_BANK_CTRL_DDR] |  |
|  | Write 1 | [scb_v_regs_reset_IOSCB_BANK_CTRL_DDR] |  |
0 | NV_MAP | This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit | WO | 0
|  | Write 0 | [scb_nv_regs_not_in_soft_reset_IOSCB_BANK_CTRL_DDR] |  |
|  | Write 1 | [scb_nv_regs_reset_IOSCB_BANK_CTRL_DDR] |  |

### IOSCB_BANK_CTRL_DDR : DPC_BITS

Address offset | 0x4
Physical address | 0x0E02 0004 | Instance | bc_ddr
Description | DPC Bits Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:20 | Reserved |  | RO | 0x000
19 | dpc_move_en_v | enable dynamic control of vrgen circuit for ADDCMD pins | RW | 0
18 | dpc_vrgen_en_v | enable vref generator for ADDCMD pins | RW | 0
17:12 | dpc_vrgen_v | reference voltage ratio setting for ADDCMD pins | RW | 0x00
11 | dpc_move_en_h | enable dynamic control of vrgen circuit for DQ/DQS pins | RW | 0
10 | dpc_vrgen_en_h | enable vref generator for DQ/DQS pins | RW | 0
9:4 | dpc_vrgen_h | reference voltage ratio setting for DQ/DQS pins | RW | 0x00
3:0 | dpc_vs | bank voltage select for pvt calibration | RW | 0x0

### IOSCB_BANK_CTRL_DDR : BANK_STATUS

Address offset | 0x8
Physical address | 0x0E02 0008 | Instance | bc_ddr
Description | Bank Complete Registers
Type | RO

Bits | Field Name | Description | Type | Reset
31:2 | Reserved |  | RO Rreturns0s | 0x0000 0000
1 | sro_ioen_bnk_b | Bank power on complete (active low for polling) | RO | 0
0 | sro_calib_status_b | Bank calibration complete (active low for polling) | RO | 0

IOSCB_BANK_CTRL_DDR has no common memories.