## MSTIMER

This section provides information on the MSTIMER Module Instance. Each of the module registers is described below.

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## MSTIMER Register Mapping Summary

### MSTIMER Common Register Mapping Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset
TIM1VALUE | RO | 32 | 0x0000 0000 | 0x000
TIM1LOADVAL | RW | 32 | 0x0000 0000 | 0x004
TIM1BGLOADVAL | RW | 32 | 0x0000 0000 | 0x008
TIM1CONTROL | RW | 32 | 0x0000 0000 | 0x00C
TIM1RIS | RW | 32 | 0x0000 0000 | 0x010
TIM1MIS | RO | 32 | 0x0000 0000 | 0x014
TIM2VALUE | RO | 32 | 0x0000 0000 | 0x018
TIM2LOADVAL | RW | 32 | 0x0000 0000 | 0x01C
TIM2BGLOADVAL | RW | 32 | 0x0000 0000 | 0x020
TIM2CONTROL | RW | 32 | 0x0000 0000 | 0x024
TIM2RIS | RW | 32 | 0x0000 0000 | 0x028
TIM2MIS | RO | 32 | 0x0000 0000 | 0x02C
TIM64VALUEU | RO | 32 | 0x0000 0000 | 0x030
TIM64VALUEL | RO | 32 | 0x0000 0000 | 0x034
TIM64LOADVALU | RW | 32 | 0x0000 0000 | 0x038
TIM64LOADVALL | RW | 32 | 0x0000 0000 | 0x03C
TIM64BGLOADVALU | RW | 32 | 0x0000 0000 | 0x040
TIM64BGLOADVALL | RW | 32 | 0x0000 0000 | 0x044
TIM64CONTROL | RW | 32 | 0x0000 0000 | 0x048
TIM64RIS | RW | 32 | 0x0000 0000 | 0x04C
TIM64MIS | RO | 32 | 0x0000 0000 | 0x050
TIM64MODE | RW | 32 | 0x0000 0000 | 0x054

## MSTIMER Instances Mapping Summary

### MSTIMER : MSTIMER_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
TIM1VALUE | RO | 32 | 0x0000 0000 | 0x000 | 0x2012 5000
TIM1LOADVAL | RW | 32 | 0x0000 0000 | 0x004 | 0x2012 5004
TIM1BGLOADVAL | RW | 32 | 0x0000 0000 | 0x008 | 0x2012 5008
TIM1CONTROL | RW | 32 | 0x0000 0000 | 0x00C | 0x2012 500C
TIM1RIS | RW | 32 | 0x0000 0000 | 0x010 | 0x2012 5010
TIM1MIS | RO | 32 | 0x0000 0000 | 0x014 | 0x2012 5014
TIM2VALUE | RO | 32 | 0x0000 0000 | 0x018 | 0x2012 5018
TIM2LOADVAL | RW | 32 | 0x0000 0000 | 0x01C | 0x2012 501C
TIM2BGLOADVAL | RW | 32 | 0x0000 0000 | 0x020 | 0x2012 5020
TIM2CONTROL | RW | 32 | 0x0000 0000 | 0x024 | 0x2012 5024
TIM2RIS | RW | 32 | 0x0000 0000 | 0x028 | 0x2012 5028
TIM2MIS | RO | 32 | 0x0000 0000 | 0x02C | 0x2012 502C
TIM64VALUEU | RO | 32 | 0x0000 0000 | 0x030 | 0x2012 5030
TIM64VALUEL | RO | 32 | 0x0000 0000 | 0x034 | 0x2012 5034
TIM64LOADVALU | RW | 32 | 0x0000 0000 | 0x038 | 0x2012 5038
TIM64LOADVALL | RW | 32 | 0x0000 0000 | 0x03C | 0x2012 503C
TIM64BGLOADVALU | RW | 32 | 0x0000 0000 | 0x040 | 0x2012 5040
TIM64BGLOADVALL | RW | 32 | 0x0000 0000 | 0x044 | 0x2012 5044
TIM64CONTROL | RW | 32 | 0x0000 0000 | 0x048 | 0x2012 5048
TIM64RIS | RW | 32 | 0x0000 0000 | 0x04C | 0x2012 504C
TIM64MIS | RO | 32 | 0x0000 0000 | 0x050 | 0x2012 5050
TIM64MODE | RW | 32 | 0x0000 0000 | 0x054 | 0x2012 5054

### MSTIMER : MSTIMER_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
TIM1VALUE | RO | 32 | 0x0000 0000 | 0x000 | 0x2812 5000
TIM1LOADVAL | RW | 32 | 0x0000 0000 | 0x004 | 0x2812 5004
TIM1BGLOADVAL | RW | 32 | 0x0000 0000 | 0x008 | 0x2812 5008
TIM1CONTROL | RW | 32 | 0x0000 0000 | 0x00C | 0x2812 500C
TIM1RIS | RW | 32 | 0x0000 0000 | 0x010 | 0x2812 5010
TIM1MIS | RO | 32 | 0x0000 0000 | 0x014 | 0x2812 5014
TIM2VALUE | RO | 32 | 0x0000 0000 | 0x018 | 0x2812 5018
TIM2LOADVAL | RW | 32 | 0x0000 0000 | 0x01C | 0x2812 501C
TIM2BGLOADVAL | RW | 32 | 0x0000 0000 | 0x020 | 0x2812 5020
TIM2CONTROL | RW | 32 | 0x0000 0000 | 0x024 | 0x2812 5024
TIM2RIS | RW | 32 | 0x0000 0000 | 0x028 | 0x2812 5028
TIM2MIS | RO | 32 | 0x0000 0000 | 0x02C | 0x2812 502C
TIM64VALUEU | RO | 32 | 0x0000 0000 | 0x030 | 0x2812 5030
TIM64VALUEL | RO | 32 | 0x0000 0000 | 0x034 | 0x2812 5034
TIM64LOADVALU | RW | 32 | 0x0000 0000 | 0x038 | 0x2812 5038
TIM64LOADVALL | RW | 32 | 0x0000 0000 | 0x03C | 0x2812 503C
TIM64BGLOADVALU | RW | 32 | 0x0000 0000 | 0x040 | 0x2812 5040
TIM64BGLOADVALL | RW | 32 | 0x0000 0000 | 0x044 | 0x2812 5044
TIM64CONTROL | RW | 32 | 0x0000 0000 | 0x048 | 0x2812 5048
TIM64RIS | RW | 32 | 0x0000 0000 | 0x04C | 0x2812 504C
TIM64MIS | RO | 32 | 0x0000 0000 | 0x050 | 0x2812 5050
TIM64MODE | RW | 32 | 0x0000 0000 | 0x054 | 0x2812 5054

## MSTIMER Register Descriptions

### MSTIMER : TIM1VALUE

Address offset | 0x000
Physical address | 0x2012 5000 | Instance | MSTIMER_LO
| 0x2812 5000 |  | MSTIMER_HI
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TIM1VALUE | Current value of timer 1. This register is read only. Writing to this register has no effect. | RO | 0x0000 0000

### MSTIMER : TIM1LOADVAL

Address offset | 0x004
Physical address | 0x2012 5004 | Instance | MSTIMER_LO
| 0x2812 5004 |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TIM1LOADVAL | Load value for timer 1. Write has no effect when timer is in 64 bit mode. Reading this register in 64 bit mode returns the reset value.When this register is written to, the value written is immediately loaded into the counter. This applies in both periodic and one-shot mode. If enabled, the counter will then continue counting down from this value. The value stored in this register is also used to reload the counter when the count reaches zero and the counter is operating in periodic mode. This register will be overwritten if the TIM1BGLOADVAL register is written to but the counter will not be updated with the new value in this case.TIM1LOADVAL always stores the value which will be loaded into the counter when it next reaches zero and periodic mode is selected. | RW | 0x0000 0000

### MSTIMER : TIM1BGLOADVAL

Address offset | 0x008
Physical address | 0x2012 5008 | Instance | MSTIMER_LO
| 0x2812 5008 |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TIM1BGLOADVAL | Background load value for timer 1. Write has no effect when timer is in 64 bit mode.Reading this register in 64 bit mode returns the reset value. Background load value for timer 1. When this register is written to, the value written is loaded into the TIM1LOADVAL register without updating the counter itself. This allows a new load value to be put in place for the counter without interrupting the current count cycle. | RW | 0x0000 0000

### MSTIMER : TIM1CONTROL

Address offset | 0x00C
Physical address | 0x2012 500C | Instance | MSTIMER_LO
| 0x2812 500C |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved |  | RO Rreturns0s | 0x0000 0000
2 | TIM1INTEN | Timer 1 interrupt enable bit. 0 = timer 1 interrupt disabled. 1 = timer 1 interrupt enabled. | RW | 0
1 | TIM1MODE | This bit sets the operating mode for timer 1. 0= periodic mode. 1=one-shot mode. | RW | 0
0 | TIM1ENABLE | Enable bit for timer 1: 0 = timer 1 disabled, i.e. counter decrements 1 = timer 1 enabled, i.e. counter value is static | RW | 0

### MSTIMER : TIM1RIS

Address offset | 0x010
Physical address | 0x2012 5010 | Instance | MSTIMER_LO
| 0x2812 5010 |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved |  | RO Rreturns0s | 0x0000 0000
0 | TIM1RIS | Raw interrupt status bit for timer 1. This is bit is set when timer 1 reaches zero. Writing a '1' to this bit clears the bit. Writing '0' has no effect. | RW | 0

### MSTIMER : TIM1MIS

Address offset | 0x014
Physical address | 0x2012 5014 | Instance | MSTIMER_LO
| 0x2812 5014 |  | MSTIMER_HI
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved |  | RO Rreturns0s | 0x0000 0000
0 | TIM1MIS | Masked interrupt status bit for timer 1. This read only bit is the logical AND of the TIM1RIS and TIM1INTEN bits. The TIMER1INT output from the timer will have the same value as this bit. Writing to this bit has no effect. | RO | 0

### MSTIMER : TIM2VALUE

Address offset | 0x018
Physical address | 0x2012 5018 | Instance | MSTIMER_LO
| 0x2812 5018 |  | MSTIMER_HI
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TIM2VALUE | This read only register contains the current value of timer 2. Writing to this register has no effect. | RO | 0x0000 0000

### MSTIMER : TIM2LOADVAL

Address offset | 0x01C
Physical address | 0x2012 501C | Instance | MSTIMER_LO
| 0x2812 501C |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TIM2LOADVAL | Load value for timer 2. | RW | 0x0000 0000

### MSTIMER : TIM2BGLOADVAL

Address offset | 0x020
Physical address | 0x2012 5020 | Instance | MSTIMER_LO
| 0x2812 5020 |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TIM2BGLOADVAL | Background load value for timer 2. When this register is written to, the value written is loaded into the TIM2LOADVAL register without updating the counter itself. This allows a new load value to be put in place for the counter without interrupting the current count cycle. | RW | 0x0000 0000

### MSTIMER : TIM2CONTROL

Address offset | 0x024
Physical address | 0x2012 5024 | Instance | MSTIMER_LO
| 0x2812 5024 |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved |  | RO Rreturns0s | 0x0000 0000
2 | TIM2INTEN | Timer 2 interrupt enable bit. 0 = timer 2 interrupt disabled. 1 = timer 2 interrupt enabled. | RW | 0
1 | TIM2MODE | This bit sets the operating mode for timer 2. 0=periodic mode, and 1= one-shot mode. | RW | 0
0 | TIM2ENABLE | Enable bit for timer 2: 0 = timer 2 disabled, i.e. counter decrements, 1 = timer 2 enabled, i.e. counter value is static. | RW | 0

### MSTIMER : TIM2RIS

Address offset | 0x028
Physical address | 0x2012 5028 | Instance | MSTIMER_LO
| 0x2812 5028 |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved |  | RO Rreturns0s | 0x0000 0000
0 | TIM2RIS | Raw interrupt status bit for timer 2. This is bit is set when timer 2 reaches zero. Writing a '1' to this bit clears the bit. Writing '0' has no effect. | RW | 0

### MSTIMER : TIM2MIS

Address offset | 0x02C
Physical address | 0x2012 502C | Instance | MSTIMER_LO
| 0x2812 502C |  | MSTIMER_HI
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved |  | RO Rreturns0s | 0x0000 0000
0 | TIM2MIS | Masked interrupt status bit for timer 2. This read only bit is the logical AND of the TIM2RIS and TIM2INTEN bits.The TIMER2INT output from the timer will have the same value as this bit. Writing to this bit has no effect. | RO | 0

### MSTIMER : TIM64VALUEU

Address offset | 0x030
Physical address | 0x2012 5030 | Instance | MSTIMER_LO
| 0x2812 5030 |  | MSTIMER_HI
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TIM64VALUEU | This read only register contains the current value of the upper 32 bit word of the 64 bit timer. Reading this register returns the value of : TIM64TEMPVALU which is set when the lower 32 bits of the 64-bit timer is read.Writing to this register has no effect. | RO | 0x0000 0000

### MSTIMER : TIM64VALUEL

Address offset | 0x034
Physical address | 0x2012 5034 | Instance | MSTIMER_LO
| 0x2812 5034 |  | MSTIMER_HI
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TIM64VALUEL | This read only register contains the current value of the lower 32 bit word of the 64 bit timer. Reading this register has the side effect of storing the upper 32 bits of the counter value in TIMTEMPVALU, which is accessed when the TIM64VALUEU register is read. Writing to this register has no effect. | RO | 0x0000 0000

### MSTIMER : TIM64LOADVALU

Address offset | 0x038
Physical address | 0x2012 5038 | Instance | MSTIMER_LO
| 0x2812 5038 |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TIM64LOADVALU | Load value for upper 32 bits of 64 bit timer. When this register is written to, the value written is immediately loaded into a temporary register. The value in the temporary register is only written to the timer when the lower 32 bit word (TIM64LOADVALL) is written. | RW | 0x0000 0000

### MSTIMER : TIM64LOADVALL

Address offset | 0x03C
Physical address | 0x2012 503C | Instance | MSTIMER_LO
| 0x2812 503C |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TIM64LOADVALL | Load value for lower 32 bits of 64 bit timer. When this register is written to, the value written is immediately loaded into the lower 32 bits of the 64 bit counter along with the value in register TIM64LOADVALU. This applies in both periodic and one-shot mode. The value stored in this register is also used to reload the counter when the count reaches zero and the counter is operating in periodic mode. This register will be overwritten if the TIM64BGLOADVAL register is written to but the counter will not be updated with the new value in this case. TIM64LOADVALL always stores the lower 32 bits of the value which will be loaded into the counter when it next reaches zero and periodic mode is selected. | RW | 0x0000 0000

### MSTIMER : TIM64BGLOADVALU

Address offset | 0x040
Physical address | 0x2012 5040 | Instance | MSTIMER_LO
| 0x2812 5040 |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TIM64BGLOADVALU | Background load value for upper 32 bits of 64 bit mode timer. This value only propagates the to the TIM64BGLOADVAL when the lower 32 bits is written. | RW | 0x0000 0000

### MSTIMER : TIM64BGLOADVALL

Address offset | 0x044
Physical address | 0x2012 5044 | Instance | MSTIMER_LO
| 0x2812 5044 |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TIM64BGLOADVALL | Background load value for lower 32 bits of 64 bit mode timer. When this register is written to, the both the upper and lower words are written into the TIM64BGLOADVALL register without updating the counter itself. This allows a new load value to be put in place for the counter without interrupting the current count cycle. | RW | 0x0000 0000

### MSTIMER : TIM64CONTROL

Address offset | 0x048
Physical address | 0x2012 5048 | Instance | MSTIMER_LO
| 0x2812 5048 |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved |  | RO Rreturns0s | 0x0000 0000
2 | TIM64INTEN | Timer 64 interrupt enable bit. 0 = timer 64 interrupt disabled. 1 = timer 2 interrupt enabled | RW | 0
1 | TIM64MODECONTROL | This bit sets the operating mode for timer 64. 0=periodic mode and 1= one-shot mode. | RW | 0
0 | TIM64ENABLE | Enable bit for 64 bit mode timer: 0 = timer 64 disabled, i.e. counter decrements 1 = timer 64 enabled, i.e. counter value is static | RW | 0

### MSTIMER : TIM64RIS

Address offset | 0x04C
Physical address | 0x2012 504C | Instance | MSTIMER_LO
| 0x2812 504C |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved |  | RO Rreturns0s | 0x0000 0000
0 | TIM64RIS | Raw interrupt status bit for 64 bit mode timer. This is bit is set when 64 bit mode timer reaches zero. Writing a '1' to this bit clears the bit. Writing '0' has no effect. | RW | 0

### MSTIMER : TIM64MIS

Address offset | 0x050
Physical address | 0x2012 5050 | Instance | MSTIMER_LO
| 0x2812 5050 |  | MSTIMER_HI
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved |  | RO Rreturns0s | 0x0000 0000
0 | TIM64MIS | Masked interrupt status bit for 64 bit mode timer. This read only bit is the logical AND of the TIM64RIS and TIM64INTEN bits. The TIMER64INT output from the timer will have the same value as this bit. Writing to this bit has no effect. | RO | 0

### MSTIMER : TIM64MODE

Address offset | 0x054
Physical address | 0x2012 5054 | Instance | MSTIMER_LO
| 0x2812 5054 |  | MSTIMER_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved |  | RO Rreturns0s | 0x0000 0000
0 | TIM64MODE | Writing a 1 to this register forces the timers 1 and 2 to be used to implement a 64 bit mode timing. Writing a 0 forces the timers operate independently. | RW | 0

MSTIMER has no common memories.