## GEM_GXIMICROSEMI

This section provides information on the gem_gximicrosemi Module Instance. Each of the module registers is described below.

No lock registers supported.

Release date: May 21,2024

## Return to pfsoc_mss_regmap

## gem_gxlmicrosemi Register Mapping Summary

### Common Register Mapping Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset
network_control | RW | 32 | 0x0000 0000 | 0x0000
network_config | RW | 32 | 0x0028 0000 | 0x0004
network_status | RO | 32 | 0x0000 0004 | 0x0008
user_io_register | RW | 32 | 0x0000 0000 | 0x000C
dma_config | RW | 32 | 0x0002 0704 | 0x0010
transmit_status | RW | 32 | 0x0000 0000 | 0x0014
receive_q_ptr | RW | 32 | 0x0000 0000 | 0x0018
transmit_q_ptr | RW | 32 | 0x0000 0000 | 0x001C
receive_status | RW | 32 | 0x0000 0000 | 0x0020
int_status | RW | 32 | 0x0000 0000 | 0x0024
int_enable | RW | 32 | 0x0000 0000 | 0x0028
int_disable | RW | 32 | 0x0000 0000 | 0x002C
int_mask | RO | 32 | 0xFFFF FEFF | 0x0030
phy_management | RW | 32 | 0x0000 0000 | 0x0034
pause_time | RO | 32 | 0x0000 0000 | 0x0038
tx_pause_quantum | RW | 32 | 0xFFFF FFFF | 0x003C
pbuf_txcutthru | RW | 32 | 0x0000 07FF | 0x0040
pbuf_rxcutthru | RW | 32 | 0x0000 07FF | 0x0044
jumbo_max_length | RW | 32 | 0x0000 2800 | 0x0048
axi_max_pipeline | RW | 32 | 0x0000 0101 | 0x0054
int_moderation | RW | 32 | 0x0000 0000 | 0x005C
sys_wake_time | RW | 32 | 0x0000 0000 | 0x0060
lockup_config | RW | 32 | 0x07FF FFFF | 0x0068
mac_lockup_time | RW | 32 | 0x07FF FFFF | 0x006C
lockup_config3 | RW | 32 | 0x0000 0000 | 0x0070
rx_water_mark | RW | 32 | 0x0000 0000 | 0x007C
hash_bottom | RW | 32 | 0x0000 0000 | 0x0080
hash_top | RW | 32 | 0x0000 0000 | 0x0084
spec_add1_bottom | RW | 32 | 0x0000 0000 | 0x0088
spec_add1_top | RW | 32 | 0x0000 0000 | 0x008C
spec_add2_bottom | RW | 32 | 0x0000 0000 | 0x0090
spec_add2_top | RW | 32 | 0x0000 0000 | 0x0094
spec_add3_bottom | RW | 32 | 0x0000 0000 | 0x0098
spec_add3_top | RW | 32 | 0x0000 0000 | 0x009C
spec_add4_bottom | RW | 32 | 0x0000 0000 | 0x00A0
spec_add4_top | RW | 32 | 0x0000 0000 | 0x00A4
spec_type1 | RW | 32 | 0x0000 0000 | 0x00A8
spec_type2 | RW | 32 | 0x0000 0000 | 0x00AC
spec_type3 | RW | 32 | 0x0000 0000 | 0x00B0
spec_type4 | RW | 32 | 0x0000 0000 | 0x00B4
wol_register | RW | 32 | 0x0000 0000 | 0x00B8
stretch_ratio | RW | 32 | 0x0000 0000 | 0x00BC
stacked_vlan | RW | 32 | 0x0000 0000 | 0x00C0
tx_pfc_pause | RW | 32 | 0x0000 0000 | 0x00C4
mask_add1_bottom | RW | 32 | 0x0000 0000 | 0x00C8
mask_add1_top | RW | 32 | 0x0000 0000 | 0x00CC
dma_addr_or_mask | RW | 32 | 0x0000 0000 | 0x00D0
rx_ptp_unicast | RW | 32 | 0x0000 0000 | 0x00D4
tx_ptp_unicast | RW | 32 | 0x0000 0000 | 0x00D8
tsu_nsec_cmp | RW | 32 | 0x0000 0000 | 0x00DC
tsu_sec_cmp | RW | 32 | 0x0000 0000 | 0x00E0
tsu_msb_sec_cmp | RW | 32 | 0x0000 0000 | 0x00E4
tsu_ptp_tx_msb_sec | RO | 32 | 0x0000 0000 | 0x00E8
tsu_ptp_rx_msb_sec | RO | 32 | 0x0000 0000 | 0x00EC
tsu_peer_tx_msb_sec | RO | 32 | 0x0000 0000 | 0x00F0
tsu_peer_rx_msb_sec | RO | 32 | 0x0000 0000 | 0x00F4
dpram_fill_dbg | RW | 32 | 0x0000 0000 | 0x00F8
revision_reg | RO | 32 | 0x0107 010C | 0x00FC
octets_txed_bottom | RO | 32 | 0x0000 0000 | 0x0100
octets_txed_top | RO | 32 | 0x0000 0000 | 0x0104
frames_txed_ok | RO | 32 | 0x0000 0000 | 0x0108
broadcast_txed | RO | 32 | 0x0000 0000 | 0x010C
multicast_txed | RO | 32 | 0x0000 0000 | 0x0110
pause_frames_txed | RO | 32 | 0x0000 0000 | 0x0114
frames_txed_64 | RO | 32 | 0x0000 0000 | 0x0118
frames_txed_65 | RO | 32 | 0x0000 0000 | 0x011C
frames_txed_128 | RO | 32 | 0x0000 0000 | 0x0120
frames_txed_256 | RO | 32 | 0x0000 0000 | 0x0124
frames_txed_512 | RO | 32 | 0x0000 0000 | 0x0128
frames_txed_1024 | RO | 32 | 0x0000 0000 | 0x012C
frames_txed_1519 | RO | 32 | 0x0000 0000 | 0x0130
tx_underruns | RO | 32 | 0x0000 0000 | 0x0134
single_collisions | RO | 32 | 0x0000 0000 | 0x0138
multiple_collisions | RO | 32 | 0x0000 0000 | 0x013C
excessive_collisions | RO | 32 | 0x0000 0000 | 0x0140
late_collisions | RO | 32 | 0x0000 0000 | 0x0144
deferred_frames | RO | 32 | 0x0000 0000 | 0x0148
crs_errors | RO | 32 | 0x0000 0000 | 0x014C
octets_rxed_bottom | RO | 32 | 0x0000 0000 | 0x0150
octets_rxed_top | RO | 32 | 0x0000 0000 | 0x0154
frames_rxed_ok | RO | 32 | 0x0000 0000 | 0x0158
broadcast_rxed | RO | 32 | 0x0000 0000 | 0x015C
multicast_rxed | RO | 32 | 0x0000 0000 | 0x0160
pause_frames_rxed | RO | 32 | 0x0000 0000 | 0x0164
frames_rxed_64 | RO | 32 | 0x0000 0000 | 0x0168
frames_rxed_65 | RO | 32 | 0x0000 0000 | 0x016C
frames_rxed_128 | RO | 32 | 0x0000 0000 | 0x0170
frames_rxed_256 | RO | 32 | 0x0000 0000 | 0x0174
frames_rxed_512 | RO | 32 | 0x0000 0000 | 0x0178
frames_rxed_1024 | RO | 32 | 0x0000 0000 | 0x017C
frames_rxed_1519 | RO | 32 | 0x0000 0000 | 0x0180
undersize_frames | RO | 32 | 0x0000 0000 | 0x0184
excessive_rx_length | RO | 32 | 0x0000 0000 | 0x0188
rx_jabbers | RO | 32 | 0x0000 0000 | 0x018C
fcs_errors | RO | 32 | 0x0000 0000 | 0x0190
rx_length_errors | RO | 32 | 0x0000 0000 | 0x0194
rx_symbol_errors | RO | 32 | 0x0000 0000 | 0x0198
alignment_errors | RO | 32 | 0x0000 0000 | 0x019C
rx_resource_errors | RO | 32 | 0x0000 0000 | 0x01A0
rx_overruns | RO | 32 | 0x0000 0000 | 0x01A4
rx_ip_ck_errors | RO | 32 | 0x0000 0000 | 0x01A8
rx_tcp_ck_errors | RO | 32 | 0x0000 0000 | 0x01AC
rx_udp_ck_errors | RO | 32 | 0x0000 0000 | 0x01B0
auto_flushed_pkts | RO | 32 | 0x0000 0000 | 0x01B4
tsu_timer_incr_sub_nsec | RW | 32 | 0x0000 0000 | 0x01BC
tsu_timer_msb_sec | RW | 32 | 0x0000 0000 | 0x01C0
tsu_strobe_msb_sec | RO | 32 | 0x0000 0000 | 0x01C4
tsu_strobe_sec | RO | 32 | 0x0000 0000 | 0x01C8
tsu_strobe_nsec | RO | 32 | 0x0000 0000 | 0x01CC
tsu_timer_sec | RW | 32 | 0x0000 0000 | 0x01D0
tsu_timer_nsec | RW | 32 | 0x0000 0000 | 0x01D4
tsu_timer_adjust | RW | 32 | 0x0000 0000 | 0x01D8
tsu_timer_incr | RW | 32 | 0x0000 0000 | 0x01DC
tsu_ptp_tx_sec | RO | 32 | 0x0000 0000 | 0x01E0
tsu_ptp_tx_nsec | RO | 32 | 0x0000 0000 | 0x01E4
tsu_ptp_rx_sec | RO | 32 | 0x0000 0000 | 0x01E8
tsu_ptp_rx_nsec | RO | 32 | 0x0000 0000 | 0x01EC
tsu_peer_tx_sec | RO | 32 | 0x0000 0000 | 0x01F0
tsu_peer_tx_nsec | RO | 32 | 0x0000 0000 | 0x01F4
tsu_peer_rx_sec | RO | 32 | 0x0000 0000 | 0x01F8
tsu_peer_rx_nsec | RO | 32 | 0x0000 0000 | 0x01FC
pcs_control | RW | 32 | 0x0000 9040 | 0x0200
pcs_status | RO | 32 | 0x0000 0109 | 0x0204
pcs_phy_top_id | RO | 32 | 0x0000 0107 | 0x0208
pcs_phy_bot_id | RO | 32 | 0x0000 010C | 0x020C
pcs_an_adv | RW | 32 | 0x0000 0020 | 0x0210
pcs_an_lp_base | RO | 32 | 0x0000 0000 | 0x0214
pcs_an_exp | RO | 32 | 0x0000 0004 | 0x0218
pcs_an_np_tx | RW | 32 | 0x0000 0000 | 0x021C
pcs_an_lp_np | RO | 32 | 0x0000 0000 | 0x0220
pcs_an_ext_status | RO | 32 | 0x0000 8000 | 0x023C
tx_pause_quantum1 | RW | 32 | 0xFFFF FFFF | 0x0260
tx_pause_quantum2 | RW | 32 | 0xFFFF FFFF | 0x0264
tx_pause_quantum3 | RW | 32 | 0xFFFF FFFF | 0x0268
pfc_status | RO | 32 | 0x0000 0000 | 0x026C
rx_lpi | RO | 32 | 0x0000 0000 | 0x0270
rx_lpi_time | RO | 32 | 0x0000 0000 | 0x0274
tx_lpi | RO | 32 | 0x0000 0000 | 0x0278
tx_lpi_time | RO | 32 | 0x0000 0000 | 0x027C
designcfg_debug1 | RO | 32 | 0x0453 1B10 | 0x0280
designcfg_debug2 | RO | 32 | 0x6EF1 2800 | 0x0284
designcfg_debug3 | RO | 32 | 0x0400 0000 | 0x0288
designcfg_debug4 | RO | 32 | 0x0000 0000 | 0x028C
designcfg_debug5 | RO | 32 | 0x502E 2745 | 0x0290
designcfg_debug6 | RO | 32 | 0x0B82 000E | 0x0294
designcfg_debug7 | RO | 32 | 0x0000 0000 | 0x0298
designcfg_debug8 | RO | 32 | 0x0404 040C | 0x029C
designcfg_debug9 | RO | 32 | 0x0000 0000 | 0x02A0
designcfg_debug10 | RO | 32 | 0x2224 1111 | 0x02A4
designcfg_debug11 | RO | 32 | 0x0000 0000 | 0x02A8
designcfg_debug12 | RO | 32 | 0x0333 0804 | 0x02AC
axi_qos_cfg_0 | RW | 32 | 0x0000 0000 | 0x02E0
int_q1_status | RW | 32 | 0x0000 0000 | 0x0400
int_q2_status | RW | 32 | 0x0000 0000 | 0x0404
int_q3_status | RW | 32 | 0x0000 0000 | 0x0408
transmit_q1_ptr | RW | 32 | 0x0000 0000 | 0x0440
transmit_q2_ptr | RW | 32 | 0x0000 0000 | 0x0444
transmit_q3_ptr | RW | 32 | 0x0000 0000 | 0x0448
receive_q1_ptr | RW | 32 | 0x0000 0000 | 0x0480
receive_q2_ptr | RW | 32 | 0x0000 0000 | 0x0484
receive_q3_ptr | RW | 32 | 0x0000 0000 | 0x0488
dma_rxbuf_size_q1 | RW | 32 | 0x0000 0002 | 0x04A0
dma_rxbuf_size_q2 | RW | 32 | 0x0000 0002 | 0x04A4
dma_rxbuf_size_q3 | RW | 32 | 0x0000 0002 | 0x04A8
cbs_control | RW | 32 | 0x0000 0000 | 0x04BC
cbs_idleslope_q_a | RW | 32 | 0x0000 0000 | 0x04C0
cbs_idleslope_q_b | RW | 32 | 0x0000 0000 | 0x04C4
upper_tx_q_base_addr | RW | 32 | 0x0000 0000 | 0x04C8
tx_bd_control | RW | 32 | 0x0000 0000 | 0x04CC
rx_bd_control | RW | 32 | 0x0000 0000 | 0x04D0
upper_rx_q_base_addr | RW | 32 | 0x0000 0000 | 0x04D4
wd_counter | RW | 32 | 0x0000 0007 | 0x04EC
axi_tx_full_thresh0 | RW | 32 | 0x0006 0008 | 0x04F8
axi_tx_full_thresh1 | RW | 32 | 0x0000 0000 | 0x04FC
screening_type_1_register_0 | RW | 32 | 0x0000 0000 | 0x0500
screening_type_1_register_1 | RW | 32 | 0x0000 0000 | 0x0504
screening_type_1_register_2 | RW | 32 | 0x0000 0000 | 0x0508
screening_type_1_register_3 | RW | 32 | 0x0000 0000 | 0x050C
screening_type_2_register_0 | RW | 32 | 0x0000 0000 | 0x0540
screening_type_2_register_1 | RW | 32 | 0x0000 0000 | 0x0544
screening_type_2_register_2 | RW | 32 | 0x0000 0000 | 0x0548
screening_type_2_register_3 | RW | 32 | 0x0000 0000 | 0x054C
tx_sched_ctrl | RW | 32 | 0x0000 0000 | 0x0580
bw_rate_limit_q0to3 | RW | 32 | 0x0000 0000 | 0x0590
tx_q_seg_alloc_q_lower | RW | 32 | 0x0000 0000 | 0x05A0
int_q1_enable | RW | 32 | 0x0000 0000 | 0x0600
int_q2_enable | RW | 32 | 0x0000 0000 | 0x0604
int_q3_enable | RW | 32 | 0x0000 0000 | 0x0608
int_q1_disable | RW | 32 | 0x0000 0000 | 0x0620
int_q2_disable | RW | 32 | 0x0000 0000 | 0x0624
int_q3_disable | RW | 32 | 0x0000 0000 | 0x0628
int_q1_mask | RO | 32 | 0x0000 08E6 | 0x0640
int_q2_mask | RO | 32 | 0x0000 08E6 | 0x0644
int_q3_mask | RO | 32 | 0x0000 08E6 | 0x0648
screening_type_2_ethertype_reg_0 | RW | 32 | 0x0000 0000 | 0x06E0
screening_type_2_ethertype_reg_1 | RW | 32 | 0x0000 0000 | 0x06E4
screening_type_2_ethertype_reg_2 | RW | 32 | 0x0000 0000 | 0x06E8
screening_type_2_ethertype_reg_3 | RW | 32 | 0x0000 0000 | 0x06EC
type2_compare_0_word_0 | RW | 32 | 0x0000 0000 | 0x0700
type2_compare_0_word_1 | RW | 32 | 0x0000 0000 | 0x0704
type2_compare_1_word_0 | RW | 32 | 0x0000 0000 | 0x0708
type2_compare_1_word_1 | RW | 32 | 0x0000 0000 | 0x070C
type2_compare_2_word_0 | RW | 32 | 0x0000 0000 | 0x0710
type2_compare_2_word_1 | RW | 32 | 0x0000 0000 | 0x0714
type2_compare_3_word_0 | RW | 32 | 0x0000 0000 | 0x0718
type2_compare_3_word_1 | RW | 32 | 0x0000 0000 | 0x071C
enst_start_time_q0 | RW | 32 | 0x0000 0000 | 0x0800
enst_start_time_q1 | RW | 32 | 0x0000 0000 | 0x0804
enst_start_time_q2 | RW | 32 | 0x0000 0000 | 0x0808
enst_start_time_q3 | RW | 32 | 0x0000 0000 | 0x080C
enst_on_time_q0 | RW | 32 | 0x0001 FFFF | 0x0820
enst_on_time_q1 | RW | 32 | 0x0001 FFFF | 0x0824
enst_on_time_q2 | RW | 32 | 0x0001 FFFF | 0x0828
enst_on_time_q3 | RW | 32 | 0x0001 FFFF | 0x082C
enst_off_time_q0 | RW | 32 | 0x0000 0000 | 0x0840
enst_off_time_q1 | RW | 32 | 0x0000 0000 | 0x0844
enst_off_time_q2 | RW | 32 | 0x0000 0000 | 0x0848
enst_off_time_q3 | RW | 32 | 0x0000 0000 | 0x084C
enst_control | RW | 32 | 0x0000 0000 | 0x0880
frer_timeout | RW | 32 | 0x0000 0000 | 0x08A0
frer_red_tag | RW | 32 | 0x4000 F1C1 | 0x08A4
frer_control_1_a | RW | 32 | 0x0000 0000 | 0x08C0
frer_control_1_b | RW | 32 | 0x0000 0000 | 0x08C4
frer_statistics_1_a | RO | 32 | 0x0000 0000 | 0x08C8
frer_statistics_1_b | RO | 32 | 0x0000 0000 | 0x08CC
frer_control_2_a | RW | 32 | 0x0000 0000 | 0x08D0
frer_control_2_b | RW | 32 | 0x0000 0000 | 0x08D4
frer_statistics_2_a | RO | 32 | 0x0000 0000 | 0x08D8
frer_statistics_2_b | RO | 32 | 0x0000 0000 | 0x08DC
frer_control_3_a | RW | 32 | 0x0000 0000 | 0x08E0
frer_control_3_b | RW | 32 | 0x0000 0000 | 0x08E4
frer_statistics_3_a | RO | 32 | 0x0000 0000 | 0x08E8
frer_statistics_3_b | RO | 32 | 0x0000 0000 | 0x08EC
frer_control_4_a | RW | 32 | 0x0000 0000 | 0x08F0
frer_control_4_b | RW | 32 | 0x0000 0000 | 0x08F4
frer_statistics_4_a | RO | 32 | 0x0000 0000 | 0x08F8
frer_statistics_4_b | RO | 32 | 0x0000 0000 | 0x08FC
rx_q0_flush | RW | 32 | 0x0000 0000 | 0x0B00
rx_q1_flush | RW | 32 | 0x0000 0000 | 0x0B04
rx_q2_flush | RW | 32 | 0x0000 0000 | 0x0B08
rx_q3_flush | RW | 32 | 0x0000 0000 | 0x0B0C
scr2_reg0_rate_limit | RW | 32 | 0x0000 0000 | 0x0B40
scr2_reg1_rate_limit | RW | 32 | 0x0000 0000 | 0x0B44
scr2_reg2_rate_limit | RW | 32 | 0x0000 0000 | 0x0B48
scr2_reg3_rate_limit | RW | 32 | 0x0000 0000 | 0x0B4C
scr2_rate_status | RO | 32 | 0x0000 0000 | 0x0B80
asf_int_status | RW | 32 | 0x0000 0000 | 0x0E00
asf_int_raw_status | RW | 32 | 0x0000 0000 | 0x0E04
asf_int_mask | RW | 32 | 0x0000 0030 | 0x0E08
asf_int_test | RW | 32 | 0x0000 0000 | 0x0E0C
asf_fatal_nonfatal_select | RW | 32 | 0x0000 0030 | 0x0E10
asf_trans_to_fault_mask | RW | 32 | 0x0000 000F | 0x0E34
asf_trans_to_fault_status | RW | 32 | 0x0000 0000 | 0x0E38
asf_protocol_fault_mask | RW | 32 | 0x003F 01FF | 0x0E40
asf_protocol_fault_status | RW | 32 | 0x0000 0000 | 0x0E44
mmsl_control | RW | 32 | 0x0000 0020 | 0x0F00
mmsl_status | RO | 32 | 0x0000 0000 | 0x0F04
mmsl_err_stats | RO | 32 | 0x0000 0000 | 0x0F08
mmsl_ass_ok_count | RO | 32 | 0x0000 0000 | 0x0F0C
mmsl_frag_count_rx | RO | 32 | 0x0000 0000 | 0x0F10
mmsl_frag_count_tx | RO | 32 | 0x0000 0000 | 0x0F14
mmsl_int_status | RW | 32 | 0x0000 0000 | 0x0F18
mmsl_int_enable | RW | 32 | 0x0000 0000 | 0x0F1C
mmsl_int_disable | RW | 32 | 0x0000 0000 | 0x0F20
mmsl_int_mask | RO | 32 | 0x0000 003F | 0x0F24
emac_network_control | RW | 32 | 0x0000 0000 | 0x1000
emac_network_config | RW | 32 | 0x0028 0000 | 0x1004
emac_network_status | RO | 32 | 0x0000 0004 | 0x1008
emac_dma_config | RW | 32 | 0x0002 0704 | 0x1010
emac_transmit_status | RW | 32 | 0x0000 0000 | 0x1014
emac_receive_q_ptr | RW | 32 | 0x0000 0000 | 0x1018
emac_transmit_q_ptr | RW | 32 | 0x0000 0000 | 0x101C
emac_receive_status | RW | 32 | 0x0000 0000 | 0x1020
emac_int_status | RW | 32 | 0x0000 0000 | 0x1024
emac_int_enable | RW | 32 | 0x0000 0000 | 0x1028
emac_int_disable | RW | 32 | 0x0000 0000 | 0x102C
emac_int_mask | RO | 32 | 0xFFFF FEFF | 0x1030
emac_phy_management | RW | 32 | 0x0000 0000 | 0x1034
emac_pause_time | RO | 32 | 0x0000 0000 | 0x1038
emac_tx_pause_quantum | RW | 32 | 0xFFFF FFFF | 0x103C
emac_pbuf_txcutthru | RW | 32 | 0x0000 01FF | 0x1040
emac_pbuf_rxcutthru | RW | 32 | 0x0000 01FF | 0x1044
emac_jumbo_max_length | RW | 32 | 0x0000 2800 | 0x1048
emac_axi_max_pipeline | RW | 32 | 0x0000 0101 | 0x1054
emac_int_moderation | RW | 32 | 0x0000 0000 | 0x105C
emac_sys_wake_time | RW | 32 | 0x0000 0000 | 0x1060
emac_lockup_config | RW | 32 | 0x07FF FFFF | 0x1068
emac_mac_lockup_time | RW | 32 | 0x07FF FFFF | 0x106C
emac_lockup_config3 | RW | 32 | 0x0000 0000 | 0x1070
emac_rx_water_mark | RW | 32 | 0x0000 0000 | 0x107C
emac_hash_bottom | RW | 32 | 0x0000 0000 | 0x1080
emac_hash_top | RW | 32 | 0x0000 0000 | 0x1084
emac_spec_add1_bottom | RW | 32 | 0x0000 0000 | 0x1088
emac_spec_add1_top | RW | 32 | 0x0000 0000 | 0x108C
emac_spec_add2_bottom | RW | 32 | 0x0000 0000 | 0x1090
emac_spec_add2_top | RW | 32 | 0x0000 0000 | 0x1094
emac_spec_add3_bottom | RW | 32 | 0x0000 0000 | 0x1098
emac_spec_add3_top | RW | 32 | 0x0000 0000 | 0x109C
emac_spec_add4_bottom | RW | 32 | 0x0000 0000 | 0x10A0
emac_spec_add4_top | RW | 32 | 0x0000 0000 | 0x10A4
emac_spec_type1 | RW | 32 | 0x0000 0000 | 0x10A8
emac_spec_type2 | RW | 32 | 0x0000 0000 | 0x10AC
emac_spec_type3 | RW | 32 | 0x0000 0000 | 0x10B0
emac_spec_type4 | RW | 32 | 0x0000 0000 | 0x10B4
emac_wol_register | RW | 32 | 0x0000 0000 | 0x10B8
emac_stretch_ratio | RW | 32 | 0x0000 0000 | 0x10BC
emac_stacked_vlan | RW | 32 | 0x0000 0000 | 0x10C0
emac_tx_pfc_pause | RW | 32 | 0x0000 0000 | 0x10C4
emac_mask_add1_bottom | RW | 32 | 0x0000 0000 | 0x10C8
emac_mask_add1_top | RW | 32 | 0x0000 0000 | 0x10CC
emac_dma_addr_or_mask | RW | 32 | 0x0000 0000 | 0x10D0
emac_rx_ptp_unicast | RW | 32 | 0x0000 0000 | 0x10D4
emac_tx_ptp_unicast | RW | 32 | 0x0000 0000 | 0x10D8
emac_tsu_nsec_cmp | RW | 32 | 0x0000 0000 | 0x10DC
emac_tsu_sec_cmp | RW | 32 | 0x0000 0000 | 0x10E0
emac_tsu_msb_sec_cmp | RW | 32 | 0x0000 0000 | 0x10E4
emac_tsu_ptp_tx_msb_sec | RO | 32 | 0x0000 0000 | 0x10E8
emac_tsu_ptp_rx_msb_sec | RO | 32 | 0x0000 0000 | 0x10EC
emac_tsu_peer_tx_msb_sec | RO | 32 | 0x0000 0000 | 0x10F0
emac_tsu_peer_rx_msb_sec | RO | 32 | 0x0000 0000 | 0x10F4
emac_dpram_fill_dbg | RW | 32 | 0x0000 0000 | 0x10F8
emac_revision_reg | RO | 32 | 0x0107 010C | 0x10FC
emac_octets_txed_bottom | RO | 32 | 0x0000 0000 | 0x1100
emac_octets_txed_top | RO | 32 | 0x0000 0000 | 0x1104
emac_frames_txed_ok | RO | 32 | 0x0000 0000 | 0x1108
emac_broadcast_txed | RO | 32 | 0x0000 0000 | 0x110C
emac_multicast_txed | RO | 32 | 0x0000 0000 | 0x1110
emac_pause_frames_txed | RO | 32 | 0x0000 0000 | 0x1114
emac_frames_txed_64 | RO | 32 | 0x0000 0000 | 0x1118
emac_frames_txed_65 | RO | 32 | 0x0000 0000 | 0x111C
emac_frames_txed_128 | RO | 32 | 0x0000 0000 | 0x1120
emac_frames_txed_256 | RO | 32 | 0x0000 0000 | 0x1124
emac_frames_txed_512 | RO | 32 | 0x0000 0000 | 0x1128
emac_frames_txed_1024 | RO | 32 | 0x0000 0000 | 0x112C
emac_frames_txed_1519 | RO | 32 | 0x0000 0000 | 0x1130
emac_tx_underruns | RO | 32 | 0x0000 0000 | 0x1134
emac_single_collisions | RO | 32 | 0x0000 0000 | 0x1138
emac_multiple_collisions | RO | 32 | 0x0000 0000 | 0x113C
emac_excessive_collisions | RO | 32 | 0x0000 0000 | 0x1140
emac_late_collisions | RO | 32 | 0x0000 0000 | 0x1144
emac_deferred_frames | RO | 32 | 0x0000 0000 | 0x1148
emac_crs_errors | RO | 32 | 0x0000 0000 | 0x114C
emac_octets_rxed_bottom | RO | 32 | 0x0000 0000 | 0x1150
emac_octets_rxed_top | RO | 32 | 0x0000 0000 | 0x1154
emac_frames_rxed_ok | RO | 32 | 0x0000 0000 | 0x1158
emac_broadcast_rxed | RO | 32 | 0x0000 0000 | 0x115C
emac_multicast_rxed | RO | 32 | 0x0000 0000 | 0x1160
emac_pause_frames_rxed | RO | 32 | 0x0000 0000 | 0x1164
emac_frames_rxed_64 | RO | 32 | 0x0000 0000 | 0x1168
emac_frames_rxed_65 | RO | 32 | 0x0000 0000 | 0x116C
emac_frames_rxed_128 | RO | 32 | 0x0000 0000 | 0x1170
emac_frames_rxed_256 | RO | 32 | 0x0000 0000 | 0x1174
emac_frames_rxed_512 | RO | 32 | 0x0000 0000 | 0x1178
emac_frames_rxed_1024 | RO | 32 | 0x0000 0000 | 0x117C
emac_frames_rxed_1519 | RO | 32 | 0x0000 0000 | 0x1180
emac_undersize_frames | RO | 32 | 0x0000 0000 | 0x1184
emac_excessive_rx_length | RO | 32 | 0x0000 0000 | 0x1188
emac_rx_jabbers | RO | 32 | 0x0000 0000 | 0x118C
emac_fcs_errors | RO | 32 | 0x0000 0000 | 0x1190
emac_rx_length_errors | RO | 32 | 0x0000 0000 | 0x1194
emac_rx_symbol_errors | RO | 32 | 0x0000 0000 | 0x1198
emac_alignment_errors | RO | 32 | 0x0000 0000 | 0x119C
emac_rx_resource_errors | RO | 32 | 0x0000 0000 | 0x11A0
emac_rx_overruns | RO | 32 | 0x0000 0000 | 0x11A4
emac_rx_ip_ck_errors | RO | 32 | 0x0000 0000 | 0x11A8
emac_rx_tcp_ck_errors | RO | 32 | 0x0000 0000 | 0x11AC
emac_rx_udp_ck_errors | RO | 32 | 0x0000 0000 | 0x11B0
emac_auto_flushed_pkts | RO | 32 | 0x0000 0000 | 0x11B4
emac_tsu_timer_incr_sub_nsec | RW | 32 | 0x0000 0000 | 0x11BC
emac_tsu_timer_msb_sec | RW | 32 | 0x0000 0000 | 0x11C0
emac_tsu_strobe_msb_sec | RO | 32 | 0x0000 0000 | 0x11C4
emac_tsu_strobe_sec | RO | 32 | 0x0000 0000 | 0x11C8
emac_tsu_strobe_nsec | RO | 32 | 0x0000 0000 | 0x11CC
emac_tsu_timer_sec | RW | 32 | 0x0000 0000 | 0x11D0
emac_tsu_timer_nsec | RW | 32 | 0x0000 0000 | 0x11D4
emac_tsu_timer_adjust | RW | 32 | 0x0000 0000 | 0x11D8
emac_tsu_timer_incr | RW | 32 | 0x0000 0000 | 0x11DC
emac_tsu_ptp_tx_sec | RO | 32 | 0x0000 0000 | 0x11E0
emac_tsu_ptp_tx_nsec | RO | 32 | 0x0000 0000 | 0x11E4
emac_tsu_ptp_rx_sec | RO | 32 | 0x0000 0000 | 0x11E8
emac_tsu_ptp_rx_nsec | RO | 32 | 0x0000 0000 | 0x11EC
emac_tsu_peer_tx_sec | RO | 32 | 0x0000 0000 | 0x11F0
emac_tsu_peer_tx_nsec | RO | 32 | 0x0000 0000 | 0x11F4
emac_tsu_peer_rx_sec | RO | 32 | 0x0000 0000 | 0x11F8
emac_tsu_peer_rx_nsec | RO | 32 | 0x0000 0000 | 0x11FC
emac_tx_pause_quantum1 | RW | 32 | 0xFFFF FFFF | 0x1260
emac_tx_pause_quantum2 | RW | 32 | 0xFFFF FFFF | 0x1264
emac_tx_pause_quantum3 | RW | 32 | 0xFFFF FFFF | 0x1268
emac_pfc_status | RO | 32 | 0x0000 0000 | 0x126C
emac_rx_lpi | RO | 32 | 0x0000 0000 | 0x1270
emac_rx_lpi_time | RO | 32 | 0x0000 0000 | 0x1274
emac_tx_lpi | RO | 32 | 0x0000 0000 | 0x1278
emac_tx_lpi_time | RO | 32 | 0x0000 0000 | 0x127C
emac_designcfg_debug1 | RO | 32 | 0x0450 8510 | 0x1280
emac_designcfg_debug2 | RO | 32 | 0x6671 2800 | 0x1284
emac_designcfg_debug3 | RO | 32 | 0x0400 0000 | 0x1288
emac_designcfg_debug4 | RO | 32 | 0x0000 0000 | 0x128C
emac_designcfg_debug5 | RO | 32 | 0x502E 2745 | 0x1290
emac_designcfg_debug6 | RO | 32 | 0x0B92 0000 | 0x1294
emac_designcfg_debug7 | RO | 32 | 0x0000 0000 | 0x1298
emac_designcfg_debug8 | RO | 32 | 0x0102 0006 | 0x129C
emac_designcfg_debug9 | RO | 32 | 0x0000 0000 | 0x12A0
emac_designcfg_debug10 | RO | 32 | 0x2224 1111 | 0x12A4
emac_designcfg_debug11 | RO | 32 | 0x0000 0000 | 0x12A8
emac_designcfg_debug12 | RO | 32 | 0x0333 0802 | 0x12AC
emac_axi_qos_cfg | RW | 32 | 0x0000 0000 | 0x12E0
emac_cbs_control | RW | 32 | 0x0000 0000 | 0x14BC
emac_cbs_idleslope_q_a | RW | 32 | 0x0000 0000 | 0x14C0
emac_cbs_idleslope_q_b | RW | 32 | 0x0000 0000 | 0x14C4
emac_upper_tx_q_base_addr | RW | 32 | 0x0000 0000 | 0x14C8
emac_tx_bd_control | RW | 32 | 0x0000 0000 | 0x14CC
emac_rx_bd_control | RW | 32 | 0x0000 0000 | 0x14D0
emac_upper_rx_q_base_addr | RW | 32 | 0x0000 0000 | 0x14D4
emac_wd_counter | RW | 32 | 0x0000 0007 | 0x14EC
emac_wd_axi_tx_full_thresh0 | RW | 32 | 0x0006 0008 | 0x14F8
emac_wd_axi_tx_full_thresh1 | RW | 32 | 0x0000 0000 | 0x14FC
emac_screening_type_1_register | RW | 32 | 0x0000 0000 | 0x1500
emac_screening_type_2_register_0 | RW | 32 | 0x0000 0000 | 0x1540
emac_screening_type_2_register_1 | RW | 32 | 0x0000 0000 | 0x1544
emac_tx_sched_ctrl | RW | 32 | 0x0000 0000 | 0x1580
emac_bw_rate_limit | RW | 32 | 0x0000 0000 | 0x1590
emac_tx_q_seg_alloc_q_lower | RW | 32 | 0x0000 0000 | 0x15A0
emac_type2_compare_0_word_0 | RW | 32 | 0x0000 0000 | 0x1700
emac_type2_compare_0_word_1 | RW | 32 | 0x0000 0000 | 0x1704
emac_type2_compare_1_word_0 | RW | 32 | 0x0000 0000 | 0x1708
emac_type2_compare_1_word_1 | RW | 32 | 0x0000 0000 | 0x170C
emac_type2_compare_2_word_0 | RW | 32 | 0x0000 0000 | 0x1710
emac_type2_compare_2_word_1 | RW | 32 | 0x0000 0000 | 0x1714
emac_type2_compare_3_word_0 | RW | 32 | 0x0000 0000 | 0x1718
emac_type2_compare_3_word_1 | RW | 32 | 0x0000 0000 | 0x171C
emac_type2_compare_4_word_0 | RW | 32 | 0x0000 0000 | 0x1720
emac_type2_compare_4_word_1 | RW | 32 | 0x0000 0000 | 0x1724
emac_type2_compare_5_word_0 | RW | 32 | 0x0000 0000 | 0x1728
emac_type2_compare_5_word_1 | RW | 32 | 0x0000 0000 | 0x172C
emac_enst_start_time | RW | 32 | 0x0000 0000 | 0x1800
emac_enst_on_time | RW | 32 | 0x0001 FFFF | 0x1820
emac_enst_off_time | RW | 32 | 0x0000 0000 | 0x1840
emac_enst_control | RW | 32 | 0x0000 0000 | 0x1880
emac_frer_timeout | RW | 32 | 0x0000 0000 | 0x18A0
emac_frer_red_tag | RW | 32 | 0x4000 F1C1 | 0x18A4
emac_frer_control_1_a | RW | 32 | 0x0000 0000 | 0x18C0
emac_frer_control_1_b | RW | 32 | 0x0000 0000 | 0x18C4
emac_frer_statistics_1_a | RO | 32 | 0x0000 0000 | 0x18C8
emac_frer_statistics_1_b | RO | 32 | 0x0000 0000 | 0x18CC
emac_frer_control_2_a | RW | 32 | 0x0000 0000 | 0x18D0
emac_frer_control_2_b | RW | 32 | 0x0000 0000 | 0x18D4
emac_frer_statistics_2_a | RO | 32 | 0x0000 0000 | 0x18D8
emac_frer_statistics_2_b | RO | 32 | 0x0000 0000 | 0x18DC
emac_rx_q0_flush | RW | 32 | 0x0000 0000 | 0x1B00
emac_scr2_reg0_rate_limit | RW | 32 | 0x0000 0000 | 0x1B40
emac_scr2_reg1_rate_limit | RW | 32 | 0x0000 0000 | 0x1B44
emac_scr2_rate_status | RO | 32 | 0x0000 0000 | 0x1B80
emac_asf_int_status | RW | 32 | 0x0000 0000 | 0x1E00
emac_asf_int_raw_status | RW | 32 | 0x0000 0000 | 0x1E04
emac_asf_int_mask | RW | 32 | 0x0000 0030 | 0x1E08
emac_asf_int_test | RW | 32 | 0x0000 0000 | 0x1E0C
emac_asf_fatal_nonfatal_select | RW | 32 | 0x0000 0030 | 0x1E10
emac_asf_trans_to_fault_mask | RW | 32 | 0x0000 000F | 0x1E34
emac_asf_trans_to_fault_status | RW | 32 | 0x0000 0000 | 0x1E38
emac_asf_protocol_fault_mask | RW | 32 | 0x003F 01FF | 0x1E40
emac_asf_protocol_fault_status | RW | 32 | 0x0000 0000 | 0x1E44

## gem_gxlmicrosemi Register Descriptions

### gem_gxlmicrosemi : network_control

Address offset | 0x0000
Description | The network control register contains general MAC control functions for both receiver and transmitter.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved_31 | Reserved, read as 0, ignored on write. | RO | 0
30 | ifg_eats_qav_credit | Setting this bit high modifies the CBS algorithm so the IFG/IPG associated with a transmit frame counts towards its 802.1Qav credit. | RW | 0
29 | two_pt_five_gig | 2.5G operation selected - setting this bit high drives the speed_mode[3] top level output pin high and also adjusts the link timer in the PCS auto-negotiation block to ensure it delivers 10ms for 2500BASE-X and 1.6ms in SGMII mode, and also ensures int_moderation counts 800ns periods with the speeded up MAC clocks. | RW | 0
28 | sel_mii_on_rgmii | If the RGMII interface is being used, set this bit high to configure the RGMII interface for MII operation (in 802.3br configurations this bit has no effect for the eMAC). | RW | 0
27 | oss_correction_field | 1588 One Step Correction Field Update. Set this bit high to enable updating the correction field of PTP 1588 version 2 sync frames by adding the current TSU timer value. | RW | 0
26 | ext_rxq_sel_en | Enable external selection of receive queue. When this bit is high the ext_match1, ext_match2, ext_match3 and ext_match4 inputs will determine which receive queue a frame is routed to. This will be the case regardless of the state of the external address match enable bit 9 of the network config register. Note that receive frames will be dropped unless they are matched by the internal frame filtering functionality. If the external address match enable bit 9 in the network config register is set frames may be matched by an external address match filter as long as one of the ext_match1, ext_match2, ext_match3 and ext_match4 inputs is asserted early enough. When set ext_rxq_sel_en takes precedence over the existing screener functionality. This bit is only relevant if priority queuing is configured. | RW | 0
25 | pfc_ctrl | Enable multiple PFC pause quantums, one per pause priority. | RW | 0
24 | one_step_sync_mode | 1588 One Step Sync Mode. Write 1 to enable. Replace timestamp field in the 1588 header for TX Sync Frames with current TSU timer value. | RW | 0
23 | reserved_23 | Reserved for external TSU timer port enable, read as 0, ignored on write. | RO | 0
22 | store_udp_offset | Store UDP / TCP offset to memory. Setting this bit to one will cause the upper 16-bits of the CRC of every received frame to be replaced with the offset from start of frame to the beginning of the UDP or TCP header. The lower 16-bits of the CRC are replaced with zero and reserved for future use. The offset is measured in units of 2 bytes. Set to zero for normal operation. | RW | 0
21 | alt_sgmii_mode | Alternative sgmii mode. If asserted with sgmii_mode in the network control register the ACK bit is driven before ability detect during transfer of status information from the PHY to the MAC. | RW | 0
20 | ptp_unicast_ena | Enable detection of unicast PTP unicast frames. | RW | 0
19 | tx_lpi_en | Enable LPI transmission when set LPI (low power idle) is immediately transmitted. Depending on configuration LPI is indicated on the GMII, RGMII or MII interface and can be encoded by the PCS used for SGMII. LPI is transmitted even if bit 3 transmit enable is disabled. Setting this bit also sends a pause signal to the transmit datapath. In 802.3br configurations LPI can only be controlled from the pMAC. | RW | 0
18 | flush_rx_pkt_pclk | Flush the next packet from the external RX DPRAM. This bit flushes the frame that is the next in line to be pushed out to the AXI interface. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory. | WO | 0
17 | transmit_pfc_priority_based_pause_frame | Write a one to transmit PFC priority based pause frame. Takes the values stored in the Transmit PFC Pause Register. | WO | 0
16 | pfc_enable | Enable PFC Priority Based Pause Reception capabilities. Setting this bit will enable PFC negotiation and recognition of priority based pause frames. | RW | 0
15 | store_rx_ts | Store receive time stamp to memory. Setting this bit to one will cause the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time stamp point (for releases prior to 1p10 bits 31 and 30 of the value written to the CRC field were hardwired to zero, from release 1p10 onwards these bits represent the two least significant seconds bit of the captured timer value). Set to zero for normal operation. | RW | 0
14:13 | reserved_14_13 | Reserved, read as 0, ignored on write. | RO | 0x0
12 | tx_pause_frame_zero | Transmit zero quantum pause frame - writing one to this bit causes a pause frame with zero quantum to be transmitted. | WO | 0
11 | tx_pause_frame_req | Transmit pause frame - writing one to this bit causes a pause frame to be transmitted. | WO | 0
10 | transmit_halt | Transmit halt - writing one to this bit resets the tx_go variable and halts the dma from reading more transmit frames into the transmit SRAM buffer. Any frames already read into the transmit SRAM will still be transmitted. | WO | 0
9 | transmit_start | Start transmission - writing one to this bit starts transmission. | WO | 0
8 | back_pressure | Back pressure if set in 10M or 100M half-duplex mode will force collisions on all received frames. Ignored in gigabit half-duplex mode. | RW | 0
7 | stats_write_en | Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes. | RW | 0
6 | inc_all_stats_regs | Incremental statistics registers - this bit is write only. Writing a one increments all the statistics registers by one for test purposes. | WO | 0
5 | clear_all_stats_regs | Clear statistics registers - this bit is write only. Writing a one clears the statistics registers. | WO | 0
4 | man_port_en | Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low. | RW | 0
3 | enable_transmit | Transmit enable - when set, it enables the GEM transmitter to send data. When reset transmission will stop immediately, the transmit pipeline and control registers will be cleared and the transmit queue pointer register will reset to point to the start of the transmit descriptor list. This bit needs to be set before bit 9 the start transmission bit. (Setting this bit low resets the transmit queue pointer however reading the transmit queue pointer register through the APB interface may still return an old value until transmission is restarted.) | RW | 0
2 | enable_receive | Receive enable - when set, it enables the GEM to receive data. When reset frame reception will stop immediately and the receive pipeline will be cleared. The receive queue pointer register is unaffected. | RW | 0
1 | loopback_local | Loopback local - asserts the loopback_local signal to the system clock generator. Also connects txd to rxd, tx_en to rx_dv and forces full duplex mode. If the GEM configuration contains the PCS then bit 11 of the network configuration register must be set low to disable TBI mode when in internal loopback. rx_clk and tx_clk may malfunction as the GEM is switched into and out of internal loopback. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loopback. Local loopback functionality is optional and may not be supported by some instantiations of the GEM. | RW | 0
0 | loopback | Loopback - controls the loopback output pin. | RW | 0

### gem_gxlmicrosemi : network_config

Address offset | 0x0004
Description | The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | uni_direction_enable | Uni-direction-enable. When low the PCS will transmit idle symbols if the link goes down. When high the PCS can transmit frame data when the link is down. | RW | 0
30 | ignore_ipg_rx_er | Ignore IPG rx_er. When set rx_er has no effect on the GEMs operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode. | RW | 0
29 | nsp_accept | Receive bad preamble. When set frames with non-standard preamble are not rejected (the first byte of preamble needs to be 55 and the last D5, bytes other than 55 or D5 may be inserted in between). | RW | 0
28 | ipg_stretch_enable | IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register. | RW | 0
27 | sgmii_mode_enable | SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms. | RW | 0
26 | ignore_rx_fcs | Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be set to zero. | RW | 0
25 | en_half_duplex_rx | Enable frames to be received in half-duplex mode while transmitting. | RW | 0
24 | receive_checksum_offload_enable | Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded. | RW | 0
23 | disable_copy_of_pause_frames | Disable copy of pause frames - set to one to prevent pause frames being copied to memory. When set, neither control frames with type id 8808, nor pause frames with destination address 010000c28001 are copied to memory, this functionality was enhanced in release 1p09. Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required. | RW | 0
22:21 | data_bus_width | Data bus width - set according to AMBA (AHB/AXI) or external FIFO data bus width. The reset value for this can be changed by defining a new value for gem_dma_bus_width_def in gem_defs. Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits., :00: 32 bit data bus width, :01: 64 bit AMBA (AHB/AXI) data bus width, :10: 128 bit AMBA (AHB/AXI) data bus width, :11: invalid, :Note. The reset value of this field is equal to the gem_dma_bus_width_def define, which is user configurable. | RW | 0x1
20:18 | mdc_clock_division | MDC clock division - set according to pclk speed. These three bits determine the number pclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). The reset value for this can be changed by defining a new value for gem_mdc_clock_div in gem_defs.v, :000: divide pclk by 8 (pclk up to 20 MHz), :001: divide pclk by 16 (pclk up to 40 MHz), :010: divide pclk by 32 (pclk up to 80 MHz), :011: divide pclk by 48 (pclk up to 120MHz), :100: divide pclk by 64 (pclk up to 160 MHz), :101: divide pclk by 96 (pclk up to 240 MHz), :110: divide pclk by 128 (pclk up to 320 MHz), :111: divide pclk by 224 (pclk up to 540 MHz)., :Note. The reset value of this field is equal to the gem_mdc_clock_div define, which is user configurable. | RW | 0x2
17 | fcs_remove | FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode. | RW | 0
16 | length_field_error_frame_discard | Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600. | RW | 0
15:14 | receive_buffer_offset | Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer. Note that when the define gem_pbuf_rsc has been set then these bits cannot be used. | RW | 0x0
13 | pause_enable | Pause enable - when set, transmission will pause if a non-zero 802.3 classic pause frame is received and PFC has not been negotiated. | RW | 0
12 | retry_test | Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every rx_clk cycle. | RW | 0
11 | pcs_select | PCS select - selects between MII/GMII and TBI. Must be set for SGMII operation., :0: GMII/MII interface enabled, TBI disabled, :1: TBI enabled, GMII/MII disabled, :(in 802.3br configurations this bit must be set identically in the eMAC and pMAC) | RW | 0
10 | gigabit_mode_enable | Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation., :0: 10/100 operation using MII or TBI interface, :1: Gigabit operation using GMII or TBI interface, :(in 802.3br configurations this bit must be set identically in the eMAC and pMAC) | RW | 0
9 | external_address_match_enable | External address match enable - when set the external address match interface can be used to copy frames to memory. | RW | 0
8 | receive_1536_byte_frames | Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes. | RW | 0
7 | unicast_hash_enable | Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register. | RW | 0
6 | multicast_hash_enable | Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register. | RW | 0
5 | no_broadcast | No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted. | RW | 0
4 | copy_all_frames | Copy all frames - when set to logic one, all valid frames will be accepted. | RW | 0
3 | jumbo_frames | Jumbo frames - set to one to enable jumbo frames up to `gem_jumbo_max_length bytes to be accepted. The default length is 10,240 bytes. | RW | 0
2 | discard_non_vlan_frames | Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic. | RW | 0
1 | full_duplex | Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin. | RW | 0
0 | speed | Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps. The value of this pin is reflected on the speed_mode[0] output pin (in 802.3br configurations this bit has no effect for the eMAC). | RW | 0

### gem_gxlmicrosemi : network_status

Address offset | 0x0008
Description | The network status register returns status information with respect to the PHY management MDIO interface, the PCS, priority flow control, LPI and other status.
Type | RO

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10:9 | link_fault_indication | For 2.5GBASE-X operation these two bits return the state of link_fault in the LFSM defined in Figure 46-11 of IEEE 802.3:, : 00 - OK, : 01 - local fault, : 10 - remote fault, : 11 - link interruption, :If the link fault state machine is not enabled (by setting the 2.5G, AN enable, uni directional enable and tbi control bits) these two bits are set to zero. | RO | 0x0
8 | axi_xaction_outstanding | Outstanding AXI Transactions - This status bit is set when one or more AXI read or write transactions have been issued by the DUT but the responses have not yet been fully collected. | RO | 0
7 | lpi_indicate_pclk | LPI Indication - Low power idle has been detected on receive. This bit is set when LPI is detected and reset when normal idle is detected. An interrupt is generated when the state of this bit changes. | RO | 0
6 | pfc_negotiate_pclk | Set when PFC Priority Based Pause has been negotiated. | RO | 0
5 | mac_pause_tx_en | PCS auto-negotiation pause transmit resolution. | RO | 0
4 | mac_pause_rx_en | PCS auto-negotiation pause receive resolution. | RO | 0
3 | mac_full_duplex | PCS auto-negotiation duplex resolution. Set to one if the resolution function determines that both devices are capable of full duplex operation. If zero half-duplex operation is possible as long as bit 0 (PCS link state) is also one. | RO | 0
2 | man_done | The PHY management logic is idle (i.e. has completed). | RO | 1
1 | mdio_in | Returns status of the mdio_in pin. | RO | 0
0 | pcs_link_state | Returns status of PCS link state. If auto-negotiation is disabled this returns the synchronisation status. If auto-negotiation is enabled it is set in the LINK_OK state as long as a compatible duplex mode is resolved, it is always set in the LINK_OK state in SGMII mode. | RO | 0

### gem_gxlmicrosemi : user_io_register

Address offset | 0x000C
Description | The GEM design provides up to 16 inputs and 16 outputs so that the I/O may be read or set under the control of the processor interface. The number of inputs and outputs are set by the user_in_width and user_out_width verilog macro defines. If the user I/O is disabled as a configuration option, this address space is defined as reserved, and hence will be a read-only register of the value 0x0. If enabled, the number of inputs and outputs can be configured separately. The first output will be represented in bit 0 of the user I/O register, the second output will use bit 1 and so on. The first input will be represented in bit 16 of the user I/O register, the second input will use bit 17 and so on.
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved_31_22 | Reserved, read as 0, ignored on write. | RO | 0x000
21:16 | user_programmable_inputs | User programmable inputs - the upper 16 bits of this register are used to monitor the state of the user inputs. A logic one read from a bit in this range will correspond to the input being in a high state. A logic zero read from a bit in this range will correspond to the input being in a low state. Any unused bits will be read as 0. Writing to any bits in this range will have no functional effect. | RO | 0x00
15:6 | reserved_15_6 | Reserved, read as 0, ignored on write. | RO | 0x000
5:0 | user_programmable_outputs | User programmable outputs - the lower 16 bits of this register are used to control the state of the user outputs. A logic one written to a bit in this range will cause the corresponding output to be set high. A logic zero written to a bit in this range shall cause the corresponding output to be forced low. Any unused bits will be read as logic zero. Writing to any unused bits in this range will have no functional effect. | RW | 0x00

### gem_gxlmicrosemi : dma_config

Address offset | 0x0010
Description | DMA Configuration Register
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved_31 | Reserved, read as 0, ignored on write. | RO | 0
30 | dma_addr_bus_width_1 | DMA address bus width. 0 = 32b, 1 = 64b. | RW | 0
29 | tx_bd_extended_mode_en | Enable TX extended BD mode. See TX BD control register definition for description of feature. | RW | 0
28 | rx_bd_extended_mode_en | Enable RX extended BD mode. See RX BD control register definition for description of feature. | RW | 0
27 | reserved_27 | Reserved, read as 0, ignored on write. | RO | 0
26 | force_max_amba_burst_tx | Force max length bursts on TX. Force the TX DMA to always issue max length bursts on EOP (end of packet) or EOB (end of buffer) transfers as defined by bits 4:0 of this register, even when there is less than max burst data bytes to read. Residual data read is ignored. AHB only - does not apply on AXI bursts (prior to release 1p10) or bursts that break 1k boundary rule - supported on AXI from release 1p10. | RW | 0
25 | force_max_amba_burst_rx | Force max length bursts on RX. Force the RX DMA to always issue max length bursts on EOP (end of packet) or EOB (end of buffer) transfers, even if there is less than max burst real packet data required to write. Any extra bytes of pad data is set to 0x00. AHB only - does not apply on AXI bursts (prior to release 1p10) or bursts that break 1k boundary rule - supported on AXI from release 1p10. | RW | 0
24 | force_discard_on_err | Auto Discard RX frames during lack of resource. When set, the GEM DMA will automatically discard the next frame (that is the oldest frame) from the receiver packet buffer memory when a receive buffer descriptor is read with its used bit set. When low, then received frames will remain to be stored in the SRAM based packet buffer until AMBA (AHB/AXI) buffer resource next becomes available. In this case if the SRAM memory fills up then there will be a receive overflow condition and the most recently received frame (that is the newest) will be discarded. A write to this bit is ignored if the DMA is not configured in the packet buffer full store and forward mode. | RW | 0
23:16 | rx_buf_size | DMA receive buffer size in external AMBA (AHB/AXI) system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes., :0x01 corresponds to buffers of 64 bytes, :0x02 corresponds to 128 bytes etc., :For example:, :0x02: 128 byte., :0x18: 1536 byte (1*max length frame/buffer), :0xA0: 10240 byte (1*10K jumbo frame/buffer), :0xFF: 16320 byte , :Note that this value should never be written as zero., :Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. | RW | 0x02
15:14 | reserved_15_14 | Reserved, read as 0, ignored on write. | RO | 0x0
13 | crc_error_report | When the bit is set, bit 16 of the receive buffer descriptor will represent FCS/CRC error (only if frames with FCS are copied to memory as enabled by bit 26 in the network config register). When this bit is clear, bit 16 of the receive buffer descriptor will represent the Canonical format indicator (CFI) bit as extracted from the receive frame (if the receive buffer descriptor is pointing to the last data buffer of the receive frame and the received frame was VLAN tagged). | RW | 0
12 | infinite_last_dbuf_size_en | Forces the receive DMA to consider the data buffer pointed to by last descriptor in the descriptor list to be of elastic size (the last descriptor is the one with its wrap bit set). This means the first buffer pointed to in the list will always contain the beginning of a frame (this helps if there is a desire to build custom logic that interfaces with the receive buffer directly without software intervention). When set the rx_buf_size bits 23:16 in the dma configuration register are ignored for the last receive buffer in the descriptor list and data will be written into the buffer sequentially until the frame is completely received and the buffer descriptor status will be updated with the frame length as normal. | RW | 0
11 | tx_pbuf_tcp_en | Transmitter IP, TCP and UDP checksum generation offload enable (not supported when in TX Partial Store and Forward mode). When set, the transmitter checksum generation engine is enabled, to calculate and substitute checksums for transmit frames. When clear, frame data is unaffected. If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as 0, ignored on write. | RW | 0
10 | tx_pbuf_size | Transmitter packet buffer memory size select. Having this bit at zero halves the amount of memory used for the transmit packet buffer. This reduces the amount of memory used by the GEM. It is important to set this bit to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 4 Kbytes., :1: Use full configured addressable space (4 Kb), :0: Do not use top address bit (2 Kb), :If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as 0, ignored on write., :Note. The reset value of this field is equal to the gem_tx_pbuf_size_def define, which is user configurable. | RW | 1
9:8 | rx_pbuf_size | Receiver packet buffer memory size select. Having these bits at less than 11 reduces the amount of memory used for the receive packet buffer. This reduces the amount of memory used by the GEM. It is important to set these bits both to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 8 Kbytes., :11: Use full configured addressable space (8 Kb), :10: Do not use top address bit (4 Kb), :01: Do not use top two address bits (2 Kb), :00: Do not use top three address bits (1 Kb), :If the GEM is not configured to use the DMA packet buffer, these bits are not implemented and will be treated as reserved, read as 0, ignored on write., :Note. The reset value of this field is equal to the gem_rx_pbuf_size_def define, which is user configurable. | RW | 0x3
7 | endian_swap_packet | endian swap mode enable for packet data accesses. When set, selects swapped endianism for AMBA (AHB/AXI) transfers. When clear, selects little endian mode. | RW | 0
6 | endian_swap_management | endian swap mode enable for management descriptor accesses. When set, selects swapped endianism for AMBA (AHB/AXI) transfers. When clear, selects little endian mode. | RW | 0
5 | hdr_data_splitting_en | Enable header data Splitting. When set, receive frames will be forwarded to main memory using a minimum of two DMA data buffers. The first X data buffers will contain the frame header, consisting of the Ethernet,VLAN,(IPv4 or IPv6),(TCP or UDP). X= (frame header size divided by rx_buf_size as defined in bits 23:16 of this register). The last Y data buffers will contain the frame payload. Y= (frame payload size divided by rx_buf_size). Note that for non VLAN/IP/TCP/UDP frames, the header will always be 14 bytes. When this feature is disabled, the frame is forwarded to main memory in blocks of rx_buf_size. | RW | 0
4:0 | amba_burst_length | Selects the burst length to use on the AMBA (AHB/AXI) when transferring frame data. Not used for DMA management operations and only used where space and data size allow and respecting AXI/AHB burst boundary rules. One-hot priority encoding enforced automatically on register writes as follows, where x represents don't care:, :1xxxx: Attempt to use bursts of up to 16., :01xxx: Attempt to use bursts of up to 8., :001xx: Attempt to use bursts of up to 4., :0001x: Always use SINGLE bursts., :00001: Always use SINGLE bursts., :00000: Attempt to use bursts of up to 256. | RW | 0x04

### gem_gxlmicrosemi : transmit_status

Address offset | 0x0014
Description | This register, when read, provides details of the status of the transmit path. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | tx_dma_lockup_detected | TX DMA lockup detected - set when lockup has been detected the transmit DMA lockup monitor. | RW W1toClr | 0
9 | tx_mac_lockup_detected | TX MAC lockup detected - set when lockup has been detected by the lockup monitor on the MAC transmit path. | RW W1toClr | 0
8 | resp_not_ok | bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit. | RW W1toClr | 0
7 | late_collision_occurred | Late collision occurred - only set if the condition occurs in gigabit mode, as retry is not attempted. Cleared by writing a one to this bit. | RW W1toClr | 0
6 | transmit_under_run | Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable. This bit is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for internal FIFO mode, this bit is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because a used bit was read. When using the DMA interface configured for packet buffer mode, this bit will never be set. When using the external FIFO interface, this bit is also set when the tx_r_underflow input is asserted during a frame transfer. Cleared by writing a 1. | RW W1toClr | 0
5 | transmit_complete | Transmit complete - set when a frame has been transmitted. Cleared by writing a one to this bit. | RW W1toClr | 0
4 | amba_error | Transmit frame corruption due to AMBA (AHB/AXI) errors. Set if an error occurs whilst midway through reading transmit frame from external memory including HRESP(AHB), RRESP or BRESP(AXI) errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Some AXI errors cause immediate reset of the transmit MAC datapath, in these cases tx_er will not be asserted and this bit will not be set. Cleared by writing a one to this bit. | RW W1toClr | 0
3 | transmit_go | Transmit go - if high transmit is active. When using the exposed FIFO interface, this bit represents the transmit enable bit (bit 3) of the network control register. When using the DMA interface this bit represents the tx_go variable as specified in the transmit buffer description. | RO | 0
2 | retry_limit_exceeded | Retry limit exceeded - cleared by writing a one to this bit. | RW W1toClr | 0
1 | collision_occurred | Collision occurred - set by the assertion of collision. Cleared by writing a one to this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. In gigabit mode, this status is not set for a late collision. | RW W1toClr | 0
0 | used_bit_read | Used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit. | RW W1toClr | 0

### gem_gxlmicrosemi : receive_q_ptr

Address offset | 0x0018
Description | This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | dma_rx_q_ptr | Receive buffer queue base address - written with the address of the start of the receive queue. | RW | 0x0000 0000
1 | reserved_1 | Reserved, read as 0, ignored on write. | RO | 0
0 | dma_rx_dis_q | Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled. | RW | 0

### gem_gxlmicrosemi : transmit_q_ptr

Address offset | 0x001C
Description | This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | dma_tx_q_ptr | Transmit buffer queue base address - written with the address of the start of the transmit queue. | RW | 0x0000 0000
1 | reserved_1 | Reserved, read as 0, ignored on write. | RO | 0
0 | dma_tx_dis_q | Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. | RW | 0

### gem_gxlmicrosemi : receive_status

Address offset | 0x0020
Description | This register, when read provides details of the status of the receive path. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved_31_6 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
5 | rx_dma_lockup_detected | RX DMA lockup detected - set when lockup has been detected the receive DMA lockup monitor. | RW W1toClr | 0
4 | rx_mac_lockup_detected | RX MAC lockup detected - set when lockup has been detected by the lockup monitor on the MAC receive path. | RW W1toClr | 0
3 | resp_not_ok | bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit. | RW W1toClr | 0
2 | receive_overrun | Receive overrun - this bit is set if either the gem_dma RX FIFO or external RX FIFO were unable to store the receive frame due to a FIFO overflow, or if the receive status, reported by the gem_rx module to the gem_dma was not taken at end of frame. This bit is also set in DMA packet buffer mode if the packet buffer overflows. For DMA operation the buffer will be recovered if an overrun occurs. This bit is cleared by writing a one to it. | RW W1toClr | 0
1 | frame_received | Frame received - one or more frames have been received and placed in memory. Cleared by writing a one to this bit. | RW W1toClr | 0
0 | buffer_not_available | Buffer not available - an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time an end of frame is received until a valid pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the meantime cleared the status flag. Cleared by writing a one to this bit. | RW W1toClr | 0

### gem_gxlmicrosemi : int_status

Address offset | 0x0024
Description | If not configured for priority queuing, the GEM generates a single interrupt. This register indicates the source of this interrupt. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the ethernet_int signal will be asserted. For test purposes each bit can be set or reset by writing to the interrupt mask register. The default configuration is shown below whereby all bits are reset to zero on read. Changing the validity of the `gem_irq_read_clear define will instead require a one to be written to the appropriate bit in order to clear it. In this mode reading has no effect on the status of the bit.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | tx_lockup_detected | TX lockup detection - set when lockup has been detected by any of the lockup monitors on the transmit datapath. | RW W1toClr | 0
30 | rx_lockup_detected | RX lockup detection - set when lockup has been detected by any of the lockup monitors on the receive datapath. | RW W1toClr | 0
29 | tsu_timer_comparison_interrupt | TSU timer comparison interrupt. Indicates when TSU timer count value is equal to programmed value. | RW W1toClr | 0
28 | wol_interrupt | WOL interrupt. Indicates a WOL event has been received. | RW W1toClr | 0
27 | receive_lpi_indication_status_bit_change | Receive LPI indication status bit change | RW W1toClr | 0
26 | tsu_seconds_register_increment | TSU seconds register increment indicates the register has incremented. Cleared on read. | RW W1toClr | 0
25 | ptp_pdelay_resp_frame_transmitted | PTP pdelay_resp frame transmitted indicates a PTP pdelay_resp frame has been transmitted. Cleared on read. | RW W1toClr | 0
24 | ptp_pdelay_req_frame_transmitted | PTP pdelay_req frame transmitted indicates a PTP pdelay_req frame has been transmitted. Cleared on read. | RW W1toClr | 0
23 | ptp_pdelay_resp_frame_received | PTP pdelay_resp frame received indicates a PTP pdelay_resp frame has been received. Cleared on read. | RW W1toClr | 0
22 | ptp_pdelay_req_frame_received | PTP pdelay_req frame received indicates a PTP pdelay_req frame has been received. Cleared on read. | RW W1toClr | 0
21 | ptp_sync_frame_transmitted | PTP sync frame transmitted indicates a PTP sync frame has been transmitted. Cleared on read. | RW W1toClr | 0
20 | ptp_delay_req_frame_transmitted | PTP delay_req frame transmitted indicates a PTP delay_req frame has been transmitted. Cleared on read. | RW W1toClr | 0
19 | ptp_sync_frame_received | PTP sync frame received indicates a PTP sync frame has been received. Cleared on read. | RW W1toClr | 0
18 | ptp_delay_req_frame_received | PTP delay_req frame received indicates a PTP delay_req frame has been received. Cleared on read. | RW W1toClr | 0
17 | pcs_link_partner_page_received | PCS link partner page received - set when a new base page or next page is received from the link partner. The first time this interrupt is received, it will indicate base page received and subsequent reads will indicate next pages. The next page and base page registers should only be read when this interrupt is signalled. For next pages, the link partner next page register should be read first to avoid the register being over written. This interrupt also indicates when the host should write a new page into the next page register. If further next page exchange is only required by the link partner, this register should be written with a null message page (0x2001). Cleared on read. | RW W1toClr | 0
16 | pcs_auto_negotiation_complete | PCS auto-negotiation complete - set once the internal PCS layer has completed auto-negotiation. Cleared on read. | RW W1toClr | 0
15 | external_interrupt | External interrupt - set when a rising edge has been detected on the ext_interrupt_in input pin. Cleared on read. | RW W1toClr | 0
14 | pause_frame_transmitted | Pause frame transmitted - indicates a pause frame has been successfully transmitted after being initiated from the network control register or from the tx_pause control pin. Cleared on read. | RW W1toClr | 0
13 | pause_time_elapsed | Pause Time elapsed - set when either the pause time register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field. Not set for PFC pause frames. Cleared on read. | RW W1toClr | 0
12 | pause_frame_with_non_zero_pause_quantum_received | Pause frame with non-zero pause quantum received - indicates a valid legacy pause frame with a non-zero pause quantum field has been received or any valid PFC pause frame has been received. Cleared on read. | RW W1toClr | 0
11 | resp_not_ok | bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared on read. | RW W1toClr | 0
10 | receive_overrun | Receive overrun - set when the receive overrun status bit gets set. Cleared on read. | RW W1toClr | 0
9 | link_change | Link change - set when the PCS link status changes. If auto-negotiation is enabled then link status goes high when it completes. If AN is disabled link status goes high when synchronization is achieved. If 802.3cb link fault signalling is enabled a link change interrupt is triggered when the link fault indication as reported in the network status register changes. Cleared on read. | RW W1toClr | 0
8 | reserved_8 | Reserved, read as 0, ignored on write. | RO | 0
7 | transmit_complete | Transmit complete - set when a frame has been transmitted. Cleared on read. | RW W1toClr | 0
6 | amba_error | Transmit frame corruption due to AMBA (AHB/AXI) error. Set if an error occurs whilst midway through reading transmit frame from external system memory, including HRESP errors(AHB), RRESP or BRESP(AXI) errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Cleared on a read. | RW W1toClr | 0
5 | retry_limit_exceeded_or_late_collision | Retry limit exceeded or late collision - transmit error. Late collision will only cause this status bit to be set in gigabit mode (as a retry is not attempted). Cleared on read. | RW W1toClr | 0
4 | transmit_under_run | Transmit under run - this interrupt is set if the transmitter was forced to terminate a frame that it has already began transmitting due to further data being unavailable. If an under run occurs, the transmitter will force bad crc and tx_er high. This interrupt is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for internal FIFO mode, this interrupt is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB/AXI error response was returned by the connected slave, or because a used bit was read. When using the DMA interface configured for packet buffer mode, this bit will never be set. When using the external FIFO interface, this interrupt is also set when the tx_r_underflow input was asserted during a frame transfer. Cleared on read. | RW W1toClr | 0
3 | tx_used_bit_read | TX used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared on read. | RW W1toClr | 0
2 | rx_used_bit_read | RX used bit read - set when a receive buffer descriptor is read with its used bit set. Cleared on read. | RW W1toClr | 0
1 | receive_complete | Receive complete - a frame has been stored in memory. Cleared on read. | RW W1toClr | 0
0 | management_frame_sent | Management frame sent - the PHY management register has completed its operation. Cleared on read. | RW W1toClr | 0

### gem_gxlmicrosemi : int_enable

Address offset | 0x0028
Description | At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | enable_tx_lockup_detected_interrupt | Enable TX lockup detection interrupt. | WO | 0
30 | enable_rx_lockup_detected_interrupt | Enable RX lockup detection interrupt. | WO | 0
29 | enable_tsu_timer_comparison_interrupt | Enable TSU timer comparison interrupt. | WO | 0
28 | enable_wol_event_received_interrupt | Enable WOL event received interrupt | WO | 0
27 | enable_rx_lpi_indication_interrupt | Enable RX LPI indication interrupt | WO | 0
26 | enable_tsu_seconds_register_increment | Enable TSU seconds register increment | WO | 0
25 | enable_ptp_pdelay_resp_frame_transmitted | Enable PTP pdelay_resp frame transmitted | WO | 0
24 | enable_ptp_pdelay_req_frame_transmitted | Enable PTP pdelay_req frame transmitted | WO | 0
23 | enable_ptp_pdelay_resp_frame_received | Enable PTP pdelay_resp frame received | WO | 0
22 | enable_ptp_pdelay_req_frame_received | Enable PTP pdelay_req frame received | WO | 0
21 | enable_ptp_sync_frame_transmitted | Enable PTP sync frame transmitted | WO | 0
20 | enable_ptp_delay_req_frame_transmitted | Enable PTP delay_req frame transmitted | WO | 0
19 | enable_ptp_sync_frame_received | Enable PTP sync frame received | WO | 0
18 | enable_ptp_delay_req_frame_received | Enable PTP delay_req frame received | WO | 0
17 | enable_pcs_link_partner_page_received | Enable PCS link partner page received | WO | 0
16 | enable_pcs_auto_negotiation_complete_interrupt | Enable PCS auto-negotiation complete interrupt | WO | 0
15 | enable_external_interrupt | Enable external interrupt | WO | 0
14 | enable_pause_frame_transmitted_interrupt | Enable pause frame transmitted interrupt | WO | 0
13 | enable_pause_time_zero_interrupt | Enable pause time zero interrupt | WO | 0
12 | enable_pause_frame_with_non_zero_pause_quantum_interrupt | Enable pause frame with non-zero pause quantum interrupt | WO | 0
11 | enable_resp_not_ok_interrupt | Enable bresp/hresp not OK interrupt | WO | 0
10 | enable_receive_overrun_interrupt | Enable receive overrun interrupt | WO | 0
9 | enable_link_change_interrupt | Enable link change interrupt | WO | 0
8 | reserved_8 | Reserved, read as 0, ignored on write. | RO | 0
7 | enable_transmit_complete_interrupt | Enable transmit complete interrupt | WO | 0
6 | enable_transmit_frame_corruption_due_to_amba_error_interrupt | Enable transmit frame corruption due to AMBA (AHB/AXI) error interrupt | WO | 0
5 | enable_retry_limit_exceeded_or_late_collision_interrupt | Enable retry limit exceeded or late collision interrupt | WO | 0
4 | enable_transmit_buffer_under_run_interrupt | Enable transmit buffer under run interrupt | WO | 0
3 | enable_transmit_used_bit_read_interrupt | Enable transmit used bit read interrupt | WO | 0
2 | enable_receive_used_bit_read_interrupt | Enable receive used bit read interrupt | WO | 0
1 | enable_receive_complete_interrupt | Enable receive complete interrupt | WO | 0
0 | enable_management_done_interrupt | Enable management done interrupt | WO | 0

### gem_gxlmicrosemi : int_disable

Address offset | 0x002C
Description | Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | disable_tx_lockup_detected_interrupt | Disable TX lockup detection interrupt. | WO | 0
30 | disable_rx_lockup_detected_interrupt | Disable RX lockup detection interrupt. | WO | 0
29 | disable_tsu_timer_comparison_interrupt | Disable TSU timer comparison interrupt. | WO | 0
28 | disable_wol_event_received_interrupt | Disable WOL event received interrupt | WO | 0
27 | disable_rx_lpi_indication_interrupt | Disable RX LPI indication interrupt | WO | 0
26 | disable_tsu_seconds_register_increment | Disable TSU seconds register increment | WO | 0
25 | disable_ptp_pdelay_resp_frame_transmitted | Disable PTP pdelay_resp frame transmitted | WO | 0
24 | disable_ptp_pdelay_req_frame_transmitted | Disable PTP pdelay_req frame transmitted | WO | 0
23 | disable_ptp_pdelay_resp_frame_received | Disable PTP pdelay_resp frame received | WO | 0
22 | disable_ptp_pdelay_req_frame_received | Disable PTP pdelay_req frame received | WO | 0
21 | disable_ptp_sync_frame_transmitted | Disable PTP sync frame transmitted | WO | 0
20 | disable_ptp_delay_req_frame_transmitted | Disable PTP delay_req frame transmitted | WO | 0
19 | disable_ptp_sync_frame_received | Disable PTP sync frame received | WO | 0
18 | disable_ptp_delay_req_frame_received | Disable PTP delay_req frame received | WO | 0
17 | disable_pcs_link_partner_page_received | Disable PCS link partner page received | WO | 0
16 | disable_pcs_auto_negotiation_complete_interrupt | Disable PCS auto-negotiation complete interrupt | WO | 0
15 | disable_external_interrupt | Disable external interrupt | WO | 0
14 | disable_pause_frame_transmitted_interrupt | Disable pause frame transmitted interrupt | WO | 0
13 | disable_pause_time_zero_interrupt | Disable pause time zero interrupt | WO | 0
12 | disable_pause_frame_with_non_zero_pause_quantum_interrupt | Disable pause frame with non-zero pause quantum interrupt | WO | 0
11 | disable_resp_not_ok_interrupt | Disable bresp/hresp not OK interrupt | WO | 0
10 | disable_receive_overrun_interrupt | Disable receive overrun interrupt | WO | 0
9 | disable_link_change_interrupt | Disable link change interrupt | WO | 0
8 | reserved_8 | Reserved, read as 0, ignored on write. | RO | 0
7 | disable_transmit_complete_interrupt | Disable transmit complete interrupt | WO | 0
6 | disable_transmit_frame_corruption_due_to_amba_error_interrupt | Disable transmit frame corruption due to AMBA (AHB/AXI) error interrupt | WO | 0
5 | disable_retry_limit_exceeded_or_late_collision_interrupt | Disable retry limit exceeded or late collision interrupt | WO | 0
4 | disable_transmit_buffer_under_run_interrupt | Disable transmit buffer under run interrupt | WO | 0
3 | disable_transmit_used_bit_read_interrupt | Disable transmit used bit read interrupt | WO | 0
2 | disable_receive_used_bit_read_interrupt | Disable receive used bit read interrupt | WO | 0
1 | disable_receive_complete_interrupt | Disable receive complete interrupt | WO | 0
0 | disable_management_done_interrupt | Disable management done interrupt | WO | 0

### gem_gxlmicrosemi : int_mask

Address offset | 0x0030
Description | The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.
Type | RO

Bits | Field Name | Description | Type | Reset
31 | tx_lockup_detected_mask | TX lockup interrupt mask. | RO | 1
30 | rx_lockup_detected_mask | RX lockup interrupt mask. | RO | 1
29 | tsu_timer_comparison_mask | Enable TSU timer comparison interrupt mask. | RO | 1
28 | wol_event_received_mask | A read of this register returns the value of the WOL event received mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
27 | rx_lpi_indication_mask | A read of this register returns the value of the RX LPI indication mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written | RO | 1
26 | tsu_seconds_register_increment_mask | A read of this register returns the value of the TSU seconds register increment mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
25 | ptp_pdelay_resp_frame_transmitted_mask | A read of this register returns the value of the PTP pdelay_resp frame transmitted mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
24 | ptp_pdelay_req_frame_transmitted_mask | A read of this register returns the value of the PTP pdelay_req frame transmitted mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
23 | ptp_pdelay_resp_frame_received_mask | A read of this register returns the value of the PTP pdelay_resp frame received mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
22 | ptp_pdelay_req_frame_received_mask | A read of this register returns the value of the PTP pdelay_req frame received mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
21 | ptp_sync_frame_transmitted_mask | A read of this register returns the value of the PTP sync frame transmitted mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
20 | ptp_delay_req_frame_transmitted_mask | A read of this register returns the value of the PTP delay_req frame transmitted mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
19 | ptp_sync_frame_received_mask | A read of this register returns the value of the PTP sync frame received mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
18 | ptp_delay_req_frame_received_mask | A read of this register returns the value of the PTP delay_req frame received mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
17 | pcs_link_partner_page_mask | A read of this register returns the value of the PCS link partner page mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
16 | pcs_auto_negotiation_complete_interrupt_mask | A read of this register returns the value of the PCS auto-negotiation complete interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
15 | external_interrupt_mask | External interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
14 | pause_frame_transmitted_interrupt_mask | Pause frame transmitted interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
13 | pause_time_zero_interrupt_mask | Pause time zero interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
12 | pause_frame_with_non_zero_pause_quantum_interrupt_mask | Pause frame with non-zero pause quantum interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
11 | resp_not_ok_interrupt_mask | bresp/hresp not OK interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
10 | receive_overrun_interrupt_mask | Receive overrun interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
9 | link_change_interrupt_mask | A read of this register returns the value of the link change interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
8 | reserved_8 | Reserved, read as 0, ignored on write. | RO | 0
7 | transmit_complete_interrupt_mask | Transmit complete interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
6 | amba_error_interrupt_mask | Transmit frame corruption due to AMBA (AHB/AXI) error interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
5 | retry_limit_exceeded_or_late_collision_mask | A read of this register returns the value of the retry limit exceeded or late collision (gigabit mode only) interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
4 | transmit_buffer_under_run_interrupt_mask | Transmit buffer under run interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
3 | transmit_used_bit_read_interrupt_mask | Transmit used bit read interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
2 | receive_used_bit_read_interrupt_mask | Receive used bit read interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
1 | receive_complete_interrupt_mask | Receive complete interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
0 | management_done_interrupt_mask | Management done interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1

### gem_gxlmicrosemi : phy_management

Address offset | 0x0034
Description | The PHY management register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete, when MDC is set for pclk divide by 32 in the network configuration register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1. For a description of MDC generation, see Network Configuration Register.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | write0 | Must be written with 0. | RW | 0
30 | write1 | Must be written to 1 for a valid Clause 22 frame and to 0 for a valid Clause 45 frame. | RW | 0
29:28 | operation | Operation. For a Clause 45 frame: 00 is an addr, 01 is a write, 10 is a post read increment, 11 is a read frame. For a Clause 22 frame: 10 is a read, 01 is a write. | RW | 0x0
27:23 | phy_address | PHY address. | RW | 0x00
22:18 | register_address | Register address - specifies the register in the PHY to access. | RW | 0x00
17:16 | write10 | Must be written with 10. | RW | 0x0
15:0 | phy_write_read_data | For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. | RW | 0x0000

### gem_gxlmicrosemi : pause_time

Address offset | 0x0038
Description | Received Pause Quantum Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | quantum | Received pause quantum - stores the current value of the received pause quantum register which is decremented every 512 bit times. | RO | 0x0000

### gem_gxlmicrosemi : tx_pause_quantum

Address offset | 0x003C
Description | Transmit Pause Quantum Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | quantum_p1 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 1. | RW | 0xFFFF
15:0 | quantum | Transmit pause quantum - written with the pause quantum value for pause frame transmission. | RW | 0xFFFF

### gem_gxlmicrosemi : pbuf_txcutthru

Address offset | 0x0040
Description | Transmit Partial Store and Forward Register. Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. This register contains the enable bit and watermark value for transmit cut-through operation.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | dma_tx_cutthru | Enable TX partial store and forward operation | RW | 0
30:11 | reserved | Reserved, read as 0, ignored on write. | RO | 0x0 0000
10:0 | dma_tx_cutthru_threshold | Watermark value corresponding to number of SRAM locations. This value must be >= 0x14. The actual number of bytes for the watermark is obtained by multiplying the watermark value by the value of the gem_tx_pbuf_data define divided by 8. The reset value depends on the value of the configuration option `gem_tx_pbuf_addr, which is defined in the verilog defs configuration file. The value chosen for the generation of the userguide was `gem_tx_pbuf_addr = 14 | RW | 0x7FF

### gem_gxlmicrosemi : pbuf_rxcutthru

Address offset | 0x0044
Description | Receive Partial Store and Forward Register. Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. This register contains the enable bit and watermark value for receive cut-through operation.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | dma_rx_cutthru | Enable RX partial store and forward operation | RW | 0
30:11 | reserved | Reserved, read as 0, ignored on write. | RO | 0x0 0000
10:0 | dma_rx_cutthru_threshold | Watermark value corresponding to number of SRAM locations. The actual number of bytes for the watermark is obtained by multiplying the watermark value by the value of the gem_rx_pbuf_data define divided by 8. The reset value depends on the value of the configuration option `gem_rx_pbuf_addr, which is defined in the verilog defs configuration file. The value chosen for the generation of the userguide was `gem_rx_pbuf_addr = 11 | RW | 0x7FF

### gem_gxlmicrosemi : jumbo_max_length

Address offset | 0x0048
Description | Maximum Jumbo Frame Size.
Type | RW

Bits | Field Name | Description | Type | Reset
31:14 | reserved_31_14 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
13:0 | jumbo_max_length | Maximum Jumbo Frame Size - resets to the gem_jumbo_max_length define value. | RW | 0x2800

### gem_gxlmicrosemi : axi_max_pipeline

Address offset | 0x0054
Description | Used to set the maximum amount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO (defined in verilog defs.v)
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved | Reserved, read as 0, ignored on write. | RO | 0x0000
16 | use_aw2b_fill | For the write issuing capability as defined in bits 15:8 of this register, select whether the max number of transactions operates between the AW to W AXI channel or the AW to B channel. Set to 0 to operate between the AW and W channels. Set to 1 to operate between the AW and B channels. | RW | 0
15:8 | aw2w_max_pipeline | Defines the maximum number of outstanding AXI write requests that can be issued by the DMA via the AW channel. This is effectively the write issuing capability. | RW | 0x01
7:0 | ar2r_max_pipeline | Defines the maximum number of outstanding AXI read requests that can be issued by the DMA via the AR channel. This is effectively the read issuing capability. | RW | 0x01

### gem_gxlmicrosemi : int_moderation

Address offset | 0x005C
Description | Used to moderate the number of transmit and receive complete interrupts issued. With interrupt moderation enabled receive and transmit interrupts are not generated immediately a frame is transmitted or received. Instead when a receive or transmit event occurs a timer is started and the interrupt is asserted after it times out. This limits the frequency with which the CPU receives interrupts. When interrupt moderation is enabled interrupt status bit one is always used for receive and bit 7 is always used for transmit even when priority queuing is enabled. With interrupt moderation 800ns periods are counted. GEM determines what constitutes an 800ns period by looking at the tbi (bit 11), gigabit bit (10) and speed (bit 0) bits in the network configuration register and counting tx_clk cycles. Bit 0 needs to be set to 1 for 100M operation., :From release 1p11 onwards a frame threshold value may also be used to moderate interrupts. If both time based and frame threshold moderation is enabled the interrupt will be asserted as soon as the first moderation method expires.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | tx_int_mod_thresh | Count of transmitted frames before bit 7 is set in the interrupt status register. A non-zero value indicates transmit interrupt moderation will be performed. | RW | 0x00
23:16 | tx_int_moderation | Count of 800ns periods before bit 7 is set in the interrupt status register after a frame is transmitted. A non-zero value indicates transmit interrupt moderation will be performed. | RW | 0x00
15:8 | rx_int_mod_thresh | Count of received frames before bit 1 is set in the interrupt status register. A non-zero value indicates receive interrupt moderation will be performed. | RW | 0x00
7:0 | rx_int_moderation | Count of 800ns periods before bit 1 is set in the interrupt status register after a frame is received. A non-zero value indicates receive interrupt moderation will be performed. | RW | 0x00

### gem_gxlmicrosemi : sys_wake_time

Address offset | 0x0060
Description | Used to pause transmission after deassertion of tx_lpi_en. Each unit in this register corresponds to 25.6ns in 2.5G mode, 64ns in gigabit mode, 320ns in 100M mode and 3200ns at 10M. After tx_lpi_en is deasserted transmission will pause for the set time.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | sys_wake_time | Count of 25.6ns, 64ns, 320ns or 3200ns intervals before transmission starts after deassertion of tx_lpi_en (each interval is equivalent to eight tx_clk periods and so varies with data rate). | RW | 0x0000

### gem_gxlmicrosemi : lockup_config

Address offset | 0x0068
Description | The lockup detection and recovery configuration register.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | tx_dma_lockup_mon_en | Enable the TX DMA lockup detector. Enable the monitor that detects lockups in the transmit DMA. | RW | 0
30 | tx_mac_lockup_mon_en | Enable the TX MAC lockup detector. Enable the monitor that detects lockups in the MAC transmit path. | RW | 0
29 | rx_dma_lockup_mon_en | Enable the RX DMA lockup detector. Enable the monitor that detects lockups in the receive DMA. | RW | 0
28 | rx_mac_lockup_mon_en | Enable the RX MAC lockup detector. Enable the monitor that detects lockups in the MAC receive path. | RW | 0
27 | lockup_recovery_en | Lockup recovery. If this bit is set then the module will go into a soft reset state if a lockup is detected on the transmit or receive data paths. | RW | 0
26:16 | dma_lockup_time | Prior to release 1p11 this field was reserved. From release 1p11 onwards this field defines the timeout value for transmit and receive DMA lockup detection defined as a multiple of the prescaler value stored in bits 15:0 of this register. | RW | 0x7FF
15:0 | prescaler_value | For release 1p10 this field defined the time (measured in units of 1024 tx_clk periods) after which the lockup detection monitors would trigger, except for the receive MAC lock up detector which had its lockup time register. From release 1p11 onwards this field defines a prescaler value which is the number of tx_clk periods used to scale the timeout registers. | RW | 0xFFFF

### gem_gxlmicrosemi : mac_lockup_time

Address offset | 0x006C
Description | MAC lockup detection time register. For receive this register specifies the maximum time between received frames. If no valid EOP is seen at the receive FIFO interface within the timer period then a lockup is considered to have occurred in the receive MAC. For transmit the MAC lockup time is simply the time it takes for data to be seen on the MII output pins after entering on the MAC FIFO interface.
Type | RW

Bits | Field Name | Description | Type | Reset
31:27 | reserved_31_27 | Reserved, read as 0, ignored on write. | RO | 0x00
26:16 | tx_mac_lockup_time | Prior to release 1p11 this field was reserved. From release 1p11 onwards this field defines the timeout value for transmit MAC lockup detection defined as a multiple of the prescaler value stored in bits 15:0 of the lockup config register. | RW | 0x7FF
15:0 | rx_mac_lockup_time | The time after which the receive MAC lockup detection monitor will trigger. For release 1p10 this was measured in units of 1024 tx_clk periods. From release 1p11 onwards it is used in conjunction with the prescaler stored in bits 15:0 of the lockup config register. | RW | 0xFFFF

### gem_gxlmicrosemi : lockup_config3

Address offset | 0x0070
Description | DMA TX Lockup Enable Control Register. This register enables the lockup timer for each individual queue. If this is set to 0, the number of outstanding packets are still counted but the actual timer does not run.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15 | reserved_15 | Reserved, read as 0, ignored on write. | RO | 0
14 | reserved_14 | Reserved, read as 0, ignored on write. | RO | 0
13 | reserved_13 | Reserved, read as 0, ignored on write. | RO | 0
12 | reserved_12 | Reserved, read as 0, ignored on write. | RO | 0
11 | reserved_11 | Reserved, read as 0, ignored on write. | RO | 0
10 | reserved_10 | Reserved, read as 0, ignored on write. | RO | 0
9 | reserved_9 | Reserved, read as 0, ignored on write. | RO | 0
8 | reserved_8 | Reserved, read as 0, ignored on write. | RO | 0
7 | reserved_7 | Reserved, read as 0, ignored on write. | RO | 0
6 | reserved_6 | Reserved, read as 0, ignored on write. | RO | 0
5 | reserved_5 | Reserved, read as 0, ignored on write. | RO | 0
4 | reserved_4 | Reserved, read as 0, ignored on write. | RO | 0
3 | dma_tx_lockup_en_q_3 | Enable DMA TX lockup timer for queue 3. | RW | 0
2 | dma_tx_lockup_en_q_2 | Enable DMA TX lockup timer for queue 2. | RW | 0
1 | dma_tx_lockup_en_q_1 | Enable DMA TX lockup timer for queue 1. | RW | 0
0 | dma_tx_lockup_en_q_0 | Enable DMA TX lockup timer for queue 0. | RW | 0

### gem_gxlmicrosemi : rx_water_mark

Address offset | 0x007C
Description | rx_water_mark - Receive water mark register. This register contains the high and low water-marks for automatic transmission of pause frames. The water-marks are compared against the internal signal rx_dpram_fill_lvl which is readable in the dpram_fill_dbg register; rx_dpram_fill_lvl indicates the number of words used in the receive SRAM (word length is configuration dependent and may be 4, 8 and 16 bytes). A value of zero in a field disables the corresponding functionality.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | rx_low_watermark | If this field is non-zero and the last pause frame transmitted was non-zero then a zero length pause frame is transmitted when the receive SRAM fill level falls below this value. | RW | 0x0000
15:0 | rx_high_watermark | If this field is non-zero and the receive SRAM fill level exceeds this value then a pause frame is transmitted | RW | 0x0000

### gem_gxlmicrosemi : hash_bottom

Address offset | 0x0080
Description | The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. Hash Register Bottom 31:0.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | The first 32 bits of the hash address register. | RW | 0x0000 0000

### gem_gxlmicrosemi : hash_top

Address offset | 0x0084
Description | Hash Register Top 63:32
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | The remaining 32 bits of the hash address register. | RW | 0x0000 0000

### gem_gxlmicrosemi : spec_add1_bottom

Address offset | 0x0088
Description | The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | Octets 3 to 0 of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. See the MAC Filtering Block of the user guide for more information on how to program this register. | RW | 0x0000 0000

### gem_gxlmicrosemi : spec_add1_top

Address offset | 0x008C
Description | Specific Address Top
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16 | filter_type | This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. | RW | 0
15:0 | address | Specific address 1. Octets 5 and 4 of the destination/source address that is to be compared, that is bits 47:32. See MAC Filtering Block of the user guide for more information. | RW | 0x0000

### gem_gxlmicrosemi : spec_add2_bottom

Address offset | 0x0090
Description | The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | Octets 3 to 0 of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. See the MAC Filtering Block of the user guide for more information on how to program this register. | RW | 0x0000 0000

### gem_gxlmicrosemi : spec_add2_top

Address offset | 0x0094
Description | Specific Address Top
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:24 | filter_byte_mask | When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. | RW | 0x00
23:17 | reserved_23_17 | Reserved, read as 0, ignored on write. | RO | 0x00
16 | filter_type | This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. | RW | 0
15:0 | address | Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. See MAC Filtering Block of the user guide for more information. | RW | 0x0000

### gem_gxlmicrosemi : spec_add3_bottom

Address offset | 0x0098
Description | The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | Octets 3 to 0 of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. See the MAC Filtering Block of the user guide for more information on how to program this register. | RW | 0x0000 0000

### gem_gxlmicrosemi : spec_add3_top

Address offset | 0x009C
Description | Specific Address Top
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:24 | filter_byte_mask | When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. | RW | 0x00
23:17 | reserved_23_17 | Reserved, read as 0, ignored on write. | RO | 0x00
16 | filter_type | This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. | RW | 0
15:0 | address | Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. See MAC Filtering Block of the user guide for more information. | RW | 0x0000

### gem_gxlmicrosemi : spec_add4_bottom

Address offset | 0x00A0
Description | The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | Octets 3 to 0 of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. See the MAC Filtering Block of the user guide for more information on how to program this register. | RW | 0x0000 0000

### gem_gxlmicrosemi : spec_add4_top

Address offset | 0x00A4
Description | Specific Address Top
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:24 | filter_byte_mask | When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. | RW | 0x00
23:17 | reserved_23_17 | Reserved, read as 0, ignored on write. | RO | 0x00
16 | filter_type | This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. | RW | 0
15:0 | address | Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. See MAC Filtering Block of the user guide for more information. | RW | 0x0000

### gem_gxlmicrosemi : spec_type1

Address offset | 0x00A8
Description | Type ID Match 1
Type | RW

Bits | Field Name | Description | Type | Reset
31 | enable_copy | Enable copying of type ID match 1 matched frames. | RW | 0
30:16 | reserved_30_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | match | Type ID match 1. For use in comparisons with received frames type ID/length field. | RW | 0x0000

### gem_gxlmicrosemi : spec_type2

Address offset | 0x00AC
Description | Type ID Match 2
Type | RW

Bits | Field Name | Description | Type | Reset
31 | enable_copy | Enable copying of type ID match 2 matched frames. | RW | 0
30:16 | reserved_30_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | match | Type ID match 2. For use in comparisons with received frames type ID/length field. | RW | 0x0000

### gem_gxlmicrosemi : spec_type3

Address offset | 0x00B0
Description | Type ID Match 3
Type | RW

Bits | Field Name | Description | Type | Reset
31 | enable_copy | Enable copying of type ID match 3 matched frames. | RW | 0
30:16 | reserved_30_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | match | Type ID match 3. For use in comparisons with received frames type ID/length field. | RW | 0x0000

### gem_gxlmicrosemi : spec_type4

Address offset | 0x00B4
Description | Type ID Match 4
Type | RW

Bits | Field Name | Description | Type | Reset
31 | enable_copy | Enable copying of type ID match 4 matched frames. | RW | 0
30:16 | reserved_30_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | match | Type ID match 4. For use in comparisons with received frames type ID/length field. | RW | 0x0000

### gem_gxlmicrosemi : wol_register

Address offset | 0x00B8
Description | Wake on LAN Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:20 | reserved_31_20 | Reserved - read 0, ignored when written. | RO | 0x000
19 | wol_mask_3 | Wake on LAN multicast hash event enable. When set multicast hash events will cause the wol output to be asserted. | RW | 0
18 | wol_mask_2 | Wake on LAN specific address register 1 event enable. When set specific address 1 events will cause the wol output to be asserted. | RW | 0
17 | wol_mask_1 | Wake on LAN ARP request event enable. When set ARP request events will cause the wol output to be asserted. | RW | 0
16 | wol_mask_0 | Wake on LAN magic packet event enable. When set magic packet events will cause the wol output to be asserted. | RW | 0
15:0 | addr | Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event, even if this is matched by the received frame. | RW | 0x0000

### gem_gxlmicrosemi : stretch_ratio

Address offset | 0x00BC
Description | IPG stretch register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | ipg_stretch | IPG Stretch. Bits 7:0 are multiplied with the previously transmitted frame length (including preamble) bits 15:8 +1 divide the frame length. If the resulting number is greater than 96 and bit 28 is set in the network configuration register then the resulting number is used for the transmit inter-packet-gap. 1 is added to bits 15:8 to prevent a divide by zero. | RW | 0x0000

### gem_gxlmicrosemi : stacked_vlan

Address offset | 0x00C0
Description | Stacked VLAN Register
Type | RW

Bits | Field Name | Description | Type | Reset
31 | enable_processing | Enable stacked VLAN processing mode | RW | 0
30:16 | reserved_30_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | match | User defined VLAN_TYPE field. When Stacked VLAN is enabled, the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type (0x8100). Note that the second VLAN tag of a Stacked VLAN packet will only be matched correctly if its VLAN_TYPE field equals 0x8100. | RW | 0x0000

### gem_gxlmicrosemi : tx_pfc_pause

Address offset | 0x00C4
Description | Transmit PFC Pause Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:8 | vector | Priority Vector Pause Size. If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8], the PFC pause frame's pause quantum field associated with that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit PFC Pause Register [15:8], the pause quantum associated with that entry will be zero. | RW | 0x00
7:0 | vector_enable | Priority Vector Enable. If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0]. | RW | 0x00

### gem_gxlmicrosemi : mask_add1_bottom

Address offset | 0x00C8
Description | Specific Address Mask 1 Bottom 31:0
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address_mask | Specific Address Mask. Setting a bit to one masks the corresponding bit in the specific address 1 register | RW | 0x0000 0000

### gem_gxlmicrosemi : mask_add1_top

Address offset | 0x00CC
Description | Specific Address Mask 1 Top 47:32
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | address_mask | Specific Address Mask. Setting a bit to one masks the corresponding bit in the specific address 1 register | RW | 0x0000

### gem_gxlmicrosemi : dma_addr_or_mask

Address offset | 0x00D0
Description | Receive DMA Data Buffer Address Mask - only applies to AHB operation
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | mask_value | Data Buffer Address Mask Value. Values used to force bits 31:28 of the receive data buffer AHB address to a particular value when the associated enable bits stored in this register [3:0] are set. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external system memory. | RW | 0x0
27:4 | reserved_27_4 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
3:0 | mask_enable | Data Buffer Address Mask Enable. These bits are associated directly with bits[31:28].When bit 0 is set, the AHB address bit 28 used for accessing the receive data buffers will be forced to the value stored in bit 28 of this register. When bit 1 is set, the AHB address bit 29 used for accessing the receive data buffers will be forced to the value stored in bit 29 of this register. When bit 2 is set, the AHB address bit 30 used for accessing the receive data buffers will be forced to the value stored in bit 30 of this register. When bit 3 is set, the AHB address bit 31 used for accessing the receive data buffers will be forced to the value stored in bit 31 of this register. When these bits are clear, the associated value stored in bits 31:28 have no effect on the AHB address used for receive data buffer accesses. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external memory. | RW | 0x0

### gem_gxlmicrosemi : rx_ptp_unicast

Address offset | 0x00D4
Description | PTP RX unicast IP destination address
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | Unicast IP destination address. Used for detection of PTP frames on receive path. | RW | 0x0000 0000

### gem_gxlmicrosemi : tx_ptp_unicast

Address offset | 0x00D8
Description | PTP TX unicast IP destination address
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | Unicast IP destination address. Used for detection of PTP frames on transmit path. | RW | 0x0000 0000

### gem_gxlmicrosemi : tsu_nsec_cmp

Address offset | 0x00DC
Description | TSU timer comparison value nanoseconds
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved_31_22 | Reserved, read as 0, ignored on write. | RO | 0x000
21:0 | comparison_value | TSU timer comparison value (ns). Value is compared to the bits[45:24] of the TSU timer count value (upper 22 bits of nanosecond value). The output tsu_timer_cmp_val is driven high when the timer comparison values match the TSU count value. From release 1p11 onwards this comparison only occurs once the nanosecond compare register has been written and when the match occurs tsu_timer_cmp_val will only be driven high for a single tsu_clk period. | RW | 0x00 0000

### gem_gxlmicrosemi : tsu_sec_cmp

Address offset | 0x00E0
Description | TSU timer comparison value seconds 31:0
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | comparison_value | TSU timer comparison value (s). Value is compared to seconds value bits [31:0] of the TSU timer count value. | RW | 0x0000 0000

### gem_gxlmicrosemi : tsu_msb_sec_cmp

Address offset | 0x00E4
Description | TSU timer comparison value seconds 47:32
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | comparison_value | TSU timer comparison value (s). Value is compared to the top 16 bits (most significant 16-bits [47:32] of seconds value) of the TSU timer count value. | RW | 0x0000

### gem_gxlmicrosemi : tsu_ptp_tx_msb_sec

Address offset | 0x00E8
Description | PTP Event Frame Transmitted Seconds Register 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | timer_seconds | PTP Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. | RO | 0x0000

### gem_gxlmicrosemi : tsu_ptp_rx_msb_sec

Address offset | 0x00EC
Description | PTP Event Frame Received Seconds Register 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | timer_seconds | PTP Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. | RO | 0x0000

### gem_gxlmicrosemi : tsu_peer_tx_msb_sec

Address offset | 0x00F0
Description | PTP Peer Event Frame Transmitted Seconds Register 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | timer_seconds | PTP Peer Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. | RO | 0x0000

### gem_gxlmicrosemi : tsu_peer_rx_msb_sec

Address offset | 0x00F4
Description | PTP Peer Event Frame Received Seconds Register 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | timer_seconds | PTP Peer Event Frame RX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. | RO | 0x0000

### gem_gxlmicrosemi : dpram_fill_dbg

Address offset | 0x00F8
Description | The fill levels for the TX and RX packet buffer SRAMs can be read using this register, including the fill level for each queue in the TX direction. The fill level is reported as the number of word locations used. The number of bytes will depend on the SRAM data width.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | dma_tx_rx_fill_level | Fill Level - TX or RX packet buffer fill level, selected by the tx_q_fill_level_select and tx_rx_fill_level_select registers. Read this register to determine the fill level. | RO | 0x0000
15:8 | reserved_15_8 | Reserved, read as 0, ignored on write. | RO | 0x00
7:4 | dma_tx_q_fill_level_select | TX queue fill level select - select what TX queue to report fill levels for. | RW | 0x0
3:1 | reserved_3_1 | Reserved, read as 0, ignored on write. | RO | 0x0
0 | dma_tx_rx_fill_level_select | TX/RX Fill Level select - report the fill level for the TX or RX packet buffer. Set 1 for transmit and 0 for receive. | RW | 0

### gem_gxlmicrosemi : revision_reg

Address offset | 0x00FC
Description | This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | fix_number | Fix number - incremented for fix releases. | RO | 0x0
27:16 | module_identification_number | Module identification number - for the GEM, this value is fixed. | RO | 0x107
15:0 | module_revision | Module revision - fixed value specific to the revision of the design which is incremented for each non-fix release of the IP. | RO | 0x010C

### gem_gxlmicrosemi : octets_txed_bottom

Address offset | 0x0100
Description | These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. In order to reduce overall design area, the statistics registers may be optionally removed in the configuration file if they are deemed unnecessary for a particular design. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. The statistics registers optionally have a snapshot capability which, when exercised, will simultaneously store and clear the current values of all the statistics registers into a snapshot register set in order to allow a consistent set of statistics to be read by the processor. The snapshot is controlled using bit 13 of the network control register. The read snapshot control indicated by bit 14 of the network control register determines whether the processor reads the snapshot registers (logic 1) or the incrementing registers (logic 0). The default GEM configuration does not support the snapshot capability. See Parameterization section under Implementation Application Notes for an explanation of how to enable this function. All the statistics registers are read only. For test purposes they may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared. When reading the octets transmitted and octets received registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. The statistics register block contains the following registers. Octets Transmitted [31:0]
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Transmitted octets in frame without errors [31:0]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : octets_txed_top

Address offset | 0x0104
Description | Octets Transmitted 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | count | Transmitted octets in frame without errors [47:32]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : frames_txed_ok

Address offset | 0x0108
Description | Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Frames transmitted without error. A 32 bit register counting the number of frames successfully transmitted, i.e. no under run and not too many retries. Excludes pause frames. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : broadcast_txed

Address offset | 0x010C
Description | Broadcast Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Broadcast frames transmitted without error. A 32 bit register counting the number of broadcast frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : multicast_txed

Address offset | 0x0110
Description | Multicast Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Multicast frames transmitted without error. A 32 bit register counting the number of multicast frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : pause_frames_txed

Address offset | 0x0114
Description | Pause Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | count | Transmitted pause frames - a 16 bit register counting the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins or automatically when rx_water_mark is reached are counted as pause frames. Pause frames received through the external FIFO interface are counted in the frames transmitted counter. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : frames_txed_64

Address offset | 0x0118
Description | 64 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 64 byte frames transmitted without error. A 32 bit register counting the number of 64 byte frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : frames_txed_65

Address offset | 0x011C
Description | 65 to 127 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 65 to127 byte frames transmitted without error. A 32 bit register counting the number of 65 to127 byte frames successfully transmitted without error, i.e. no under run and not too many retries. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : frames_txed_128

Address offset | 0x0120
Description | 128 to 255 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 128 to 255 byte frames transmitted without error. A 32 bit register counting the number of 128 to 255 byte frames successfully transmitted without error, i.e. no under run and not too many retries. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : frames_txed_256

Address offset | 0x0124
Description | 256 to 511 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 256 to 511 byte frames transmitted without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error, i.e. no under run and not too many retries. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : frames_txed_512

Address offset | 0x0128
Description | 512 to 1023 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 512 to 1023 byte frames transmitted without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully transmitted without error, i.e. no under run and not too many retries. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : frames_txed_1024

Address offset | 0x012C
Description | 1024 to 1518 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 1024 to 1518 byte frames transmitted without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully transmitted without error, i.e. no under run and not too many retries. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : frames_txed_1519

Address offset | 0x0130
Description | Greater Than 1518 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Greater than 1518 byte frames transmitted without error. A 32 bit register counting the number of 1518 or above byte frames successfully transmitted without error, i.e. no under run and not too many retries. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : tx_underruns

Address offset | 0x0134
Description | Transmit Under Runs
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Transmit under runs - a 10 bit register counting the number of frames not transmitted due to a transmit under run. If this register is incremented then no other statistics register is incremented. | RO RtoClr | 0x000

### gem_gxlmicrosemi : single_collisions

Address offset | 0x0138
Description | Single Collision Frames
Type | RO

Bits | Field Name | Description | Type | Reset
31:18 | reserved_31_18 | Reserved, read as 0, ignored on write. | RO | 0x0000
17:0 | count | Single collision frames - an 18 bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no under run. | RO RtoClr | 0x0 0000

### gem_gxlmicrosemi : multiple_collisions

Address offset | 0x013C
Description | Multiple Collision Frames
Type | RO

Bits | Field Name | Description | Type | Reset
31:18 | reserved_31_18 | Reserved, read as 0, ignored on write. | RO | 0x0000
17:0 | count | Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no under run and not too many retries. | RO RtoClr | 0x0 0000

### gem_gxlmicrosemi : excessive_collisions

Address offset | 0x0140
Description | Excessive Collisions
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Excessive collisions - a 10 bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions. | RO RtoClr | 0x000

### gem_gxlmicrosemi : late_collisions

Address offset | 0x0144
Description | Late Collisions
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Late collisions - a 10 bit register counting the number of late collision occurring after the slot time (512 bits) has expired. In 10/100 mode, late collisions are counted twice i.e. both as a collision and a late collision. In gigabit mode, a late collision causes the transmission to be aborted, thus the single and multi collision registers are not updated. | RO RtoClr | 0x000

### gem_gxlmicrosemi : deferred_frames

Address offset | 0x0148
Description | Deferred Transmission Frames
Type | RO

Bits | Field Name | Description | Type | Reset
31:18 | reserved_31_18 | Reserved, read as 0, ignored on write. | RO | 0x0000
17:0 | count | Deferred transmission frames - an 18 bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit under run. | RO RtoClr | 0x0 0000

### gem_gxlmicrosemi : crs_errors

Address offset | 0x014C
Description | Carrier Sense Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Carrier sense errors - a 10 bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no under run). Only incremented in half-duplex mode. The only effect of a carrier sense error is to increment this register. The behaviour of the other statistics registers is unaffected by the detection of a carrier sense error. | RO RtoClr | 0x000

### gem_gxlmicrosemi : octets_rxed_bottom

Address offset | 0x0150
Description | Octets Received 31:0
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : octets_rxed_top

Address offset | 0x0154
Description | Octets Received 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | count | Received octets in frame without errors [47:32]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : frames_rxed_ok

Address offset | 0x0158
Description | Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Frames received without error. A 32 bit register counting the number of frames successfully received. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : broadcast_rxed

Address offset | 0x015C
Description | Broadcast Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Broadcast frames received without error. A 32 bit register counting the number of broadcast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : multicast_rxed

Address offset | 0x0160
Description | Multicast Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Multicast frames received without error. A 32 bit register counting the number of multicast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : pause_frames_rxed

Address offset | 0x0164
Description | Pause Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | count | Received pause frames - a 16 bit register counting the number of pause frames received without error. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : frames_rxed_64

Address offset | 0x0168
Description | 64 Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 64 byte frames received without error. A 32 bit register counting the number of 64 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : frames_rxed_65

Address offset | 0x016C
Description | 65 to 127 Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 65 to 127 byte frames received without error. A 32 bit register counting the number of 65 to 127 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : frames_rxed_128

Address offset | 0x0170
Description | 128 to 255 Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 128 to 255 byte frames received without error. A 32 bit register counting the number of 128 to 255 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : frames_rxed_256

Address offset | 0x0174
Description | 256 to 511 Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 256 to 511 byte frames received without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : frames_rxed_512

Address offset | 0x0178
Description | 512 to 1023 Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 512 to 1023 byte frames received without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : frames_rxed_1024

Address offset | 0x017C
Description | 1024 to 1518 Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 1024 to 1518 byte frames received without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : frames_rxed_1519

Address offset | 0x0180
Description | 1519 to maximum Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 1519 to maximum byte frames received without error. A 32 bit register counting the number of 1519 byte or above frames successfully received without error. Maximum frame size is determined by the network configuration register bit 8 (1536 maximum frame size) or bit 3 (jumbo frame size). Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : undersize_frames

Address offset | 0x0184
Description | Undersized Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Undersize frames received - a 10 bit register counting the number of frames received less than 64 bytes in length (10/100 mode or gigabit mode, full duplex) that do not have either a CRC error or an alignment error. In gigabit mode, half-duplex, this register counts either frames not conforming to the minimum slot time of 512 bytes or frames not conforming to the minimum frame size once bursting is active. | RO RtoClr | 0x000

### gem_gxlmicrosemi : excessive_rx_length

Address offset | 0x0188
Description | Oversize Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved read 0, ignored on write. | RO | 0x00 0000
9:0 | count | Oversize frames received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 bytes if bit 8 is set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register) in length but do not have either a CRC error, an alignment error nor a receive symbol error. | RO RtoClr | 0x000

### gem_gxlmicrosemi : rx_jabbers

Address offset | 0x018C
Description | Jabbers Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Jabbers received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error. | RO RtoClr | 0x000

### gem_gxlmicrosemi : fcs_errors

Address offset | 0x0190
Description | Frame Check Sequence Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Frame check sequence errors - a 10 bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes. This register is incremented for a frame with bad FCS, regardless of whether it is copied to memory due to ignore FCS mode being enabled in bit 26 of the network configuration register. | RO RtoClr | 0x000

### gem_gxlmicrosemi : rx_length_errors

Address offset | 0x0194
Description | Length Field Frame Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Length field frame errors - this 10-bit register counts the number of frames received that have a measured length shorter than that extracted from the length field (bytes 13 and 14). This condition is only counted if the value of the length field is less than 0x0600, the frame is not of excessive length and checking is enabled through bit 16 of the network configuration register. | RO RtoClr | 0x000

### gem_gxlmicrosemi : rx_symbol_errors

Address offset | 0x0198
Description | Receive Symbol Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Receive symbol errors - a 10-bit register counting the number of frames that had rx_er asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks. For gigabit mode the frame must satisfy slot time requirements in order to count a symbol error. Additionally, in gigabit half-duplex mode, carrier extension errors are also recorded. Receive symbol errors will also be counted as an FCS or alignment error if the frame is between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register, 10240 bytes if bit 3 is set in the network configuration register). If the frame is larger it will be recorded as a jabber error. | RO RtoClr | 0x000

### gem_gxlmicrosemi : alignment_errors

Address offset | 0x019C
Description | Alignment Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Alignment errors - a 10 bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes. | RO RtoClr | 0x000

### gem_gxlmicrosemi : rx_resource_errors

Address offset | 0x01A0
Description | Receive Resource Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:18 | reserved_31_18 | Reserved, read as 0, ignored on write. | RO | 0x0000
17:0 | count | Receive resource errors - an 18 bit register counting the number of times a receive buffer descriptor was read with its used bit set. This can be used as a means of checking the efficiency of the software in processing and releasing receive buffers. In an ideally configured system, this counter would not increase. | RO RtoClr | 0x0 0000

### gem_gxlmicrosemi : rx_overruns

Address offset | 0x01A4
Description | Receive Overruns
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Receive overruns - a 10 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive overrun. | RO RtoClr | 0x000

### gem_gxlmicrosemi : rx_ip_ck_errors

Address offset | 0x01A8
Description | IP Header Checksum Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:0 | count | IP header checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect IP header checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error. | RO RtoClr | 0x00

### gem_gxlmicrosemi : rx_tcp_ck_errors

Address offset | 0x01AC
Description | TCP Checksum Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:0 | count | TCP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect TCP checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error. | RO RtoClr | 0x00

### gem_gxlmicrosemi : rx_udp_ck_errors

Address offset | 0x01B0
Description | UDP Checksum Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:0 | count | UDP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect UDP checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error. | RO RtoClr | 0x00

### gem_gxlmicrosemi : auto_flushed_pkts

Address offset | 0x01B4
Description | Receive DMA Flushed Packets
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | count | Flushed RX packets counter. A 16 bit register counting the number of frames that have been flushed from the receive SRAM based packet buffer due to one of the following reasons:, :1. When either partial store and forward mode, bit 24 of the DMA configuration register, or the drop_on_resource_err mode of the traffic policing feature is active, and a packet is received while there is no AMBA (AHB/AXI) resource (no free descriptors for the DUT to use)., :2. When partial store and forward mode is enabled and an AMBA (AHB/AXI) error is encountered while writing the packet data to external memory., :3. When bit 18 of the network control register (software action to flush a packet from the head of the PBUF queue) is pulsed and the GEM DMA is not currently busy., :4. When a frame is dropped due to the policing actions defined in the rx_qX_flush registers located at 0x0b00-0x0b3c. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : tsu_timer_incr_sub_nsec

Address offset | 0x01BC
Description | 1588 Timer Increment Register sub nsec. From release 1p08f1 onwards this register must be written before the tsu_timer_incr register and the value written will not take effect until the tsu_timer_incr register is written to.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | sub_ns_incr_lsb | These are the least significant bits [7:0] of the sub-ns value by which the 1588 timer will be incremented each clock cycle. | RW | 0x00
23:16 | reserved_23_16 | Reserved, read as 0, ignored on write. | RO | 0x00
15:0 | sub_ns_incr | These are the most significant bits [23:8] of the sub-ns value by which the 1588 timer will be incremented each clock cycle. 24 bits of sub nanosecond precision gives resolution of approximately 5.86E-17 seconds (16 bits gives 15.2 femtoseconds). | RW | 0x0000

### gem_gxlmicrosemi : tsu_timer_msb_sec

Address offset | 0x01C0
Description | 1588 Timer Seconds Register 47:32
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | timer | TSU timer value (s). Most significant 16 bits of seconds timer count. The register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented or decremented when the timer adjust register is written (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF). Note: The value of this register is used only when the lower 32 bit register is written to. This is to ensure a single update of the 48 bit seconds value | RW | 0x0000

### gem_gxlmicrosemi : tsu_strobe_msb_sec

Address offset | 0x01C4
Description | 1588 Timer Sync Strobe Seconds Register 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | strobe | 1588 Timer Sync Strobe Seconds. The most significant 16-bit value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero. | RO | 0x0000

### gem_gxlmicrosemi : tsu_strobe_sec

Address offset | 0x01C8
Description | 1588 Timer Sync Strobe Seconds Register 31:0
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | strobe | 1588 Timer Sync Strobe Seconds. The lowest significant 32-bit value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero. | RO | 0x0000 0000

### gem_gxlmicrosemi : tsu_strobe_nsec

Address offset | 0x01CC
Description | 1588 Timer Sync Strobe Nanoseconds Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:0 | strobe | 1588 Timer Sync Strobe Nanoseconds. The value of the Timer Nanoseconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero. | RO | 0x0000 0000

### gem_gxlmicrosemi : tsu_timer_sec

Address offset | 0x01D0
Description | 1588 Timer Seconds Register 31:0
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | timer | 1588 Timer Seconds Register. TSU timer value (s). Least significant 32 bits of seconds timer count. This register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented or decremented when the timer adjust register is written (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF). | RW | 0x0000 0000

### gem_gxlmicrosemi : tsu_timer_nsec

Address offset | 0x01D4
Description | 1588 Timer Nanoseconds Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:0 | timer | Timer count in nanoseconds. This register is writeable. It can also be adjusted by writes to the 1588 timer adjust register. It increments by the value of the 1588 timer increment register each clock cycle (if this register is close to zero and a write to the timer adjust register causes a decrement the seconds register will be decremented if necessary and the nanoseconds register will roll back to 9999999xx (decimal)). | RW | 0x0000 0000

### gem_gxlmicrosemi : tsu_timer_adjust

Address offset | 0x01D8
Description | This register is used to adjust the value of the timer in the TSU. It allows an integral number of nanoseconds to be added or subtracted from the timer in a one-off operation. This register returns all zeroes when read.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | add_subtract | Write as one to subtract from the 1588 timer. Write as zero to add to it. | WO | 0
30 | reserved_30 | Reserved, read as 0, ignored on write. | RO | 0
29:0 | increment_value | Timer increment value. The number of nanoseconds to increment or decrement the 1588 timer nanoseconds register. If necessary the 1588 seconds register will be incremented or decremented. | WO | 0x0000 0000

### gem_gxlmicrosemi : tsu_timer_incr

Address offset | 0x01DC
Description | 1588 Timer Increment Register. From release 1p08f1 onwards this register must be written after the tsu_timer_incr_sub_ns register and the write operation will cause the value written to the tsu_timer_incr_sub_ns register to take effect.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | num_incs | Number of incs before alt inc. The number of increments after which the alternative increment is used. | RW | 0x00
15:8 | alt_ns_incr | Alternative nanoseconds count. Alternative count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. | RW | 0x00
7:0 | ns_increment | A count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. These are the most significant 8 bits of the 32 bit timer_increment counter. The tsu_timer_incr_sub_nsec register holds the least significant 24 bits of the increment. | RW | 0x00

### gem_gxlmicrosemi : tsu_ptp_tx_sec

Address offset | 0x01E0
Description | PTP Event Frame Transmitted Seconds Register 31:0
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | timer | PTP Event Frame Transmitted Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : tsu_ptp_tx_nsec

Address offset | 0x01E4
Description | PTP Event Frame Transmitted Nanoseconds Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:0 | timer | PTP Event Frame Transmitted Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : tsu_ptp_rx_sec

Address offset | 0x01E8
Description | PTP Event Frame Received Seconds Register 31:0
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | timer | PTP Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : tsu_ptp_rx_nsec

Address offset | 0x01EC
Description | PTP Event Frame Received Nanoseconds Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:0 | timer | PTP Event Frame Received Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : tsu_peer_tx_sec

Address offset | 0x01F0
Description | PTP Peer Event Frame Transmitted Seconds Register 31:0
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | timer | PTP Peer Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : tsu_peer_tx_nsec

Address offset | 0x01F4
Description | PTP Peer Event Frame Transmitted Nanoseconds Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:0 | timer | PTP Peer Event Frame Transmitted Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : tsu_peer_rx_sec

Address offset | 0x01F8
Description | PTP Peer Event Frame Received Seconds Register 31:0
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | timer | PTP Peer Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : tsu_peer_rx_nsec

Address offset | 0x01FC
Description | PTP Peer Event Frame Received Nanoseconds Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:0 | timer | PTP Peer Event Frame Received Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : pcs_control

Address offset | 0x0200
Description | Note: All PCS registers are defined in the IEEE 802.3 Standard. PCS Control Register. This register provides the main control functions with respect to the PCS.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved. Set to zero. | RO | 0x0000
15 | pcs_software_reset | PCS software reset - written by software to force the hardware logic into a reset state. This bit is self-clearing. When reading this bit, logic 1 is returned until both the soft reset has completed and the PCS is enabled through the PCS select bit of the network configuration register. Writing logic 0 has no effect. | RW | 1
14 | loopback_mode | Loopback mode - the ewrap output pin of the GEM reflects this control bit, and can be used to select loopback mode in the PHY transceiver. 0: Loopback mode disabled. 1: Loopback mode enabled. | RW | 0
13 | speed_select_bit_1 | Speed select bit 1 - combined with speed select [0] to indicate the speed of operation of the PCS. As the GEM PCS is only intended to operate at 1000 Mbps, this bit is hardwired to logic 0. | RO | 0
12 | enable_auto_neg | Enable auto-negotiation - when set active high, auto-negotiation operation is enabled. | RW | 1
11:10 | reserved_11_10 | Reserved. Set to zero. | RO | 0x0
9 | restart_auto_neg | Restart auto-negotiation - when set active high, the hardware restarts auto-negotiation. This bit is self-clearing, but once set shall remain in this state until auto-negotiation has restarted. Writing logic 0 has no effect. | RW | 0
8 | mac_duplex_state | MAC Duplex state. This returns the value of the MAC's duplex state as indicated in bit 1 of the MAC's network configuration register. | RO | 0
7 | collision_test | Collision test - when set active high, the PCS generates collisions on transmit. This bit should only be set for test purposes. | RW | 0
6 | speed_select_bit_0 | Speed select bit 0 - combined with speed select [1] to indicate the speed of operation of the PCS. As the GEM PCS is only intended to operate at 1000 Mbps, this bit is hardwired to logic 1. | RO | 1
5:0 | reserved_5_0 | Reserved. Set to zero. | RO | 0x00

### gem_gxlmicrosemi : pcs_status

Address offset | 0x0204
Description | This register indicates general status information concerning the PCS.
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved. Set to zero. | RO | 0x0000
15 | base_100_t4 | 100 BASE-T4 - the GEM PCS does not support 100 BASE-T4. This bit is hardwired to logic 0. | RO | 0
14 | base_100_x_full_duplex | 100 BASE-X full duplex - the GEM PCS does not support 100 BASE-X. This bit is hardwired to logic 0. | RO | 0
13 | base_100_x_half_duplex | 100 BASE-X half-duplex - the GEM PCS does not support 100 BASE-X. This bit is hardwired to logic 0. | RO | 0
12 | mbps_10_full_duplex | 10 Mbps full duplex - the GEM PCS does not support this mode. This bit is hardwired to logic 0. | RO | 0
11 | mbps_10_half_duplex | 10 Mbps half-duplex - the GEM PCS does not support this mode. This bit is hardwired to logic 0. | RO | 0
10 | base_100_t2_full_duplex | 100 BASE-T2 full duplex - the GEM PCS does not support 100 BASE-T2. This bit is hardwired to logic 0. | RO | 0
9 | base_100_t2_half_duplex | 100 BASE-T2 half-duplex - the GEM PCS does not support 100 BASE-T2. This bit is hardwired to logic 0. | RO | 0
8 | extended_status | Extended status - when set active high, indicates extended status information is present in the PCS auto-negotiation extended status register. This bit is hardwired to logic 1. | RO | 1
7:6 | reserved_7_6 | Reserved. Set to zero. | RO | 0x0
5 | auto_neg_complete | Auto-negotiation complete - set active high by the PCS hardware to indicate auto-negotiation has completed. | RO | 0
4 | remote_fault | Remote fault - set active high if the link partner remote fault bits in the PCS auto-negotiation link partner ability register, indicates an error. Resets low when read. | RO | 0
3 | auto_neg_ability | Auto-negotiation ability - this bit indicates whether the PCS has auto-negotiation ability and reflects the value of the auto-negotiation enable bit in the PCS control register. 0: PCS is not able to perform auto-negotiation. 1: PCS is able to perform auto-negotiation. | RO | 1
2 | link_status | Link status - indicates the status of the physical connection to the link partner. When set to logic 1 the link is up, and when set to logic 0, the link is down. If auto-negotiation is disabled this returns the synchronisation status. Held at logic 0 if the link goes down until this bit is read. | RO | 0
1 | reserved_1 | Reserved. Set to zero. | RO | 0
0 | extended_capabilities | Extended register capabilities - when set active high, indicates the PCS supports extended register capabilities. This bit is hardwired to logic 1. | RO | 1

### gem_gxlmicrosemi : pcs_phy_top_id

Address offset | 0x0208
Description | The value of this register indicates the upper 16-bits of the PHY's identification code. This is a read-only register with a value defined by `gem_phy_id_top
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved. Set to zero. | RO | 0x0000
15:0 | id_code | Upper 16-bits of the PHY identification code, corresponding to the fixed identification for the GEM IP. | RO | 0x0107

### gem_gxlmicrosemi : pcs_phy_bot_id

Address offset | 0x020C
Description | The value of this register indicates the lower 16-bits of the PHY's identification code. This is a read-only register with a value defined by `gem_phy_id_bot
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved. Set to zero. | RO | 0x0000
15:0 | id_code | Lower 16-bits of the PHY identification code, corresponding to the revision of the GEM IP, which is incremented after each release of the IP. | RO | 0x010C

### gem_gxlmicrosemi : pcs_an_adv

Address offset | 0x0210
Description | The value of this register is used to transmit the base page of the GEM PCS advertised capabilities as long as SGMII mode is not enabled. If SGMII mode is enabled by setting bit 27 in the network configuration register then this register becomes read only with a fixed value of 0x00000001. (SGMII specifies that the transmit configuration information sent from the MAC to the PHY is fixed with bit 14 set to 1 to indicate acknowledge, bit 0 set to 1 to indicate SGMII and all other bits set to 0.)
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved. Set to zero. | RO | 0x0000
15 | next_page | Next page. When set active high, this bit is used during auto-negotiation to indicate to the link partner that the PCS requires exchanging next pages. | RW | 0
14 | reserved_14 | Reserved. Set to zero. | RO | 0
13:12 | remote_fault | Remote fault [1:0] - indicates and classifies a remote fault condition to the link partner:, :00: No error, Link OK, :01: Link Failure. , :10: Off line. , :11: Auto-negotiation error. | RW | 0x0
11:9 | reserved_11_9 | Reserved. Set to zero. | RO | 0x0
8:7 | pause | Pause[1:0] - used to provide a pause capability mechanism as follows:, :00: No pause. , :01: Symmetric pause. , :10: Asymmetric pause toward link partner. , :11: Both symmetric pause and asymmetric pause toward link device. | RW | 0x0
6 | half_duplex | half-duplex - this bit defines to the link partner whether the GEM is capable of supporting half-duplex operation., :0: The GEM cannot support half-duplex. , :1: The GEM can support half-duplex. | RW | 0
5 | full_duplex | Full duplex - this bit defines to the link partner whether the GEM is capable of supporting full duplex operation. , :0: The GEM cannot support full duplex. , :1: The GEM can support full duplex. | RW | 1
4:0 | reserved_4_0 | Reserved. Set to zero. | RO | 0x00

### gem_gxlmicrosemi : pcs_an_lp_base

Address offset | 0x0214
Description | When SGMII mode is not enabled, the value of this register contains the link partner's base page received information. This register is updated in the ABILITY_DETECT state of the PCS auto-negotiation state machine so bit 14 will only be set if the link partner is sending acknowledge while the PCS in this state. The register is not updated in the ACK_DETECT state. For SGMII mode, the contents of this register change to the one defined in the SGMII standard. The value of this register contains the link partner's base page received information. In this case the link partner is the PHY connected by the SGMII.
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved. Set to zero. | RO | 0x0000
15 | link_partner_next_page_status | The contents of this register change depending on SGMII or non SGMII mode., :, :non SGMII Mode:, :Link partner next page - when set active high, this bit indicates the link partner's intention to exchange next pages., :, :SGMII Mode: , :Link Status., :0 : Link Down., :1 : Link Up. | RO | 0
14 | link_partner_acknowledge | Link partner acknowledge - indicates the link partner has successfully received the transmitted base page | RO | 0
13:12 | link_partner_remote_fault_duplex_mode | The contents of this register change depending on SGMII or non SGMII mode., :, :non SGMII Mode:, :Link partner remote fault [1:0] - indicates and classifies a remote fault condition has been detected by the link partner as follows:, :00: No error, Link OK, :01: Link Failure., :10: Off line. , :11: Auto-negotiation error., :, :SGMII Mode:, :Bit 13: Reserved. read as 0., :Bit 12 : 0 : half-duplex. 1: Full Duplex. | RO | 0x0
11:9 | speed_reserved | The contents of this register change depending on SGMII or non SGMII mode., :, :non SGMII Mode:, :Reserved. Set to zero., :, :SGMII Mode :, :Bits 11:10 : Speed : , :11 : Reserved, :10 : 1000 Mbps, :01 : 100Mbps, :00 : 10 Mbps, :Bit 9 : Reserved. read as 0. | RO | 0x0
8:7 | pause | The contents of this register change depending on SGMII or non SGMII mode., :, :non SGMII Mode:, :Pause[1:0] - provides the link partner's pause frame capability as follows:, :00: No pause. , :01: Symmetric pause. , :10: Asymmetric pause toward link partner. , :11: Both symmetric pause and asymmetric pause toward link device., :, :SGMII Mode:, :Reserved. read as 0. | RO | 0x0
6 | link_partner_half_duplex | The contents of this register change depending on SGMII or non SGMII mode., :, :non SGMII Mode:, :Link partner half-duplex - this bit indicates whether the link partner is capable of supporting half-duplex operation. , :0: The link partner cannot support half-duplex. , :1: The link partner can support half-duplex., :, :SGMII Mode: , :Reserved. read as 0. | RO | 0
5 | link_partner_full_duplex | The contents of this register change depending on SGMII or non SGMII mode., :, :non SGMII Mode:, :Link partner full duplex - this bit indicates whether the link partner is capable of supporting full duplex operation. , :0: The link partner cannot support full duplex. , :1: The link partner can support full duplex., :, :SGMII Mode: , :Reserved. read as 0. | RO | 0
4:0 | reserved_4_0 | Reserved. Set to zero. | RO | 0x00

### gem_gxlmicrosemi : pcs_an_exp

Address offset | 0x0218
Description | This register contains auto-negotiation next page ability and page received information.
Type | RO

Bits | Field Name | Description | Type | Reset
31:3 | reserved_31_3 | Reserved. Set to zero. | RO | 0x0000 0000
2 | next_page_capability | Next page capability - hard wired to logic 1 to indicate that the GEM PCS supports next page operation. | RO | 1
1 | page_received | Page received - this bit is set active high when a new page has been received from the link partner. It is cleared when the link partner next page register has been read. | RO | 0
0 | reserved_0 | Reserved. Set to zero. | RO | 0

### gem_gxlmicrosemi : pcs_an_np_tx

Address offset | 0x021C
Description | The value of this register is used to transmit the next page information for the GEM PCS. For next page exchange to work this register must be written within 10 ms of receiving a new page from the link partner. If the link partner is requesting next pages and the GEM has none or no more to send then this register should be written with the null message (0x2001). The value 0x0000 must not be written to this register.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved. Set to zero. | RO | 0x0000
15 | next_page_to_transmit | Next page to transmit - this bit indicates whether this is the last next page to be transmitted:0: Last page. 1: Additional page(s) to follow. | RW | 0
14 | reserved_14 | Reserved. Set to zero. | RO | 0
13 | message_page_indicator | Message page indicator - this bit identifies the message. 0: Unformatted page. 1: Message page. | RW | 0
12 | acknowledge_2 | Acknowledge 2 - when set active high, indicates that the GEM PCS has the ability to comply with the last received message. | RW | 0
11 | reserved_11 | Reserved. Set to zero. | RO | 0
10:0 | message | Message - contains data as defined by the message page indicator bit. | RW | 0x000

### gem_gxlmicrosemi : pcs_an_lp_np

Address offset | 0x0220
Description | This value of this register contains the next page received information from the link partner.
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved. Set to zero. | RO | 0x0000
15 | next_page_to_receive | Next page to receive - this bit indicates whether this is the last page to be received in the sequence by the GEM PCS:, :0: Last page. , :1: Additional page(s) to follow. | RO | 0
14 | acknowledge | Acknowledge - this bit indicates whether as part of the next page function, the link partner has successfully received the last message transmitted. | RO | 0
13 | message_page_indicator | Message page indicator - this bit identifies the message. , :0: Unformatted page. , :1: Message page. | RO | 0
12 | acknowledge_2 | Acknowledge 2 - set active high by the link partner to indicate when it has the ability to comply with the last message received. | RO | 0
11 | toggle | Toggle - this bit toggles with every received page. | RO | 0
10:0 | message | Message - contains data as defined by the message page indicator bit. | RO | 0x000

### gem_gxlmicrosemi : pcs_an_ext_status

Address offset | 0x023C
Description | This register contains PCS auto-negotiation extended status information.
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved. Set to zero. | RO | 0x0000
15 | full_duplex_1000base_x | Full duplex 1000BASE-X - hardwired to logic 1, indicates the GEM PCS can support full duplex operation of 1000BASE-X. | RO | 1
14 | half_duplex_1000base_x | half-duplex 1000BASE-X - hardwired to logic 0, indicates the GEM MAC cannot support half-duplex operation at gigabit speeds. | RO | 0
13 | full_duplex_1000base_t | Full duplex 1000BASE-T - hardwired to logic 0, indicates the GEM PCS cannot support 1000BASE-T full duplex operation. | RO | 0
12 | half_duplex_1000base_t | half-duplex 1000BASE-T - hardwired to logic 0, indicates the GEM PCS cannot support 1000BASE-T half-duplex operation. | RO | 0
11:0 | reserved_11_0 | Reserved. Set to zero. | RO | 0x000

### gem_gxlmicrosemi : tx_pause_quantum1

Address offset | 0x0260
Description | Transmit Pause Quantum Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | quantum_p3 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 3. | RW | 0xFFFF
15:0 | quantum_p2 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 2. | RW | 0xFFFF

### gem_gxlmicrosemi : tx_pause_quantum2

Address offset | 0x0264
Description | Transmit Pause Quantum Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | quantum_p5 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 5. | RW | 0xFFFF
15:0 | quantum_p4 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 4. | RW | 0xFFFF

### gem_gxlmicrosemi : tx_pause_quantum3

Address offset | 0x0268
Description | Transmit Pause Quantum Register 3
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | quantum_p7 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 7. | RW | 0xFFFF
15:0 | quantum_p6 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 6. | RW | 0xFFFF

### gem_gxlmicrosemi : pfc_status

Address offset | 0x026C
Description | Priority Flow Control status register - indicates whether PFC has been negotiated and the current state of the PFC counters for each priority.
Type | RO

Bits | Field Name | Description | Type | Reset
31:9 | reserved_31_9 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
8 | pfc_negotiate_pclk | Set when PFC Priority Based Pause has been negotiated. | RO | 0
7:0 | rx_pfc_paused | Reflects the state of the rx_pfc_paused signals. Each bit in the vector corresponds to a priority indicated within the received PFC priority based pause frame. A bit is set when a PFC priority based pause frame has been received, and the associated priority pause time quantum is non-zero. The bit is cleared when the associated pause time has elapsed. | RO | 0x00

### gem_gxlmicrosemi : rx_lpi

Address offset | 0x0270
Description | Received LPI transitions
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Unused, read zero | RO | 0x0000
15:0 | count | Count of RX LPI transitions. A count of the number of times there is a transition from receiving normal idle to receiving low power idle. Cleared on read. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : rx_lpi_time

Address offset | 0x0274
Description | Received LPI time
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Unused, read zero | RO | 0x00
23:0 | lpi_time | Time in LPI. This register increments once every 16 pclk cycles when the LPI indication bit 7 is set in the network status register. Cleared on read. | RO RtoClr | 0x00 0000

### gem_gxlmicrosemi : tx_lpi

Address offset | 0x0278
Description | Transmit LPI transitions
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Unused, read zero | RO | 0x0000
15:0 | count | Count of TX LPI transmissions. A count of the number of times the enable LPI transmission bit 19 goes from low to high in the network control register. Cleared on read. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : tx_lpi_time

Address offset | 0x027C
Description | Transmit LPI time
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Unused, read zero | RO | 0x00
23:0 | lpi_time | Time in LPI. This register increments once every 16 pclk cycles when the enable LPI transmission bit 19 is set in the network control register. Cleared on read. | RO RtoClr | 0x00 0000

### gem_gxlmicrosemi : designcfg_debug1

Address offset | 0x0280
Description | Design Configuration Register 1 - The GEM has many parameterisation options to configure the IP during compilation stage. This is achieved using Verilog define compiler directives in an include file called gem_defs.v. This configuration is readable through APB addressable designcfg_debug registers.
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | axi_cache_value | Takes the value of the edma_axi_awcache_value parameter which is set by the `gem_axi_awcache_value DEFINE or will be zero if no packet buffer DMA is present | RO | 0x0
27:25 | dma_bus_width | Takes the value of bits 7:5 of the `gem_dma_bus_width DEFINE. So if the define is set to decimal 64 this will return binary 010. | RO | 0x2
24 | exclude_cbs | Takes the value of the edma_exclude_cbs parameter which is set by the `gem_exclude_cbs DEFINE. | RO | 0
23 | irq_read_clear | Takes the value of the edma_irq_read_clear parameter which is set by the `gem_irq_read_clear DEFINE | RO | 0
22 | no_snapshot | Takes the value of the edma_no_snapshot parameter which is set by the `gem_no_snapshot DEFINE | RO | 1
21 | no_stats | Takes the value of the edma_no_stats parameter which is set by the `gem_no_stats DEFINE | RO | 0
20 | reserved_20 | Reserved, read as 1, ignored on write. | RO | 1
19:15 | user_in_width | Takes the value of the `gem_user_in_width DEFINE or 1 if user_io not defined | RO | 0x06
14:10 | user_out_width | Takes the value of the `gem_user_out_width DEFINE or 1 if user_io not defined | RO | 0x06
9 | user_io | Takes the value of the `gem_user_io DEFINE | RO | 1
8 | reserved_8 | Reserved, read as 1, ignored on write. | RO | 1
7 | reserved_7 | Reserved, read as 0, ignored on write. | RO | 0
6 | ext_fifo_interface | Takes the value of the edma_ext_fifo_interface parameter which is set by the `gem_ext_fifo_interface DEFINE | RO | 0
5 | reserved_5 | Reserved, read as 0, ignored on write. | RO | 0
4 | int_loopback | Takes the value of the edma_int_loopback parameter which is set by the `gem_int_loopback DEFINE | RO | 1
3:2 | reserved_3_2 | Reserved, read as 0, ignored on write. | RO | 0x0
1 | exclude_qbv | Takes the value of the edma_exclude_qbv parameter which is set by the `gem_exclude_qbv DEFINE | RO | 0
0 | no_pcs | Takes the value of the edma_no_pcs parameter which is set by the `gem_no_pcs DEFINE | RO | 0

### gem_gxlmicrosemi : designcfg_debug2

Address offset | 0x0284
Description | Design Configuration Register 2
Type | RO

Bits | Field Name | Description | Type | Reset
31 | spram | Takes the value of the edma_spram parameter which is set by the `gem_spram DEFINE | RO | 0
30 | axi | Takes the value of the edma_axi parameter which is set by the `gem_axi DEFINE but will be zero if the FIFO interface has been configured | RO | 1
29:26 | tx_pbuf_addr | Takes the value of the `gem_tx_pbuf_addr DEFINE or zero if pbuf_address is decimal 16 | RO | 0xB
25:22 | rx_pbuf_addr | Takes the value of the `gem_rx_pbuf_addr DEFINE or zero if pbuf_address is decimal 16 | RO | 0xB
21 | tx_pkt_buffer | Takes the value of the edma_tx_pkt_buffer parameter which is set by the `gem_tx_pkt_buffer DEFINE but will be zero if the FIFO interface has been configured | RO | 1
20 | rx_pkt_buffer | Takes the value of the edma_rx_pkt_buffer parameter which is set by the `gem_rx_pkt_buffer DEFINE but will be zero if the FIFO interface has been configured | RO | 1
19:16 | hprot_value | Takes the value of the edma_hprot parameter which is set by the `gem_hprot_value DEFINE | RO | 0x1
15:14 | reserved_15_14 | Unused, read zero | RO | 0x0
13:0 | jumbo_max_length | Takes the value of the edma_jumbo_max_length parameter which is set by the `gem_jumbo_max_length DEFINE | RO | 0x2800

### gem_gxlmicrosemi : designcfg_debug3

Address offset | 0x0288
Description | Design Configuration Register 3
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Unused, read zero | RO | 0x0
29:24 | num_spec_add_filters | Takes the value of the `num_spec_add_filters DEFINE | RO | 0x04
23:21 | reserved_23_21 | Unused, read zero | RO | 0x0
20:0 | reserved_20_0 | Unused, read zero - reserved for rx_base2_fifo_size and rx_fifo_size defines in internal FIFO mode | RO | 0x00 0000

### gem_gxlmicrosemi : designcfg_debug4

Address offset | 0x028C
Description | Design Configuration Register 4
Type | RO

Bits | Field Name | Description | Type | Reset
31:20 | reserved_31_20 | Unused, read zero | RO | 0x000
19:0 | reserved_19_0 | Unused, read zero - reserved for tx_base2_fifo_size and tx_fifo_size defines in internal FIFO mode | RO | 0x0 0000

### gem_gxlmicrosemi : designcfg_debug5

Address offset | 0x0290
Description | Design Configuration Register 5
Type | RO

Bits | Field Name | Description | Type | Reset
31:29 | axi_prot_value | Takes the value of the edma_axi_prot_value parameter which is set by the `gem_axi_prot_value DEFINE but will be zero if the FIFO interface has been configured | RO | 0x2
28 | tsu_clk | Takes the value of the `gem_tsu_clk DEFINE | RO | 1
27:20 | rx_buffer_length_def | Takes the value of the `gem_rx_buffer_length_def DEFINE | RO | 0x02
19 | tx_pbuf_size_def | Takes the value of the edma_tx_pbuf_size_def parameter which is set by the `gem_tx_pbuf_size_def DEFINE but will be zero if the FIFO inteface has been configured | RO | 1
18:17 | rx_pbuf_size_def | Takes the value of the `gem_rx_pbuf_size_def DEFINE | RO | 0x3
16:15 | endian_swap_def | Takes the value of the `gem_endian_swap_def DEFINE | RO | 0x0
14:12 | mdc_clock_div | Takes the value of the `gem_mdc_clock_div DEFINE | RO | 0x2
11:10 | dma_bus_width_def | Takes the value of the `gem_dma_bus_width_def DEFINE | RO | 0x1
9 | phy_ident | Indicates whether the top and bottom PHY_ID registers are present in the address map | RO | 1
8 | tsu | Takes the value of the `gem_tsu DEFINE | RO | 1
7:4 | tx_fifo_cnt_width | Takes the value of the `gem_tx_fifo_cnt_width DEFINE | RO | 0x4
3:0 | rx_fifo_cnt_width | Takes the value of the `gem_rx_fifo_cnt_width DEFINE | RO | 0x5

### gem_gxlmicrosemi : designcfg_debug6

Address offset | 0x0294
Description | Design Configuration Register 6
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | reserved_31_28 | Reserved. Set to zero. | RO | 0x0
27 | pbuf_lso | Takes the value of the edma_lso parameter which is set by the `gem_pbuf_lso DEFINE this is zero if the FIFO interface or AHB is configured. | RO | 1
26 | pbuf_rsc | Takes the value of the edma_rsc parameter which is set by the `gem_pbuf_rsc DEFINE or is zero if the FIFO interface or AHB is configured. | RO | 0
25 | pbuf_cutthru | Takes the value of the `gem_pbuf_cutthru DEFINE | RO | 1
24 | pfc_multi_quantum | Takes the value of the `gem_pfc_multi_quantum DEFINE | RO | 1
23 | dma_addr_width_is_64b | This is one if the `gem_dma_addr_width DEFINE is set to 64. | RO | 1
22 | host_if_soft_select | Takes the value of the `gem_host_if_soft_select DEFINE | RO | 0
21 | tx_add_fifo_if | Takes the value of the `gem_tx_add_fifo_if DEFINE | RO | 0
20 | ext_tsu_timer | Takes the value of the `gem_ext_tsu_timer DEFINE | RO | 0
19:16 | tx_pbuf_queue_segment_size | Takes the value of the `gem_tx_pbuf_queue_segment_size DEFINE | RO | 0x2
15 | dma_priority_queue15 | Takes the value of the `dma_priority_queue15 DEFINE | RO | 0
14 | dma_priority_queue14 | Takes the value of the `dma_priority_queue14 DEFINE | RO | 0
13 | dma_priority_queue13 | Takes the value of the `dma_priority_queue13 DEFINE | RO | 0
12 | dma_priority_queue12 | Takes the value of the `dma_priority_queue12 DEFINE | RO | 0
11 | dma_priority_queue11 | Takes the value of the `dma_priority_queue11 DEFINE | RO | 0
10 | dma_priority_queue10 | Takes the value of the `dma_priority_queue10 DEFINE | RO | 0
9 | dma_priority_queue9 | Takes the value of the `dma_priority_queue9 DEFINE | RO | 0
8 | dma_priority_queue8 | Takes the value of the `dma_priority_queue8 DEFINE | RO | 0
7 | dma_priority_queue7 | Takes the value of the `dma_priority_queue7 DEFINE | RO | 0
6 | dma_priority_queue6 | Takes the value of the `dma_priority_queue6 DEFINE | RO | 0
5 | dma_priority_queue5 | Takes the value of the `dma_priority_queue5 DEFINE | RO | 0
4 | dma_priority_queue4 | Takes the value of the `dma_priority_queue4 DEFINE | RO | 0
3 | dma_priority_queue3 | Takes the value of the `dma_priority_queue3 DEFINE | RO | 1
2 | dma_priority_queue2 | Takes the value of the `dma_priority_queue2 DEFINE | RO | 1
1 | dma_priority_queue1 | Takes the value of the `dma_priority_queue1 DEFINE | RO | 1
0 | reserved_0 | Reserved. Set to zero. | RO | 0

### gem_gxlmicrosemi : designcfg_debug7

Address offset | 0x0298
Description | Design Configuration Register 7
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | tx_pbuf_num_segments_q7 | Takes the value of the `gem_tx_pbuf_num_segments_q7 DEFINE | RO | 0x0
27:24 | tx_pbuf_num_segments_q6 | Takes the value of the `gem_tx_pbuf_num_segments_q6 DEFINE | RO | 0x0
23:20 | tx_pbuf_num_segments_q5 | Takes the value of the `gem_tx_pbuf_num_segments_q5 DEFINE | RO | 0x0
19:16 | tx_pbuf_num_segments_q4 | Takes the value of the `gem_tx_pbuf_num_segments_q4 DEFINE | RO | 0x0
15:12 | tx_pbuf_num_segments_q3 | Takes the value of the `gem_tx_pbuf_num_segments_q3 DEFINE | RO | 0x0
11:8 | tx_pbuf_num_segments_q2 | Takes the value of the `gem_tx_pbuf_num_segments_q2 DEFINE | RO | 0x0
7:4 | tx_pbuf_num_segments_q1 | Takes the value of the `gem_tx_pbuf_num_segments_q1 DEFINE | RO | 0x0
3:0 | tx_pbuf_num_segments_q0 | Takes the value of the edma_tx_pbuf_num_segments_q0 parameter which is set by the `gem_tx_pbuf_num_segments_q0 DEFINE or is zero if priority queuing is not configured. | RO | 0x0

### gem_gxlmicrosemi : designcfg_debug8

Address offset | 0x029C
Description | Design Configuration Register 8
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | num_type1_screeners | Takes the value of the `num_type1_screeners DEFINE | RO | 0x04
23:16 | num_type2_screeners | Takes the value of the `num_type2_screeners DEFINE | RO | 0x04
15:8 | num_scr2_ethtype_regs | Takes the value of the `num_scr2_ethtype_regs DEFINE | RO | 0x04
7:0 | num_scr2_compare_regs | Takes the value of the `num_scr2_compare_regs DEFINE | RO | 0x0C

### gem_gxlmicrosemi : designcfg_debug9

Address offset | 0x02A0
Description | Design Configuration Register 9
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | tx_pbuf_num_segments_q15 | Takes the value of the `gem_tx_pbuf_num_segments_q15 DEFINE | RO | 0x0
27:24 | tx_pbuf_num_segments_q14 | Takes the value of the `gem_tx_pbuf_num_segments_q14 DEFINE | RO | 0x0
23:20 | tx_pbuf_num_segments_q13 | Takes the value of the `gem_tx_pbuf_num_segments_q13 DEFINE | RO | 0x0
19:16 | tx_pbuf_num_segments_q12 | Takes the value of the `gem_tx_pbuf_num_segments_q12 DEFINE | RO | 0x0
15:12 | tx_pbuf_num_segments_q11 | Takes the value of the `gem_tx_pbuf_num_segments_q11 DEFINE | RO | 0x0
11:8 | tx_pbuf_num_segments_q10 | Takes the value of the `gem_tx_pbuf_num_segments_q10 DEFINE | RO | 0x0
7:4 | tx_pbuf_num_segments_q9 | Takes the value of the `gem_tx_pbuf_num_segments_q9 DEFINE | RO | 0x0
3:0 | tx_pbuf_num_segments_q8 | Takes the value of the `gem_tx_pbuf_num_segments_q8 DEFINE | RO | 0x0

### gem_gxlmicrosemi : designcfg_debug10

Address offset | 0x02A4
Description | Design Configuration Register 10
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | emac_bus_width | Takes the value of the `gem_emac_bus_width DEFINE. 1 - The MAC has a datawidth of 32bits. 2 - The MAC has a datawidth of 64bits. 4 - The MAC has a datawidth of 128bits | RO | 0x2
27:24 | tx_pbuf_data | Takes the value of the `gem_tx_pbuf_data DEFINE. 1 - The TX DPRAM has a datawidth of 32bits. 2 - The TX DPRAM has a datawidth of 64bits. 4 - The TX DPRAM has a datawidth of 128bits | RO | 0x2
23:20 | rx_pbuf_data | Takes the value of the `gem_rx_pbuf_data DEFINE. 1 - The RX DPRAM has a datawidth of 32bits. 2 - The RX DPRAM has a datawidth of 64bits. 4 - RX The DPRAM has a datawidth of 128bits | RO | 0x2
19:16 | axi_access_pipeline_bits | Takes the value of the edma_axi_access_pipeline_bits parameter which is set by the `gem_axi_access_pipeline_bits DEFINE or is zero if the FIFO interface is configured. | RO | 0x4
15:12 | axi_tx_descr_rd_buff_bits | Takes the value of the edma_axi_tx_descr_rd_buff_bits parameter which is set by the `gem_axi_tx_descr_rd_buff_bits DEFINE or is zero if the FIFO interface is configured. | RO | 0x1
11:8 | axi_rx_descr_rd_buff_bits | Takes the value of the edma_axi_rx_descr_rd_buff_bits parameter which is set by the `gem_axi_rx_descr_rd_buff_bits DEFINE or is zero if the FIFO interface is configured. | RO | 0x1
7:4 | axi_tx_descr_wr_buff_bits | Takes the value of the edma_axi_tx_descr_wr_buff_bits parameter which is set by the `gem_axi_tx_descr_wr_buff_bits DEFINE or is zero if the FIFO interface is configured. | RO | 0x1
3:0 | axi_rx_descr_wr_buff_bits | Takes the value of the edma_axi_rx_descr_wr_buff_bits parameter which is set by the `gem_axi_rx_descr_wr_buff_bits DEFINE or is zero if the FIFO interface is configured. | RO | 0x1

### gem_gxlmicrosemi : designcfg_debug11

Address offset | 0x02A8
Description | Design Configuration Register 11
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7 | asf_prot_tx_sched | Takes the value of the edma_asf_asf_prot_tx_sched parameter which is set by the `gem_asf_prot_tx_sched DEFINE. | RO | 0
6 | asf_host_par | Takes the value of the edma_asf_host_par parameter which is set by the `gem_asf_host_par DEFINE. | RO | 0
5 | asf_trans_to_prot | Takes the value of the edma_asf_trans_to_prot parameter which is set by the `gem_asf_enable DEFINE. | RO | 0
4 | asf_integrity_prot | Takes the value of the edma_asf_integrity_prot parameter which is set by the `gem_asf_enable DEFINE. | RO | 0
3 | protect_tsu | akes the value of the edma_asf_prot_tsu parameter which is set by the `gem_asf_prot_tsu DEFINE or is zero if no TSU is present. | RO | 0
2 | csr_protection | Takes the value of the edma_asf_csr_prot parameter which is set by the `gem_asf_enable DEFINE. | RO | 0
1 | dap_protection | Takes the value of the edma_asf_dap_prot parameter which is set by the `gem_asf_enable DEFINE. | RO | 0
0 | ecc_sram | Takes the value of the edma_asf_ecc_sram parameter which is set by the `gem_asf_ecc_sram DEFINE. | RO | 0

### gem_gxlmicrosemi : designcfg_debug12

Address offset | 0x02AC
Description | Design Configuration Register 12
Type | RO

Bits | Field Name | Description | Type | Reset
31:26 | reserved_31_26 | Reserved, read as 0, ignored on write. | RO | 0x00
25 | gem_has_802p3_br | Takes the value of the edma_has_br parameter which is set by the gem_has_802p3_br tick define. If defined the configuration contains both an express MAC (eMAC) and a pre-emptable MAC (pMAC) to allow 802.3br frame pre-emption. | RO | 1
24:21 | emac_tx_pbuf_addr | Takes the value of the `gem_emac_tx_pbuf_addr DEFINE - this defines the size of the transmit SRAM for express MAC (eMAC) when 802.3br is configured - will be zero if emac_tx_pbuf_address is decimal 16 | RO | 0x9
20:17 | emac_rx_pbuf_addr | Takes the value of the `gem_emac_rx_pbuf_addr DEFINE - this defines the size of the receive SRAM for express MAC (eMAC) when 802.3br is configured - will be zero if emac_rx_pbuf_address is decimal 16 | RO | 0x9
16 | gem_has_cb | Indicates whether gem has 802.1CB/FRER configured. This is zero if `gem_no_of_cb_streams is undefined or zero. | RO | 1
15:8 | gem_cb_history_len | Takes the value of the `gem_seq_history_len DEFINE or 0x01 if undefined. | RO | 0x08
7:0 | gem_num_cb_streams | Takes the value of the `gem_no_of_cb_streams DEFINE or 0x01 if undefined or the defined value is zero. | RO | 0x04

### gem_gxlmicrosemi : axi_qos_cfg_0

Address offset | 0x02E0
Description | AXI Quality of Service register 0. This register is only present if AXI is configured. This register contains 8-bits per queue to control driving of the ARQOS and AWQOS outputs (4-bits each). For each queue the lower four bits are for data accesses and the upper four bits are for descriptor accesses.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | q_3_descr_qos | Determines what value to drive to the ARQOS and AWQOS outputs (4-bits each) for queue 3 descriptor accesses. | RW | 0x0
27:24 | q_3_data_qos | Determines what value to drive to the ARQOS and AWQOS outputs (4-bits each) for queue 3 data accesses. | RW | 0x0
23:20 | q_2_descr_qos | Determines what value to drive to the ARQOS and AWQOS outputs (4-bits each) for queue 2 descriptor accesses. | RW | 0x0
19:16 | q_2_data_qos | Determines what value to drive to the ARQOS and AWQOS outputs (4-bits each) for queue 2 data accesses. | RW | 0x0
15:12 | q_1_descr_qos | Determines what value to drive to the ARQOS and AWQOS outputs (4-bits each) for queue 1 descriptor accesses. | RW | 0x0
11:8 | q_1_data_qos | Determines what value to drive to the ARQOS and AWQOS outputs (4-bits each) for queue 1 data accesses. | RW | 0x0
7:4 | q_0_descr_qos | Determines what value to drive to the ARQOS and AWQOS outputs (4-bits each) for queue 0 descriptor accesses. | RW | 0x0
3:0 | q_0_data_qos | Determines what value to drive to the ARQOS and AWQOS outputs (4-bits each) for queue 0 data accesses. | RW | 0x0

### gem_gxlmicrosemi : int_q1_status

Address offset | 0x0400
Description | Priority Queue Interrupt Status Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved_31_12 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
11 | resp_not_ok | bresp/hresp not OK | RW W1toClr | 0
10:8 | reserved_10_8 | Reserved, read as 0, ignored on write. | RO | 0x0
7 | transmit_complete | Transmit complete | RW W1toClr | 0
6 | amba_error | Transmit frame corruption due to AMBA (AHB/AXI) error set if an error occurs whilst midway through reading transmit frame from the external memory, including HRESP errors(AHB), RRESP and BRESP errors (AXI) and buffers exhausted mid frame | RW W1toClr | 0
5 | retry_limit_exceeded_or_late_collision | Retry limit exceeded or late collision | RW W1toClr | 0
4:3 | reserved_4_3 | Reserved, read as 0, ignored on write. | RO | 0x0
2 | rx_used_bit_read | RX used bit read | RW W1toClr | 0
1 | receive_complete | Receive complete | RW W1toClr | 0
0 | reserved_0 | Reserved, read as 0, ignored on write. | RO | 0

### gem_gxlmicrosemi : int_q2_status

Address offset | 0x0404
Description | Priority Queue Interrupt Status Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved_31_12 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
11 | resp_not_ok | bresp/hresp not OK | RW W1toClr | 0
10:8 | reserved_10_8 | Reserved, read as 0, ignored on write. | RO | 0x0
7 | transmit_complete | Transmit complete | RW W1toClr | 0
6 | amba_error | Transmit frame corruption due to AMBA (AHB/AXI) error set if an error occurs whilst midway through reading transmit frame from the external memory, including HRESP errors(AHB), RRESP and BRESP errors (AXI) and buffers exhausted mid frame | RW W1toClr | 0
5 | retry_limit_exceeded_or_late_collision | Retry limit exceeded or late collision | RW W1toClr | 0
4:3 | reserved_4_3 | Reserved, read as 0, ignored on write. | RO | 0x0
2 | rx_used_bit_read | RX used bit read | RW W1toClr | 0
1 | receive_complete | Receive complete | RW W1toClr | 0
0 | reserved_0 | Reserved, read as 0, ignored on write. | RO | 0

### gem_gxlmicrosemi : int_q3_status

Address offset | 0x0408
Description | Priority Queue Interrupt Status Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved_31_12 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
11 | resp_not_ok | bresp/hresp not OK | RW W1toClr | 0
10:8 | reserved_10_8 | Reserved, read as 0, ignored on write. | RO | 0x0
7 | transmit_complete | Transmit complete | RW W1toClr | 0
6 | amba_error | Transmit frame corruption due to AMBA (AHB/AXI) error set if an error occurs whilst midway through reading transmit frame from the external memory, including HRESP errors(AHB), RRESP and BRESP errors (AXI) and buffers exhausted mid frame | RW W1toClr | 0
5 | retry_limit_exceeded_or_late_collision | Retry limit exceeded or late collision | RW W1toClr | 0
4:3 | reserved_4_3 | Reserved, read as 0, ignored on write. | RO | 0x0
2 | rx_used_bit_read | RX used bit read | RW W1toClr | 0
1 | receive_complete | Receive complete | RW W1toClr | 0
0 | reserved_0 | Reserved, read as 0, ignored on write. | RO | 0

### gem_gxlmicrosemi : transmit_q1_ptr

Address offset | 0x0440
Description | This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | dma_tx_q_ptr | Transmit buffer queue base address - written with the address of the start of the transmit queue. | RW | 0x0000 0000
1 | reserved_1 | Reserved, read as 0, ignored on write. | RO | 0
0 | dma_tx_dis_q | Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. | RW | 0

### gem_gxlmicrosemi : transmit_q2_ptr

Address offset | 0x0444
Description | This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | dma_tx_q_ptr | Transmit buffer queue base address - written with the address of the start of the transmit queue. | RW | 0x0000 0000
1 | reserved_1 | Reserved, read as 0, ignored on write. | RO | 0
0 | dma_tx_dis_q | Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. | RW | 0

### gem_gxlmicrosemi : transmit_q3_ptr

Address offset | 0x0448
Description | This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | dma_tx_q_ptr | Transmit buffer queue base address - written with the address of the start of the transmit queue. | RW | 0x0000 0000
1 | reserved_1 | Reserved, read as 0, ignored on write. | RO | 0
0 | dma_tx_dis_q | Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. | RW | 0

### gem_gxlmicrosemi : receive_q1_ptr

Address offset | 0x0480
Description | This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | dma_rx_q_ptr | Receive buffer queue base address - written with the address of the start of the receive queue. | RW | 0x0000 0000
1 | reserved_1 | Reserved, read as 0, ignored on write. | RO | 0
0 | dma_rx_dis_q | Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled. | RW | 0

### gem_gxlmicrosemi : receive_q2_ptr

Address offset | 0x0484
Description | This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | dma_rx_q_ptr | Receive buffer queue base address - written with the address of the start of the receive queue. | RW | 0x0000 0000
1 | reserved_1 | Reserved, read as 0, ignored on write. | RO | 0
0 | dma_rx_dis_q | Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled. | RW | 0

### gem_gxlmicrosemi : receive_q3_ptr

Address offset | 0x0488
Description | This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | dma_rx_q_ptr | Receive buffer queue base address - written with the address of the start of the receive queue. | RW | 0x0000 0000
1 | reserved_1 | Reserved, read as 0, ignored on write. | RO | 0
0 | dma_rx_dis_q | Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled. | RW | 0

### gem_gxlmicrosemi : dma_rxbuf_size_q1

Address offset | 0x04A0
Description | Receive Buffer Size
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:0 | dma_rx_q_buf_size | DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes., :0x01 corresponds to buffers of 64 bytes., :0x02 corresponds to 128 bytes etc., :For example:, :0x02: 128 byte, :0x18: 1536 byte (1*max length frame/buffer), :0xA0: 10240 byte (1*10K jumbo frame/buffer), :0xFF: 16320 byte, :Note that this value should never be written as zero., :Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. | RW | 0x02

### gem_gxlmicrosemi : dma_rxbuf_size_q2

Address offset | 0x04A4
Description | Receive Buffer Size
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:0 | dma_rx_q_buf_size | DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes., :0x01 corresponds to buffers of 64 bytes., :0x02 corresponds to 128 bytes etc., :For example:, :0x02: 128 byte, :0x18: 1536 byte (1*max length frame/buffer), :0xA0: 10240 byte (1*10K jumbo frame/buffer), :0xFF: 16320 byte, :Note that this value should never be written as zero., :Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. | RW | 0x02

### gem_gxlmicrosemi : dma_rxbuf_size_q3

Address offset | 0x04A8
Description | Receive Buffer Size
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:0 | dma_rx_q_buf_size | DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes., :0x01 corresponds to buffers of 64 bytes., :0x02 corresponds to 128 bytes etc., :For example:, :0x02: 128 byte, :0x18: 1536 byte (1*max length frame/buffer), :0xA0: 10240 byte (1*10K jumbo frame/buffer), :0xFF: 16320 byte, :Note that this value should never be written as zero., :Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. | RW | 0x02

### gem_gxlmicrosemi : cbs_control

Address offset | 0x04BC
Description | The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not exceed the portTransmitRate which is dependent on the speed of operation, eg, portTransmitRate: 1Gb/s = 32'h07735940 (125 Mbytes/s), 100Mb/sec = 32'h017D7840 (25 Mnibbles/s), 10Mb/sec = 32'h002625A0 (2.5 Mnibbles/s). If 50% of bandwidth was to be allocated to a particular queue in 1Gb/sec mode then the IdleSlope value for that queue would be calculated as 32'h07735940/2. Note: Credit-Based Shaping should be disabled prior to updating the IdleSlope values. As another example, for a 1722 audio packet with a payload of 6 samples per channel, the packet size would be: 7 (preamble) + 1 (SFD) + 50 (packet header) + 6x4x2(payload) + 4 (CRC) = 110 bytes. For a rate of 8000 packets per second, the desired rate would 110 x 8000 bytes per second, so the programmed idleSlope value would be 880000 for a 1Gb/s connection, or 1760000 for a 100Mb/s or 10Mbs connection. See Figure 6.3 in the IEEE 1722 standard. In practice, the actual transmission rate will be vary slightly from that calculated. In this case, the idleSlope value should be recalibrated based on the variance between the measured and expected rate, and in this case very accurate transmission rates can be achieved. (The idleslope value is scaled by 2.5 in 2.5G operation and so the port transmit rate is the same for 1G and 2.5G.)
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved_31_2 | Reserved, read as 0, ignored on write. | RO | 0x0000 0000
1 | cbs_enable_queue_b | Enable Credit-Based shaping on the 2nd highest priority queue (queue B). Write 1 to enable | RW | 0
0 | cbs_enable_queue_a | Enable Credit-Based Shaping on the highest priority queue (queue A). Write 1 to enable | RW | 0

### gem_gxlmicrosemi : cbs_idleslope_q_a

Address offset | 0x04C0
Description | Queue A is the highest priority queue. This is the highest indexed active queue, e.g. For a system with Q0 to Q7, this would be Q7 if all queues were active.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | idleslope_a | IdleSlope value for queue A in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation | RW | 0x0000 0000

### gem_gxlmicrosemi : cbs_idleslope_q_b

Address offset | 0x04C4
Description | Queue B is the 2nd highest priority queue. This is the second highest indexed active queue, e.g. For a system with Q0 to Q7, this would be Q6 if all queues were active.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | idleslope_b | IdleSlope value for queue B in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation | RW | 0x0000 0000

### gem_gxlmicrosemi : upper_tx_q_base_addr

Address offset | 0x04C8
Description | Upper 32 bits of transmit buffer descriptor queue base address.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | upper_tx_q_base_addr | Upper 32 bits of transmit buffer descriptor queue base address. Used when 64 bit addressing is enabled. (In releases earlier to 1p06f2 this register also affected the receive descriptor queue.) | RW | 0x0000 0000

### gem_gxlmicrosemi : tx_bd_control

Address offset | 0x04CC
Description | Transmit buffer descriptor control register - this register determines which transmit frames, with time stamps reported in the buffer descriptor status field in extended buffer descriptor mode, set bit 23 in transmit buffer descriptor word 1.
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved_31_6 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
5:4 | tx_bd_ts_mode | Transmit Descriptor Timestamp Insertion mode - bit 23 in transmit buffer descriptor word 1 when extended buffer descriptor mode is enabled,, : 00: Bit 23 always zero,, : 01: Bit 23 high for PTP Event Frames only,, : 10: Bit 23 high for all PTP Frames only,, : 11: Bit 23 always high | RW | 0x0
3:0 | reserved_3_0 | Reserved, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : rx_bd_control

Address offset | 0x04D0
Description | Receive buffer descriptor control register - this register determines which receive frames have time stamps reported in the buffer descriptor status field
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved_31_6 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
5:4 | rx_bd_ts_mode | Receive Descriptor Timestamp Insertion mode,, : 00: TS insertion disable,, : 01: TS inserted for PTP Event Frames only,, : 10: TS inserted for All PTP Frames only,, : 11: TS insertion for All Frames | RW | 0x0
3:0 | reserved_3_0 | Reserved, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : upper_rx_q_base_addr

Address offset | 0x04D4
Description | Upper 32 bits of receive buffer descriptor queue base address.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | upper_rx_q_base_addr | Upper 32 bits of receive buffer descriptor queue base address. Used when 64 bit addressing is enabled. | RW | 0x0000 0000

### gem_gxlmicrosemi : wd_counter

Address offset | 0x04EC
Description | Hidden control register - do not alter
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved_31_4 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
3:0 | rx_bd_reread_timer | Controls counter used to retry receive descriptor reads (retries may occur if there was a resource error and there are frames waiting in the internal SRAM buffer to be off-loaded to host memory) | RW | 0x7

### gem_gxlmicrosemi : axi_tx_full_thresh0

Address offset | 0x04F8
Description | Hidden control register - do not alter
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | axi_tx_full_adj_0 | AXI single port SRAM fine tuning | RW | 0x06
15:8 | reserved_15_8 | Reserved, read as 0, ignored on write. | RO | 0x00
7:0 | axi_tx_full_adj_1 | AXI single port SRAM fine tuning | RW | 0x08

### gem_gxlmicrosemi : axi_tx_full_thresh1

Address offset | 0x04FC
Description | Hidden control register - do not alter
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | axi_tx_full_adj_2 | AXI single port SRAM fine tuning | RW | 0x00
15:8 | reserved_15_8 | Reserved, read as 0, ignored on write. | RO | 0x00
7:0 | axi_tx_full_adj_3 | AXI single port SRAM fine tuning | RW | 0x00

### gem_gxlmicrosemi : screening_type_1_register_0

Address offset | 0x0500
Description | Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved_31 | Reserved, read as 0, ignored on write. | RO | 0
30 | drop_on_match | When set, if the frame matches it will be completely dropped. In this case the queue number is don't care. | RW | 0
29 | udp_port_match_enable | UDP port match enable | RW | 0
28 | dstc_enable | DS/TC Enable | RW | 0
27:12 | udp_port_match | UDP Port Match | RW | 0x0000
11:4 | dstc_match | DS/TC Match | RW | 0x00
3:0 | queue_number | Queue Number (0 to 15) | RW | 0x0

### gem_gxlmicrosemi : screening_type_1_register_1

Address offset | 0x0504
Description | Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved_31 | Reserved, read as 0, ignored on write. | RO | 0
30 | drop_on_match | When set, if the frame matches it will be completely dropped. In this case the queue number is don't care. | RW | 0
29 | udp_port_match_enable | UDP port match enable | RW | 0
28 | dstc_enable | DS/TC Enable | RW | 0
27:12 | udp_port_match | UDP Port Match | RW | 0x0000
11:4 | dstc_match | DS/TC Match | RW | 0x00
3:0 | queue_number | Queue Number (0 to 15) | RW | 0x0

### gem_gxlmicrosemi : screening_type_1_register_2

Address offset | 0x0508
Description | Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved_31 | Reserved, read as 0, ignored on write. | RO | 0
30 | drop_on_match | When set, if the frame matches it will be completely dropped. In this case the queue number is don't care. | RW | 0
29 | udp_port_match_enable | UDP port match enable | RW | 0
28 | dstc_enable | DS/TC Enable | RW | 0
27:12 | udp_port_match | UDP Port Match | RW | 0x0000
11:4 | dstc_match | DS/TC Match | RW | 0x00
3:0 | queue_number | Queue Number (0 to 15) | RW | 0x0

### gem_gxlmicrosemi : screening_type_1_register_3

Address offset | 0x050C
Description | Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved_31 | Reserved, read as 0, ignored on write. | RO | 0
30 | drop_on_match | When set, if the frame matches it will be completely dropped. In this case the queue number is don't care. | RW | 0
29 | udp_port_match_enable | UDP port match enable | RW | 0
28 | dstc_enable | DS/TC Enable | RW | 0
27:12 | udp_port_match | UDP Port Match | RW | 0x0000
11:4 | dstc_match | DS/TC Match | RW | 0x00
3:0 | queue_number | Queue Number (0 to 15) | RW | 0x0

### gem_gxlmicrosemi : screening_type_2_register_0

Address offset | 0x0540
Description | Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:
Type | RW

Bits | Field Name | Description | Type | Reset
31 | drop_on_match | When set, if the frame matches it will be completely dropped. In this case the queue number is don't care. | RW | 0
30 | compare_c_enable | Compare C Enable | RW | 0
29:25 | compare_c | Compare C - Index to screener type 2 Compare register | RW | 0x00
24 | compare_b_enable | Compare B Enable | RW | 0
23:19 | compare_b | Compare B - Index to screener type 2 Compare register | RW | 0x00
18 | compare_a_enable | Compare A Enable | RW | 0
17:13 | compare_a | Compare A - Index to screener type 2 Compare register | RW | 0x00
12 | ethertype_enable | EtherType Enable | RW | 0
11:9 | ethertype_reg_index | Index to screener type 2 EtherType register | RW | 0x0
8 | vlan_enable | VLAN Enable | RW | 0
7 | reserved_7 | Reserved and implemented as RW | RW | 0
6:4 | vlan_priority | VLAN Priority | RW | 0x0
3:0 | queue_number | Queue Number (0 to 15) | RW | 0x0

### gem_gxlmicrosemi : screening_type_2_register_1

Address offset | 0x0544
Description | Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:
Type | RW

Bits | Field Name | Description | Type | Reset
31 | drop_on_match | When set, if the frame matches it will be completely dropped. In this case the queue number is don't care. | RW | 0
30 | compare_c_enable | Compare C Enable | RW | 0
29:25 | compare_c | Compare C - Index to screener type 2 Compare register | RW | 0x00
24 | compare_b_enable | Compare B Enable | RW | 0
23:19 | compare_b | Compare B - Index to screener type 2 Compare register | RW | 0x00
18 | compare_a_enable | Compare A Enable | RW | 0
17:13 | compare_a | Compare A - Index to screener type 2 Compare register | RW | 0x00
12 | ethertype_enable | EtherType Enable | RW | 0
11:9 | ethertype_reg_index | Index to screener type 2 EtherType register | RW | 0x0
8 | vlan_enable | VLAN Enable | RW | 0
7 | reserved_7 | Reserved and implemented as RW | RW | 0
6:4 | vlan_priority | VLAN Priority | RW | 0x0
3:0 | queue_number | Queue Number (0 to 15) | RW | 0x0

### gem_gxlmicrosemi : screening_type_2_register_2

Address offset | 0x0548
Description | Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:
Type | RW

Bits | Field Name | Description | Type | Reset
31 | drop_on_match | When set, if the frame matches it will be completely dropped. In this case the queue number is don't care. | RW | 0
30 | compare_c_enable | Compare C Enable | RW | 0
29:25 | compare_c | Compare C - Index to screener type 2 Compare register | RW | 0x00
24 | compare_b_enable | Compare B Enable | RW | 0
23:19 | compare_b | Compare B - Index to screener type 2 Compare register | RW | 0x00
18 | compare_a_enable | Compare A Enable | RW | 0
17:13 | compare_a | Compare A - Index to screener type 2 Compare register | RW | 0x00
12 | ethertype_enable | EtherType Enable | RW | 0
11:9 | ethertype_reg_index | Index to screener type 2 EtherType register | RW | 0x0
8 | vlan_enable | VLAN Enable | RW | 0
7 | reserved_7 | Reserved and implemented as RW | RW | 0
6:4 | vlan_priority | VLAN Priority | RW | 0x0
3:0 | queue_number | Queue Number (0 to 15) | RW | 0x0

### gem_gxlmicrosemi : screening_type_2_register_3

Address offset | 0x054C
Description | Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:
Type | RW

Bits | Field Name | Description | Type | Reset
31 | drop_on_match | When set, if the frame matches it will be completely dropped. In this case the queue number is don't care. | RW | 0
30 | compare_c_enable | Compare C Enable | RW | 0
29:25 | compare_c | Compare C - Index to screener type 2 Compare register | RW | 0x00
24 | compare_b_enable | Compare B Enable | RW | 0
23:19 | compare_b | Compare B - Index to screener type 2 Compare register | RW | 0x00
18 | compare_a_enable | Compare A Enable | RW | 0
17:13 | compare_a | Compare A - Index to screener type 2 Compare register | RW | 0x00
12 | ethertype_enable | EtherType Enable | RW | 0
11:9 | ethertype_reg_index | Index to screener type 2 EtherType register | RW | 0x0
8 | vlan_enable | VLAN Enable | RW | 0
7 | reserved_7 | Reserved and implemented as RW | RW | 0
6:4 | vlan_priority | VLAN Priority | RW | 0x0
3:0 | queue_number | Queue Number (0 to 15) | RW | 0x0

### gem_gxlmicrosemi : tx_sched_ctrl

Address offset | 0x0580
Description | This register controls the transmit scheduling algorithm the user can select for each active transmit queue. By default all queues are initialized to fixed priority, with the top indexed queue having overall priority.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:6 | tx_sched_q3 | Queue 3 selection., : 00 : Fixed Priority, : 01 : CBS Enabled only valid for top two enabled queues and if CBS capability selected., : 10 : DWRR Enabled, : 11 : ETS Enabled | RW | 0x0
5:4 | tx_sched_q2 | Queue 2 selection., : 00 : Fixed Priority, : 01 : CBS Enabled only valid for top two enabled queues and if CBS capability selected., : 10 : DWRR Enabled, : 11 : ETS Enabled | RW | 0x0
3:2 | tx_sched_q1 | Queue 1 selection., : 00 : Fixed Priority, : 01 : CBS Enabled only valid for top two enabled queues and if CBS capability selected., : 10 : DWRR Enabled, : 11 : ETS Enabled | RW | 0x0
1:0 | tx_sched_q0 | Queue 0 selection., : 00 : Fixed Priority, : 01 : CBS Enabled only valid for top two enabled queues and if CBS capability selected., : 10 : DWRR Enabled, : 11 : ETS Enabled | RW | 0x0

### gem_gxlmicrosemi : bw_rate_limit_q0to3

Address offset | 0x0590
Description | This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 0 to 3.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | dwrr_ets_weight_q3 | DWRR Weighting / ETS Bandwidth Allocation for queue 3 | RW | 0x00
23:16 | dwrr_ets_weight_q2 | DWRR Weighting / ETS Bandwidth Allocation for queue 2 | RW | 0x00
15:8 | dwrr_ets_weight_q1 | DWRR Weighting / ETS Bandwidth Allocation for queue 1 | RW | 0x00
7:0 | dwrr_ets_weight_q0 | DWRR Weighting / ETS Bandwidth Allocation for queue 0 | RW | 0x00

### gem_gxlmicrosemi : tx_q_seg_alloc_q_lower

Address offset | 0x05A0
Description | This register allows the user to distribute the Transmit SRAM used by the DMA across the priority queues, for queues 0 to 3. The SRAM itself is split into a number of evenly sized segments (this is defined in the verilog configuration defs file - for the configuration used to generate this register description, the total number of segments was set to '4'). Those segments can then be freely distributed across the active queues, in powers of 2. I.e. a value of 0 would mean 1 segment has been allocated to the queue. A value of 1 would mean 2 segments, a value of 2 means 4 segments and so on. The reset values of these registers are defined in the configuration defs file.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15 | reserved_15_15 | Reserved, read as 0, ignored on write. | RO | 0
14:12 | segment_alloc_q3 | Number of segments allocated to q3. This should be entered as a log 2, for example entering a value of 2 would grant 4 segments. A maximum of 16 segments can be granted. | RW | 0x0
11 | reserved_11_11 | Reserved, read as 0, ignored on write. | RO | 0
10:8 | segment_alloc_q2 | Number of segments allocated to q2. This should be entered as a log 2, for example entering a value of 2 would grant 4 segments. A maximum of 16 segments can be granted. | RW | 0x0
7 | reserved_7_7 | Reserved, read as 0, ignored on write. | RO | 0
6:4 | segment_alloc_q1 | Number of segments allocated to q1. This should be entered as a log 2, for example entering a value of 2 would grant 4 segments. A maximum of 16 segments can be granted. | RW | 0x0
3 | reserved_3_3 | Reserved, read as 0, ignored on write. | RO | 0
2:0 | segment_alloc_q0 | Number of segments allocated to q0. This should be entered as a log 2, for example entering a value of 2 would grant 4 segments. A maximum of 16 segments can be granted. | RW | 0x0

### gem_gxlmicrosemi : int_q1_enable

Address offset | 0x0600
Description | At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved_31_12 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
11 | enable_resp_not_ok_interrupt | Enable bresp/hresp not OK interrupt | WO | 0
10:8 | reserved_10_8 | Reserved, read as 0, ignored on write. | RO | 0x0
7 | enable_transmit_complete_interrupt | Enable Transmit complete interrupt | WO | 0
6 | enable_transmit_frame_corruption_due_to_amba_error_interrupt | Enable Transmit frame corruption due to AMBA (AHB/AXI) error interrupt | WO | 0
5 | enable_retry_limit_exceeded_or_late_collision_interrupt | Enable Retry limit exceeded or late collision interrupt | WO | 0
4:3 | reserved_4_3 | Reserved, read as 0, ignored on write. | RO | 0x0
2 | enable_rx_used_bit_read_interrupt | Enable RX used bit read interrupt | WO | 0
1 | enable_receive_complete_interrupt | Enable Receive complete interrupt | WO | 0
0 | reserved_0 | Reserved, read as 0, ignored on write. | RO | 0

### gem_gxlmicrosemi : int_q2_enable

Address offset | 0x0604
Description | At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved_31_12 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
11 | enable_resp_not_ok_interrupt | Enable bresp/hresp not OK interrupt | WO | 0
10:8 | reserved_10_8 | Reserved, read as 0, ignored on write. | RO | 0x0
7 | enable_transmit_complete_interrupt | Enable Transmit complete interrupt | WO | 0
6 | enable_transmit_frame_corruption_due_to_amba_error_interrupt | Enable Transmit frame corruption due to AMBA (AHB/AXI) error interrupt | WO | 0
5 | enable_retry_limit_exceeded_or_late_collision_interrupt | Enable Retry limit exceeded or late collision interrupt | WO | 0
4:3 | reserved_4_3 | Reserved, read as 0, ignored on write. | RO | 0x0
2 | enable_rx_used_bit_read_interrupt | Enable RX used bit read interrupt | WO | 0
1 | enable_receive_complete_interrupt | Enable Receive complete interrupt | WO | 0
0 | reserved_0 | Reserved, read as 0, ignored on write. | RO | 0

### gem_gxlmicrosemi : int_q3_enable

Address offset | 0x0608
Description | At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved_31_12 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
11 | enable_resp_not_ok_interrupt | Enable bresp/hresp not OK interrupt | WO | 0
10:8 | reserved_10_8 | Reserved, read as 0, ignored on write. | RO | 0x0
7 | enable_transmit_complete_interrupt | Enable Transmit complete interrupt | WO | 0
6 | enable_transmit_frame_corruption_due_to_amba_error_interrupt | Enable Transmit frame corruption due to AMBA (AHB/AXI) error interrupt | WO | 0
5 | enable_retry_limit_exceeded_or_late_collision_interrupt | Enable Retry limit exceeded or late collision interrupt | WO | 0
4:3 | reserved_4_3 | Reserved, read as 0, ignored on write. | RO | 0x0
2 | enable_rx_used_bit_read_interrupt | Enable RX used bit read interrupt | WO | 0
1 | enable_receive_complete_interrupt | Enable Receive complete interrupt | WO | 0
0 | reserved_0 | Reserved, read as 0, ignored on write. | RO | 0

### gem_gxlmicrosemi : int_q1_disable

Address offset | 0x0620
Description | Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved_31_12 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
11 | disable_resp_not_ok_interrupt | Disable bresp/hresp not OK interrupt | WO | 0
10:8 | reserved_10_8 | Reserved, read as 0, ignored on write. | RO | 0x0
7 | disable_transmit_complete_interrupt | Disable Transmit complete interrupt | WO | 0
6 | disable_transmit_frame_corruption_due_to_amba_error_interrupt | Disable Transmit frame corruption due to AMBA (AHB/AXI) error interrupt | WO | 0
5 | disable_retry_limit_exceeded_or_late_collision_interrupt | Disable Retry limit exceeded or late collision interrupt | WO | 0
4:3 | reserved_4_3 | Reserved, read as 0, ignored on write. | RO | 0x0
2 | disable_rx_used_bit_read_interrupt | Disable RX used bit read interrupt | WO | 0
1 | disable_receive_complete_interrupt | Disable Receive complete interrupt | WO | 0
0 | reserved_0 | Reserved, read as 0, ignored on write. | RO | 0

### gem_gxlmicrosemi : int_q2_disable

Address offset | 0x0624
Description | Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved_31_12 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
11 | disable_resp_not_ok_interrupt | Disable bresp/hresp not OK interrupt | WO | 0
10:8 | reserved_10_8 | Reserved, read as 0, ignored on write. | RO | 0x0
7 | disable_transmit_complete_interrupt | Disable Transmit complete interrupt | WO | 0
6 | disable_transmit_frame_corruption_due_to_amba_error_interrupt | Disable Transmit frame corruption due to AMBA (AHB/AXI) error interrupt | WO | 0
5 | disable_retry_limit_exceeded_or_late_collision_interrupt | Disable Retry limit exceeded or late collision interrupt | WO | 0
4:3 | reserved_4_3 | Reserved, read as 0, ignored on write. | RO | 0x0
2 | disable_rx_used_bit_read_interrupt | Disable RX used bit read interrupt | WO | 0
1 | disable_receive_complete_interrupt | Disable Receive complete interrupt | WO | 0
0 | reserved_0 | Reserved, read as 0, ignored on write. | RO | 0

### gem_gxlmicrosemi : int_q3_disable

Address offset | 0x0628
Description | Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved_31_12 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
11 | disable_resp_not_ok_interrupt | Disable bresp/hresp not OK interrupt | WO | 0
10:8 | reserved_10_8 | Reserved, read as 0, ignored on write. | RO | 0x0
7 | disable_transmit_complete_interrupt | Disable Transmit complete interrupt | WO | 0
6 | disable_transmit_frame_corruption_due_to_amba_error_interrupt | Disable Transmit frame corruption due to AMBA (AHB/AXI) error interrupt | WO | 0
5 | disable_retry_limit_exceeded_or_late_collision_interrupt | Disable Retry limit exceeded or late collision interrupt | WO | 0
4:3 | reserved_4_3 | Reserved, read as 0, ignored on write. | RO | 0x0
2 | disable_rx_used_bit_read_interrupt | Disable RX used bit read interrupt | WO | 0
1 | disable_receive_complete_interrupt | Disable Receive complete interrupt | WO | 0
0 | reserved_0 | Reserved, read as 0, ignored on write. | RO | 0

### gem_gxlmicrosemi : int_q1_mask

Address offset | 0x0640
Description | The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.
Type | RO

Bits | Field Name | Description | Type | Reset
31:12 | reserved_31_12 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
11 | resp_not_ok_interrupt_mask | bresp/hresp not OK interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
10:8 | reserved_10_8 | Reserved, read as 0, ignored on write. | RO | 0x0
7 | transmit_complete_interrupt_mask | Transmit complete interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
6 | amba_error_interrupt_mask | A read of this register returns the value of the AMBA (AHB/AXI) error interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
5 | retry_limit_exceeded_or_late_collision_interrupt_mask | retry limit exceeded or late collision interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
4:3 | reserved_4_3 | Reserved, read as 0, ignored on write. | RO | 0x0
2 | rx_used_interrupt_mask | A read of this register returns the value of the RX Used interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
1 | receive_complete_interrupt_mask | Receive complete interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
0 | reserved_0 | Reserved, read as 0, ignored on write. | RO | 0

### gem_gxlmicrosemi : int_q2_mask

Address offset | 0x0644
Description | The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.
Type | RO

Bits | Field Name | Description | Type | Reset
31:12 | reserved_31_12 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
11 | resp_not_ok_interrupt_mask | bresp/hresp not OK interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
10:8 | reserved_10_8 | Reserved, read as 0, ignored on write. | RO | 0x0
7 | transmit_complete_interrupt_mask | Transmit complete interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
6 | amba_error_interrupt_mask | A read of this register returns the value of the AMBA (AHB/AXI) error interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
5 | retry_limit_exceeded_or_late_collision_interrupt_mask | retry limit exceeded or late collision interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
4:3 | reserved_4_3 | Reserved, read as 0, ignored on write. | RO | 0x0
2 | rx_used_interrupt_mask | A read of this register returns the value of the RX Used interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
1 | receive_complete_interrupt_mask | Receive complete interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
0 | reserved_0 | Reserved, read as 0, ignored on write. | RO | 0

### gem_gxlmicrosemi : int_q3_mask

Address offset | 0x0648
Description | The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.
Type | RO

Bits | Field Name | Description | Type | Reset
31:12 | reserved_31_12 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
11 | resp_not_ok_interrupt_mask | bresp/hresp not OK interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
10:8 | reserved_10_8 | Reserved, read as 0, ignored on write. | RO | 0x0
7 | transmit_complete_interrupt_mask | Transmit complete interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
6 | amba_error_interrupt_mask | A read of this register returns the value of the AMBA (AHB/AXI) error interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
5 | retry_limit_exceeded_or_late_collision_interrupt_mask | retry limit exceeded or late collision interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
4:3 | reserved_4_3 | Reserved, read as 0, ignored on write. | RO | 0x0
2 | rx_used_interrupt_mask | A read of this register returns the value of the RX Used interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
1 | receive_complete_interrupt_mask | Receive complete interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
0 | reserved_0 | Reserved, read as 0, ignored on write. | RO | 0

### gem_gxlmicrosemi : screening_type_2_ethertype_reg_0

Address offset | 0x06E0
Description | EtherType Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write | RO | 0x0000
15:0 | compare_value | EtherType compare value | RW | 0x0000

### gem_gxlmicrosemi : screening_type_2_ethertype_reg_1

Address offset | 0x06E4
Description | EtherType Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write | RO | 0x0000
15:0 | compare_value | EtherType compare value | RW | 0x0000

### gem_gxlmicrosemi : screening_type_2_ethertype_reg_2

Address offset | 0x06E8
Description | EtherType Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write | RO | 0x0000
15:0 | compare_value | EtherType compare value | RW | 0x0000

### gem_gxlmicrosemi : screening_type_2_ethertype_reg_3

Address offset | 0x06EC
Description | EtherType Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write | RO | 0x0000
15:0 | compare_value | EtherType compare value | RW | 0x0000

### gem_gxlmicrosemi : type2_compare_0_word_0

Address offset | 0x0700
Description | Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | compare_value | 2 byte Compare Value., :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3., :, :If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1., : | RW | 0x0000
15:0 | mask_value | These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. , :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. , :, :If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. A value of zero in a mask bit masks the corresponding data bit, a value of 1 enables the comparison. | RW | 0x0000

### gem_gxlmicrosemi : type2_compare_0_word_1

Address offset | 0x0704
Description | Type2 Compare Word 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | compare_vlan_id | If set bits 9, 8 and 6:0 must be 0 and bit 7 of compare_offset is used as follows:, :0 Compare C-TAG VID (VLAN has EtherType of 0x8100), :1 Compare S-TAG VID comparison (VLAN has EtherType of the value in the stacked VLAN register at 0x00C0), :Note the byte order is such that if 81 00 00 20 is received to indicate a C-TAG frame with VID 020 0x00200FFF would be written to the compare register. So in the special case of VLAN comparison the last byte received is the least significant byte in the compare register | RW | 0
9 | disable_mask | This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value., :1 - 4-byte compare value, :0 - 2-byte compare, 2-byte mask | RW | 0
8:7 | compare_offset | Compare byte offset., :00 : Offset from beginning of the frame., :01 : Offset from byte after Ether Type., :10 : Offset from byte following end of IP header., :11 : Offset from byte following end of TCP/UDP header | RW | 0x0
6:0 | offset_value | Offset value in bytes | RW | 0x00

### gem_gxlmicrosemi : type2_compare_1_word_0

Address offset | 0x0708
Description | Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | compare_value | 2 byte Compare Value., :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3., :, :If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1., : | RW | 0x0000
15:0 | mask_value | These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. , :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. , :, :If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. A value of zero in a mask bit masks the corresponding data bit, a value of 1 enables the comparison. | RW | 0x0000

### gem_gxlmicrosemi : type2_compare_1_word_1

Address offset | 0x070C
Description | Type2 Compare Word 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | compare_vlan_id | If set bits 9, 8 and 6:0 must be 0 and bit 7 of compare_offset is used as follows:, :0 Compare C-TAG VID (VLAN has EtherType of 0x8100), :1 Compare S-TAG VID comparison (VLAN has EtherType of the value in the stacked VLAN register at 0x00C0), :Note the byte order is such that if 81 00 00 20 is received to indicate a C-TAG frame with VID 020 0x00200FFF would be written to the compare register. So in the special case of VLAN comparison the last byte received is the least significant byte in the compare register | RW | 0
9 | disable_mask | This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value., :1 - 4-byte compare value, :0 - 2-byte compare, 2-byte mask | RW | 0
8:7 | compare_offset | Compare byte offset., :00 : Offset from beginning of the frame., :01 : Offset from byte after Ether Type., :10 : Offset from byte following end of IP header., :11 : Offset from byte following end of TCP/UDP header | RW | 0x0
6:0 | offset_value | Offset value in bytes | RW | 0x00

### gem_gxlmicrosemi : type2_compare_2_word_0

Address offset | 0x0710
Description | Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | compare_value | 2 byte Compare Value., :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3., :, :If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1., : | RW | 0x0000
15:0 | mask_value | These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. , :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. , :, :If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. A value of zero in a mask bit masks the corresponding data bit, a value of 1 enables the comparison. | RW | 0x0000

### gem_gxlmicrosemi : type2_compare_2_word_1

Address offset | 0x0714
Description | Type2 Compare Word 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | compare_vlan_id | If set bits 9, 8 and 6:0 must be 0 and bit 7 of compare_offset is used as follows:, :0 Compare C-TAG VID (VLAN has EtherType of 0x8100), :1 Compare S-TAG VID comparison (VLAN has EtherType of the value in the stacked VLAN register at 0x00C0), :Note the byte order is such that if 81 00 00 20 is received to indicate a C-TAG frame with VID 020 0x00200FFF would be written to the compare register. So in the special case of VLAN comparison the last byte received is the least significant byte in the compare register | RW | 0
9 | disable_mask | This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value., :1 - 4-byte compare value, :0 - 2-byte compare, 2-byte mask | RW | 0
8:7 | compare_offset | Compare byte offset., :00 : Offset from beginning of the frame., :01 : Offset from byte after Ether Type., :10 : Offset from byte following end of IP header., :11 : Offset from byte following end of TCP/UDP header | RW | 0x0
6:0 | offset_value | Offset value in bytes | RW | 0x00

### gem_gxlmicrosemi : type2_compare_3_word_0

Address offset | 0x0718
Description | Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | compare_value | 2 byte Compare Value., :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3., :, :If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1., : | RW | 0x0000
15:0 | mask_value | These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. , :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. , :, :If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. A value of zero in a mask bit masks the corresponding data bit, a value of 1 enables the comparison. | RW | 0x0000

### gem_gxlmicrosemi : type2_compare_3_word_1

Address offset | 0x071C
Description | Type2 Compare Word 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | compare_vlan_id | If set bits 9, 8 and 6:0 must be 0 and bit 7 of compare_offset is used as follows:, :0 Compare C-TAG VID (VLAN has EtherType of 0x8100), :1 Compare S-TAG VID comparison (VLAN has EtherType of the value in the stacked VLAN register at 0x00C0), :Note the byte order is such that if 81 00 00 20 is received to indicate a C-TAG frame with VID 020 0x00200FFF would be written to the compare register. So in the special case of VLAN comparison the last byte received is the least significant byte in the compare register | RW | 0
9 | disable_mask | This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value., :1 - 4-byte compare value, :0 - 2-byte compare, 2-byte mask | RW | 0
8:7 | compare_offset | Compare byte offset., :00 : Offset from beginning of the frame., :01 : Offset from byte after Ether Type., :10 : Offset from byte following end of IP header., :11 : Offset from byte following end of TCP/UDP header | RW | 0x0
6:0 | offset_value | Offset value in bytes | RW | 0x00

### gem_gxlmicrosemi : enst_start_time_q0

Address offset | 0x0800
Description | This register sets the absolute time at which queue q0 starts EnST transmit scheduling
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | start_time_sec | Bits 31:30 of the start time (seconds field), for q0 | RW | 0x0
29:0 | start_time_nsec | Bits 29:0 of the start time (nanoseconds field), for q0 | RW | 0x0000 0000

### gem_gxlmicrosemi : enst_start_time_q1

Address offset | 0x0804
Description | This register sets the absolute time at which queue q1 starts EnST transmit scheduling
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | start_time_sec | Bits 31:30 of the start time (seconds field), for q1 | RW | 0x0
29:0 | start_time_nsec | Bits 29:0 of the start time (nanoseconds field), for q1 | RW | 0x0000 0000

### gem_gxlmicrosemi : enst_start_time_q2

Address offset | 0x0808
Description | This register sets the absolute time at which queue q2 starts EnST transmit scheduling
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | start_time_sec | Bits 31:30 of the start time (seconds field), for q2 | RW | 0x0
29:0 | start_time_nsec | Bits 29:0 of the start time (nanoseconds field), for q2 | RW | 0x0000 0000

### gem_gxlmicrosemi : enst_start_time_q3

Address offset | 0x080C
Description | This register sets the absolute time at which queue q3 starts EnST transmit scheduling
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | start_time_sec | Bits 31:30 of the start time (seconds field), for q3 | RW | 0x0
29:0 | start_time_nsec | Bits 29:0 of the start time (nanoseconds field), for q3 | RW | 0x0000 0000

### gem_gxlmicrosemi : enst_on_time_q0

Address offset | 0x0820
Description | This register sets the time period for which queue q0 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | on_time | on_time, for q0 | RW | 0x1 FFFF

### gem_gxlmicrosemi : enst_on_time_q1

Address offset | 0x0824
Description | This register sets the time period for which queue q1 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | on_time | on_time, for q1 | RW | 0x1 FFFF

### gem_gxlmicrosemi : enst_on_time_q2

Address offset | 0x0828
Description | This register sets the time period for which queue q2 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | on_time | on_time, for q2 | RW | 0x1 FFFF

### gem_gxlmicrosemi : enst_on_time_q3

Address offset | 0x082C
Description | This register sets the time period for which queue q3 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | on_time | on_time, for q3 | RW | 0x1 FFFF

### gem_gxlmicrosemi : enst_off_time_q0

Address offset | 0x0840
Description | This register sets the time period for which queue q0 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | off_time | Off_time, for q0 | RW | 0x0 0000

### gem_gxlmicrosemi : enst_off_time_q1

Address offset | 0x0844
Description | This register sets the time period for which queue q1 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | off_time | Off_time, for q1 | RW | 0x0 0000

### gem_gxlmicrosemi : enst_off_time_q2

Address offset | 0x0848
Description | This register sets the time period for which queue q2 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | off_time | Off_time, for q2 | RW | 0x0 0000

### gem_gxlmicrosemi : enst_off_time_q3

Address offset | 0x084C
Description | This register sets the time period for which queue q3 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | off_time | Off_time, for q3 | RW | 0x0 0000

### gem_gxlmicrosemi : enst_control

Address offset | 0x0880
Description | Enhancement for Scheduled Traffic control register. EnST scheduling can only be applied to a maximum number of 8 queues. If 802.3br operation has been configured and both an eMAC and pMAC are present then the eMAC only supports a single queue and EnST is enabled on the eMAC by writing to bit 0 of emac_enst_control.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:4 | reserved_7_4 | Reserved. | RW | 0x0
3 | enst_enable_q3 | Set to enable enhanced scheduler traffic (ENST), for q3 | RW | 0
2 | enst_enable_q2 | Set to enable enhanced scheduler traffic (ENST), for q2 | RW | 0
1 | enst_enable_q1 | Set to enable enhanced scheduler traffic (ENST), for q1 | RW | 0
0 | enst_enable_q0 | Set to enable enhanced scheduler traffic (ENST), for q0 | RW | 0

### gem_gxlmicrosemi : frer_timeout

Address offset | 0x08A0
Description | FRER timeout register. This determines when the sequence recovery reset timers are reset and is used by all of the configured CB streams. It is programmed as a count of 8192 rx_clk periods. 8192 rx_clk periods is 65.536 microseconds at gigabit speeds and 327.68 microseconds at 100M speeds, this allows a max timeout value of about 4 seconds at gigabit speeds - for test purposes if bit 12 (retry_test) is set in the network configuration register at 0x004 then the timeout value just becomes a count of rx_clk periods (ie a speed-up of 8192 in the time-out process).
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | timeout | Count of 8192 rx_clk periods. | RW | 0x0000

### gem_gxlmicrosemi : frer_red_tag

Address offset | 0x08A4
Description | FRER redundancy tag register. This defines the Ethertype used to identify the R-TAG (redundancy tag) and contains a control bit to enable stripping of the R-TAG from received frames. IEEE 802.1CB has defined the value of this Ethertype to be 0xF1C1. Whether or not a particular stream uses the redundancy tag to locate the sequence number is determined by bit 28 in that streams control register.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | strip_r_tag | If set the redundancy tag is stripped from received frames. If this bit is set then the receive octet counters reflect post deletion frame size so the FRER functionality is transparent to higher level management if the stripping function is enabled. If the statistics counters need to reflect the actual number of octets received, then the stripping functionality should be disabled. | RW | 0
30 | six_byte_tag | Draft 2.4 and earlier drafts of the 802.1CB standard defined a four-byte redundancy tag. Drafts 2.5 and later specified a six-byte tag. Releases 1p10 and 1p11 were implemented in accordance with draft 2.4 of the standard. Set this bit to zero to inter-operate with implementations that use a four-byte tag. | RW | 1
29:16 | reserved_29_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | redundancy_tag | Ethertype value used to identify the redundancy tag (R-TAG). | RW | 0xF1C1

### gem_gxlmicrosemi : frer_control_1_a

Address offset | 0x08C0
Description | FRER control register A
Type | RW

Bits | Field Name | Description | Type | Reset
31 | en_elimination | Enable 802.1CB elimination of received frames | RW | 0
30 | en_vector_rec_alg | Enable 802.1CB vector recovery algorithm, : 0 enables the match recovery algorithm, : 1 enables the vector recovery algorithm, :This bit should only be changed when bit 31 en_elimination is low | RW | 0
29 | en_seqrecrst_timer | Enable 802.1CB sequence recovery reset timer - this bit may be changed when bit 31 en_elimination is low | RW | 0
28 | use_r_tag | Set to one to use redundancy tag to identify sequence number otherwise use offset value to identify bottom of sequence number - this bit should only be changed when bit 31 en_elimination is low | RW | 0
27:17 | reserved_27_17 | Reserved, read as 0, ignored on write. | RO | 0x000
16:8 | offset_value | Offset value in bytes from the start packet delimiter to the most significant byte of the 802.1CB sequence number - 9 bits allow a maximum value of 511 - allowing a TCP sequence number to be used with IPv6 - this bit should only be changed when en_elimination is low | RW | 0x000
7:4 | member_stream_2 | Pointer to screener type 2 register used for member stream identification. The member stream 1 and 2 values may be programmed to identical values. - this bit should only be changed when en_elimination is low | RW | 0x0
3:0 | member_stream_1 | Pointer to screener type 2 register used for member stream identification. The member stream 1 and 2 values may be programmed to identical values. - this bit should only be changed when en_elimination is low | RW | 0x0

### gem_gxlmicrosemi : frer_control_1_b

Address offset | 0x08C4
Description | FRER control register B. This register has default values where the sequence number length defaults to 16 and the vector recovery window defaults to the size of the history vector. It is not expected that the user will need to change these default values.
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | reserved_31_13 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
12:8 | seq_num_length | Number of significant bits of the 802.1CB sequence number. The value 0x00 or numbers greater than 16 bits are equivalent to 16, but the number written will still be read back if it is greater than 16. If a value of less than 16 is written, then the sequence recovery algorithm will only consider that number of LSBs of the sequence number. The minimum size of seq_num_length has to be such that 2^seq_num_len is at least 2xgem_seq_history_len otherwise the vector recovery algorithm will not work correctly - this bit should only be changed when en_elimination is low | RW | 0x00
7:6 | reserved_7_6 | Reserved, read as 0, ignored on write. | RO | 0x0
5:0 | seq_rec_window | Vector recovery window, defines the window size used by the vector recovery algorithm to determine whether to reject a packet. Six bits allow a window size of 63, for effective operation of FRER users should not write a value greater than the gem_seq_history_len configuration define, a value of zero means the entire history vector is used - this bit should only be changed when en_elimination is low. | RW | 0x00

### gem_gxlmicrosemi : frer_statistics_1_a

Address offset | 0x08C8
Description | FRER statistics register A. This register is cleared on a read and does not roll over if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:26 | reserved_31_26 | Reserved, read as 0, ignored on write. | RO | 0x00
25:16 | vec_rec_rogue | Count of number of frames dropped by the vector recovery algorithm for being out of range | RO RtoClr | 0x000
15:10 | reserved_15_10 | Reserved, read as 0, ignored on write. | RO | 0x00
9:0 | latent_errors | Count of sequence numbers seen without a duplicate. The latent error count is updated when a frame is dropped from the history vector. So the update only happens after a new frame is received. | RO RtoClr | 0x000

### gem_gxlmicrosemi : frer_statistics_1_b

Address offset | 0x08CC
Description | FRER statistics register B. This register is cleared on a read and does not roll over if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | seqrst_count | Count of number of times the sequence recovery reset timer decrements to zero. | RO RtoClr | 0x00
15:10 | reserved_15_10 | Reserved, read as 0, ignored on write. | RO | 0x00
9:0 | out_of_order | Count of out of order sequence numbers received. Incremented when a frame is accepted but the sequence number is not +1 of the highest stored value. | RO RtoClr | 0x000

### gem_gxlmicrosemi : frer_control_2_a

Address offset | 0x08D0
Description | FRER control register A
Type | RW

Bits | Field Name | Description | Type | Reset
31 | en_elimination | Enable 802.1CB elimination of received frames | RW | 0
30 | en_vector_rec_alg | Enable 802.1CB vector recovery algorithm, : 0 enables the match recovery algorithm, : 1 enables the vector recovery algorithm, :This bit should only be changed when bit 31 en_elimination is low | RW | 0
29 | en_seqrecrst_timer | Enable 802.1CB sequence recovery reset timer - this bit may be changed when bit 31 en_elimination is low | RW | 0
28 | use_r_tag | Set to one to use redundancy tag to identify sequence number otherwise use offset value to identify bottom of sequence number - this bit should only be changed when bit 31 en_elimination is low | RW | 0
27:17 | reserved_27_17 | Reserved, read as 0, ignored on write. | RO | 0x000
16:8 | offset_value | Offset value in bytes from the start packet delimiter to the most significant byte of the 802.1CB sequence number - 9 bits allow a maximum value of 511 - allowing a TCP sequence number to be used with IPv6 - this bit should only be changed when en_elimination is low | RW | 0x000
7:4 | member_stream_2 | Pointer to screener type 2 register used for member stream identification. The member stream 1 and 2 values may be programmed to identical values. - this bit should only be changed when en_elimination is low | RW | 0x0
3:0 | member_stream_1 | Pointer to screener type 2 register used for member stream identification. The member stream 1 and 2 values may be programmed to identical values. - this bit should only be changed when en_elimination is low | RW | 0x0

### gem_gxlmicrosemi : frer_control_2_b

Address offset | 0x08D4
Description | FRER control register B. This register has default values where the sequence number length defaults to 16 and the vector recovery window defaults to the size of the history vector. It is not expected that the user will need to change these default values.
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | reserved_31_13 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
12:8 | seq_num_length | Number of significant bits of the 802.1CB sequence number. The value 0x00 or numbers greater than 16 bits are equivalent to 16, but the number written will still be read back if it is greater than 16. If a value of less than 16 is written, then the sequence recovery algorithm will only consider that number of LSBs of the sequence number. The minimum size of seq_num_length has to be such that 2^seq_num_len is at least 2xgem_seq_history_len otherwise the vector recovery algorithm will not work correctly - this bit should only be changed when en_elimination is low | RW | 0x00
7:6 | reserved_7_6 | Reserved, read as 0, ignored on write. | RO | 0x0
5:0 | seq_rec_window | Vector recovery window, defines the window size used by the vector recovery algorithm to determine whether to reject a packet. Six bits allow a window size of 63, for effective operation of FRER users should not write a value greater than the gem_seq_history_len configuration define, a value of zero means the entire history vector is used - this bit should only be changed when en_elimination is low. | RW | 0x00

### gem_gxlmicrosemi : frer_statistics_2_a

Address offset | 0x08D8
Description | FRER statistics register A. This register is cleared on a read and does not roll over if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:26 | reserved_31_26 | Reserved, read as 0, ignored on write. | RO | 0x00
25:16 | vec_rec_rogue | Count of number of frames dropped by the vector recovery algorithm for being out of range | RO RtoClr | 0x000
15:10 | reserved_15_10 | Reserved, read as 0, ignored on write. | RO | 0x00
9:0 | latent_errors | Count of sequence numbers seen without a duplicate. The latent error count is updated when a frame is dropped from the history vector. So the update only happens after a new frame is received. | RO RtoClr | 0x000

### gem_gxlmicrosemi : frer_statistics_2_b

Address offset | 0x08DC
Description | FRER statistics register B. This register is cleared on a read and does not roll over if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | seqrst_count | Count of number of times the sequence recovery reset timer decrements to zero. | RO RtoClr | 0x00
15:10 | reserved_15_10 | Reserved, read as 0, ignored on write. | RO | 0x00
9:0 | out_of_order | Count of out of order sequence numbers received. Incremented when a frame is accepted but the sequence number is not +1 of the highest stored value. | RO RtoClr | 0x000

### gem_gxlmicrosemi : frer_control_3_a

Address offset | 0x08E0
Description | FRER control register A
Type | RW

Bits | Field Name | Description | Type | Reset
31 | en_elimination | Enable 802.1CB elimination of received frames | RW | 0
30 | en_vector_rec_alg | Enable 802.1CB vector recovery algorithm, : 0 enables the match recovery algorithm, : 1 enables the vector recovery algorithm, :This bit should only be changed when bit 31 en_elimination is low | RW | 0
29 | en_seqrecrst_timer | Enable 802.1CB sequence recovery reset timer - this bit may be changed when bit 31 en_elimination is low | RW | 0
28 | use_r_tag | Set to one to use redundancy tag to identify sequence number otherwise use offset value to identify bottom of sequence number - this bit should only be changed when bit 31 en_elimination is low | RW | 0
27:17 | reserved_27_17 | Reserved, read as 0, ignored on write. | RO | 0x000
16:8 | offset_value | Offset value in bytes from the start packet delimiter to the most significant byte of the 802.1CB sequence number - 9 bits allow a maximum value of 511 - allowing a TCP sequence number to be used with IPv6 - this bit should only be changed when en_elimination is low | RW | 0x000
7:4 | member_stream_2 | Pointer to screener type 2 register used for member stream identification. The member stream 1 and 2 values may be programmed to identical values. - this bit should only be changed when en_elimination is low | RW | 0x0
3:0 | member_stream_1 | Pointer to screener type 2 register used for member stream identification. The member stream 1 and 2 values may be programmed to identical values. - this bit should only be changed when en_elimination is low | RW | 0x0

### gem_gxlmicrosemi : frer_control_3_b

Address offset | 0x08E4
Description | FRER control register B. This register has default values where the sequence number length defaults to 16 and the vector recovery window defaults to the size of the history vector. It is not expected that the user will need to change these default values.
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | reserved_31_13 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
12:8 | seq_num_length | Number of significant bits of the 802.1CB sequence number. The value 0x00 or numbers greater than 16 bits are equivalent to 16, but the number written will still be read back if it is greater than 16. If a value of less than 16 is written, then the sequence recovery algorithm will only consider that number of LSBs of the sequence number. The minimum size of seq_num_length has to be such that 2^seq_num_len is at least 2xgem_seq_history_len otherwise the vector recovery algorithm will not work correctly - this bit should only be changed when en_elimination is low | RW | 0x00
7:6 | reserved_7_6 | Reserved, read as 0, ignored on write. | RO | 0x0
5:0 | seq_rec_window | Vector recovery window, defines the window size used by the vector recovery algorithm to determine whether to reject a packet. Six bits allow a window size of 63, for effective operation of FRER users should not write a value greater than the gem_seq_history_len configuration define, a value of zero means the entire history vector is used - this bit should only be changed when en_elimination is low. | RW | 0x00

### gem_gxlmicrosemi : frer_statistics_3_a

Address offset | 0x08E8
Description | FRER statistics register A. This register is cleared on a read and does not roll over if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:26 | reserved_31_26 | Reserved, read as 0, ignored on write. | RO | 0x00
25:16 | vec_rec_rogue | Count of number of frames dropped by the vector recovery algorithm for being out of range | RO RtoClr | 0x000
15:10 | reserved_15_10 | Reserved, read as 0, ignored on write. | RO | 0x00
9:0 | latent_errors | Count of sequence numbers seen without a duplicate. The latent error count is updated when a frame is dropped from the history vector. So the update only happens after a new frame is received. | RO RtoClr | 0x000

### gem_gxlmicrosemi : frer_statistics_3_b

Address offset | 0x08EC
Description | FRER statistics register B. This register is cleared on a read and does not roll over if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | seqrst_count | Count of number of times the sequence recovery reset timer decrements to zero. | RO RtoClr | 0x00
15:10 | reserved_15_10 | Reserved, read as 0, ignored on write. | RO | 0x00
9:0 | out_of_order | Count of out of order sequence numbers received. Incremented when a frame is accepted but the sequence number is not +1 of the highest stored value. | RO RtoClr | 0x000

### gem_gxlmicrosemi : frer_control_4_a

Address offset | 0x08F0
Description | FRER control register A
Type | RW

Bits | Field Name | Description | Type | Reset
31 | en_elimination | Enable 802.1CB elimination of received frames | RW | 0
30 | en_vector_rec_alg | Enable 802.1CB vector recovery algorithm, : 0 enables the match recovery algorithm, : 1 enables the vector recovery algorithm, :This bit should only be changed when bit 31 en_elimination is low | RW | 0
29 | en_seqrecrst_timer | Enable 802.1CB sequence recovery reset timer - this bit may be changed when bit 31 en_elimination is low | RW | 0
28 | use_r_tag | Set to one to use redundancy tag to identify sequence number otherwise use offset value to identify bottom of sequence number - this bit should only be changed when bit 31 en_elimination is low | RW | 0
27:17 | reserved_27_17 | Reserved, read as 0, ignored on write. | RO | 0x000
16:8 | offset_value | Offset value in bytes from the start packet delimiter to the most significant byte of the 802.1CB sequence number - 9 bits allow a maximum value of 511 - allowing a TCP sequence number to be used with IPv6 - this bit should only be changed when en_elimination is low | RW | 0x000
7:4 | member_stream_2 | Pointer to screener type 2 register used for member stream identification. The member stream 1 and 2 values may be programmed to identical values. - this bit should only be changed when en_elimination is low | RW | 0x0
3:0 | member_stream_1 | Pointer to screener type 2 register used for member stream identification. The member stream 1 and 2 values may be programmed to identical values. - this bit should only be changed when en_elimination is low | RW | 0x0

### gem_gxlmicrosemi : frer_control_4_b

Address offset | 0x08F4
Description | FRER control register B. This register has default values where the sequence number length defaults to 16 and the vector recovery window defaults to the size of the history vector. It is not expected that the user will need to change these default values.
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | reserved_31_13 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
12:8 | seq_num_length | Number of significant bits of the 802.1CB sequence number. The value 0x00 or numbers greater than 16 bits are equivalent to 16, but the number written will still be read back if it is greater than 16. If a value of less than 16 is written, then the sequence recovery algorithm will only consider that number of LSBs of the sequence number. The minimum size of seq_num_length has to be such that 2^seq_num_len is at least 2xgem_seq_history_len otherwise the vector recovery algorithm will not work correctly - this bit should only be changed when en_elimination is low | RW | 0x00
7:6 | reserved_7_6 | Reserved, read as 0, ignored on write. | RO | 0x0
5:0 | seq_rec_window | Vector recovery window, defines the window size used by the vector recovery algorithm to determine whether to reject a packet. Six bits allow a window size of 63, for effective operation of FRER users should not write a value greater than the gem_seq_history_len configuration define, a value of zero means the entire history vector is used - this bit should only be changed when en_elimination is low. | RW | 0x00

### gem_gxlmicrosemi : frer_statistics_4_a

Address offset | 0x08F8
Description | FRER statistics register A. This register is cleared on a read and does not roll over if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:26 | reserved_31_26 | Reserved, read as 0, ignored on write. | RO | 0x00
25:16 | vec_rec_rogue | Count of number of frames dropped by the vector recovery algorithm for being out of range | RO RtoClr | 0x000
15:10 | reserved_15_10 | Reserved, read as 0, ignored on write. | RO | 0x00
9:0 | latent_errors | Count of sequence numbers seen without a duplicate. The latent error count is updated when a frame is dropped from the history vector. So the update only happens after a new frame is received. | RO RtoClr | 0x000

### gem_gxlmicrosemi : frer_statistics_4_b

Address offset | 0x08FC
Description | FRER statistics register B. This register is cleared on a read and does not roll over if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | seqrst_count | Count of number of times the sequence recovery reset timer decrements to zero. | RO RtoClr | 0x00
15:10 | reserved_15_10 | Reserved, read as 0, ignored on write. | RO | 0x00
9:0 | out_of_order | Count of out of order sequence numbers received. Incremented when a frame is accepted but the sequence number is not +1 of the highest stored value. | RO RtoClr | 0x000

### gem_gxlmicrosemi : rx_q0_flush

Address offset | 0x0B00
Description | Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | max_val | This 16 bit vector is used when either bit 2 or 3 of this register is asserted. Refer to the description in those bits for details. | RW | 0x0000
15:4 | reserved_15_4 | Reserved, read as 0, ignored on write. | RO | 0x000
3 | limit_frame_size | When set max_val (bits 31:16) indicates the maximum frame-length in bytes that may be received. Frames exceeding this length will be dropped. This traffic policing function is relevant to the 802.1Qci standard which specifies stream filtering based on a maximum SDU (service data unit) size. | RW | 0
2 | limit_num_bytes | When set, the number of 128 byte chunks of data received for this queue and already stored in the SRAM awaiting DMA memory writes cannot exceed max_val (bits 31:16). | RW | 0
1 | drop_on_resource_err | When set, if a free DMA descriptor for this queue cannot be obtained (also referred to as lack of descriptor resource and occurs when the software either cannot free up descriptors quickly enough to meet the receive traffic rate or has deliberately decided not to free any descriptors), all new frames received on this queue will be automatically discarded. | RW | 0
0 | drop_all_frames | When set, all frames on this queue will be dropped. | RW | 0

### gem_gxlmicrosemi : rx_q1_flush

Address offset | 0x0B04
Description | Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | max_val | This 16 bit vector is used when either bit 2 or 3 of this register is asserted. Refer to the description in those bits for details. | RW | 0x0000
15:4 | reserved_15_4 | Reserved, read as 0, ignored on write. | RO | 0x000
3 | limit_frame_size | When set max_val (bits 31:16) indicates the maximum frame-length in bytes that may be received. Frames exceeding this length will be dropped. This traffic policing function is relevant to the 802.1Qci standard which specifies stream filtering based on a maximum SDU (service data unit) size. | RW | 0
2 | limit_num_bytes | When set, the number of 128 byte chunks of data received for this queue and already stored in the SRAM awaiting DMA memory writes cannot exceed max_val (bits 31:16). | RW | 0
1 | drop_on_resource_err | When set, if a free DMA descriptor for this queue cannot be obtained (also referred to as lack of descriptor resource and occurs when the software either cannot free up descriptors quickly enough to meet the receive traffic rate or has deliberately decided not to free any descriptors), all new frames received on this queue will be automatically discarded. | RW | 0
0 | drop_all_frames | When set, all frames on this queue will be dropped. | RW | 0

### gem_gxlmicrosemi : rx_q2_flush

Address offset | 0x0B08
Description | Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | max_val | This 16 bit vector is used when either bit 2 or 3 of this register is asserted. Refer to the description in those bits for details. | RW | 0x0000
15:4 | reserved_15_4 | Reserved, read as 0, ignored on write. | RO | 0x000
3 | limit_frame_size | When set max_val (bits 31:16) indicates the maximum frame-length in bytes that may be received. Frames exceeding this length will be dropped. This traffic policing function is relevant to the 802.1Qci standard which specifies stream filtering based on a maximum SDU (service data unit) size. | RW | 0
2 | limit_num_bytes | When set, the number of 128 byte chunks of data received for this queue and already stored in the SRAM awaiting DMA memory writes cannot exceed max_val (bits 31:16). | RW | 0
1 | drop_on_resource_err | When set, if a free DMA descriptor for this queue cannot be obtained (also referred to as lack of descriptor resource and occurs when the software either cannot free up descriptors quickly enough to meet the receive traffic rate or has deliberately decided not to free any descriptors), all new frames received on this queue will be automatically discarded. | RW | 0
0 | drop_all_frames | When set, all frames on this queue will be dropped. | RW | 0

### gem_gxlmicrosemi : rx_q3_flush

Address offset | 0x0B0C
Description | Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | max_val | This 16 bit vector is used when either bit 2 or 3 of this register is asserted. Refer to the description in those bits for details. | RW | 0x0000
15:4 | reserved_15_4 | Reserved, read as 0, ignored on write. | RO | 0x000
3 | limit_frame_size | When set max_val (bits 31:16) indicates the maximum frame-length in bytes that may be received. Frames exceeding this length will be dropped. This traffic policing function is relevant to the 802.1Qci standard which specifies stream filtering based on a maximum SDU (service data unit) size. | RW | 0
2 | limit_num_bytes | When set, the number of 128 byte chunks of data received for this queue and already stored in the SRAM awaiting DMA memory writes cannot exceed max_val (bits 31:16). | RW | 0
1 | drop_on_resource_err | When set, if a free DMA descriptor for this queue cannot be obtained (also referred to as lack of descriptor resource and occurs when the software either cannot free up descriptors quickly enough to meet the receive traffic rate or has deliberately decided not to free any descriptors), all new frames received on this queue will be automatically discarded. | RW | 0
0 | drop_all_frames | When set, all frames on this queue will be dropped. | RW | 0

### gem_gxlmicrosemi : scr2_reg0_rate_limit

Address offset | 0x0B40
Description | Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | max_rate_val | This is the maximum number of bytes this screener is permitted to match in the programmed interval time. | RW | 0x0000
15:0 | interval_time | If during the interval time the total number of bytes of received frames matched by the screener exceeds max_rate_val then the current frame and frames subsequently matched will dropped until an interval time passes where max_rate_val is not exceeded. If this value is set to zero, then no rate limiting will be performed. The interval time is specified in units of 64 rx_clk periods. | RW | 0x0000

### gem_gxlmicrosemi : scr2_reg1_rate_limit

Address offset | 0x0B44
Description | Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | max_rate_val | This is the maximum number of bytes this screener is permitted to match in the programmed interval time. | RW | 0x0000
15:0 | interval_time | If during the interval time the total number of bytes of received frames matched by the screener exceeds max_rate_val then the current frame and frames subsequently matched will dropped until an interval time passes where max_rate_val is not exceeded. If this value is set to zero, then no rate limiting will be performed. The interval time is specified in units of 64 rx_clk periods. | RW | 0x0000

### gem_gxlmicrosemi : scr2_reg2_rate_limit

Address offset | 0x0B48
Description | Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | max_rate_val | This is the maximum number of bytes this screener is permitted to match in the programmed interval time. | RW | 0x0000
15:0 | interval_time | If during the interval time the total number of bytes of received frames matched by the screener exceeds max_rate_val then the current frame and frames subsequently matched will dropped until an interval time passes where max_rate_val is not exceeded. If this value is set to zero, then no rate limiting will be performed. The interval time is specified in units of 64 rx_clk periods. | RW | 0x0000

### gem_gxlmicrosemi : scr2_reg3_rate_limit

Address offset | 0x0B4C
Description | Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | max_rate_val | This is the maximum number of bytes this screener is permitted to match in the programmed interval time. | RW | 0x0000
15:0 | interval_time | If during the interval time the total number of bytes of received frames matched by the screener exceeds max_rate_val then the current frame and frames subsequently matched will dropped until an interval time passes where max_rate_val is not exceeded. If this value is set to zero, then no rate limiting will be performed. The interval time is specified in units of 64 rx_clk periods. | RW | 0x0000

### gem_gxlmicrosemi : scr2_rate_status

Address offset | 0x0B80
Description | Screener rate limit exceeded status register. For each screener type 2 register configured a status bit will be set and cleared on read if the maximum receive rate is exceeded.
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:4 | reserved_15_4 | Reserved, read as 0, ignored on write. | RO | 0x000
3 | scr2_3_excess_rate | Set to 1 if screeners rate limiting mechanism has been triggered | RO RtoClr | 0
2 | scr2_2_excess_rate | Set to 1 if screeners rate limiting mechanism has been triggered | RO RtoClr | 0
1 | scr2_1_excess_rate | Set to 1 if screeners rate limiting mechanism has been triggered | RO RtoClr | 0
0 | scr2_0_excess_rate | Set to 1 if screeners rate limiting mechanism has been triggered | RO RtoClr | 0

### gem_gxlmicrosemi : asf_int_status

Address offset | 0x0E00
Description | ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the asf_fatal or asf_nonfatal signal will be asserted. Writing to either raw or masked status registers, clear both registers. For test purposes, trigger signal interrupt event by writing to the ASF interrupt status test register.
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved_31_7 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
6 | reserved_6 | Reserved, read as 0, ignored on write. | RO | 0
5 | asf_protocol_err | Protocol error interrupt | RW W1toClr | 0
4 | asf_trans_to_err | Transaction timeouts error interrupt | RW W1toClr | 0
3 | reserved_3 | Reserved, read as 0, ignored on write. | RO | 0
2 | reserved_2 | Reserved, read as 0, ignored on write. | RO | 0
1:0 | reserved_1_0 | Reserved for SRAM ECC, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : asf_int_raw_status

Address offset | 0x0E04
Description | ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers, clear both registers. For test purposes, trigger signal interrupt event by writing to the ASF interrupt status test register.
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved_31_7 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
6 | reserved_6 | Reserved, read as 0, ignored on write. | RO | 0
5 | asf_protocol_err | Protocol error interrupt | RW W1toClr | 0
4 | asf_trans_to_err | Transaction timeouts error interrupt | RW W1toClr | 0
3 | reserved_3 | Reserved, read as 0, ignored on write. | RO | 0
2 | reserved_2 | Reserved, read as 0, ignored on write. | RO | 0
1:0 | reserved_1_0 | Reserved for SRAM ECC, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : asf_int_mask

Address offset | 0x0E08
Description | The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding interrupt.
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved_31_7 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
6 | reserved_6 | Reserved, read as 0, ignored on write. | RO | 0
5 | asf_protocol_err_mask | Mask bit for protocol error interrupt. | RW | 1
4 | asf_trans_to_err_mask | Mask bit for transaction timeouts error interrupt. | RW | 1
3 | reserved_3 | Reserved, read as 0, ignored on write. | RO | 0
2 | reserved_2 | Reserved, read as 0, ignored on write. | RO | 0
1:0 | reserved_1_0 | Reserved for SRAM ECC, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : asf_int_test

Address offset | 0x0E0C
Description | The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly.
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved_31_7 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
6 | reserved_6 | Reserved, read as 0, ignored on write. | RO | 0
5 | asf_protocol_err_test | Test bit for protocol error interrupt. | WO | 0
4 | asf_trans_to_err_test | Test bit for transaction timeouts error interrupt. | WO | 0
3 | reserved_3 | Reserved, read as 0, ignored on write. | RO | 0
2 | reserved_2 | Reserved, read as 0, ignored on write. | RO | 0
1:0 | reserved_1_0 | Reserved for SRAM ECC, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : asf_fatal_nonfatal_select

Address offset | 0x0E10
Description | The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then fatal interrupt (asf_int_fatal) will be triggered. Otherwise the non-fatal interrupt (asf_int_nonfatal) will be triggered.
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved_31_7 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
6 | reserved_6 | Reserved, read as 0, ignored on write. | RO | 0
5 | asf_protocol_err | Enable protocol error interrupt as fatal. | RW | 1
4 | asf_trans_to_err | Enable transaction timeouts error interrupt as fatal. | RW | 1
3 | reserved_3 | Reserved, read as 0, ignored on write. | RO | 0
2 | reserved_2 | Reserved, read as 0, ignored on write. | RO | 0
1:0 | reserved_1_0 | Reserved for SRAM ECC, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : asf_trans_to_fault_mask

Address offset | 0x0E34
Description | Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset, all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source.
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved_31_5 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
4 | reserved_4 | Reserved, read as 0, ignored on write. | RO | 0
3 | dma_rx_to_mask | Mask register for DMA RX lockup detection. | RW | 1
2 | dma_tx_to_mask | Mask register for DMA TX lockup detection. | RW | 1
1 | mac_rx_to_mask | Mask register for MAC RX lockup detection. | RW | 1
0 | mac_tx_to_mask | Mask register for MAC TX lockup detection. | RW | 1

### gem_gxlmicrosemi : asf_trans_to_fault_status

Address offset | 0x0E38
Description | Status register for transaction timeouts fault. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit.
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved_31_5 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
4 | reserved_4 | Reserved, read as 0, ignored on write. | RO | 0
3 | dma_rx_to_status | Status bit for DMA RX lockup detection. | RW W1toClr | 0
2 | dma_tx_to_status | Status bit for DMA TX lockup detection. | RW W1toClr | 0
1 | mac_rx_to_status | Status bit for MAC RX lockup detection. | RW W1toClr | 0
0 | mac_tx_to_status | Status bit for MAC TX lockup detection. | RW W1toClr | 0

### gem_gxlmicrosemi : asf_protocol_fault_mask

Address offset | 0x0E40
Description | Control register to mask out ASF Protocol faults from triggering interrupts. On reset, all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source.
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved_31_22 | Reserved, read as 0, ignored on write. | RO | 0x000
21 | rx_dma_pkt_flush_mask | Mask bit for RX packet was flushed from the DMA. | RW | 1
20 | rx_overflow_mask | Mask bit for DMA buffer overflow and packet was dropped. | RW | 1
19 | rx_hresp_err_mask | Mask bit for DMA hresp error (AHB only). | RW | 1
18 | tx_hresp_err_mask | Mask bit for DMA hresp error (AHB only). | RW | 1
17 | tx_buff_ex_mid_mask | Mask bit for Transmit buffers exhausted before end of packet. | RW | 1
16 | tx_underrun_mask | Mask bit for Transmit DMA underrun occurred. | RW | 1
15:9 | reserved_15_9 | Reserved, read as 0, ignored on write. | RO | 0x00
8 | tx_too_many_retries_mask | Mask bit for too many retry attempts after collision error (half duplex only). | RW | 1
7 | rx_udp_ck_err_mask | Mask bit for RX packet UDP checksum error. | RW | 1
6 | rx_tcp_ck_err_mask | Mask bit for RX packet TCP checksum error. | RW | 1
5 | rx_ip_ck_err_mask | Mask bit for RX packet IP checksum error. | RW | 1
4 | rx_length_err_mask | Mask bit for RX packet with length field error. | RW | 1
3 | rx_symbol_err_mask | Mask bit for RX packet with symbol errors. | RW | 1
2 | rx_long_err_mask | Mask bit for RX packet too long. | RW | 1
1 | rx_short_err_mask | Mask bit for RX packet too short. | RW | 1
0 | rx_crc_err_mask | Mask bit for RX packet with bad CRC. | RW | 1

### gem_gxlmicrosemi : asf_protocol_fault_status

Address offset | 0x0E44
Description | Status register for protocol faults. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved_31_22 | Reserved, read as 0, ignored on write. | RO | 0x000
21 | rx_dma_pkt_flush_status | Status bit for RX packet was flushed from the DMA. | RW W1toClr | 0
20 | rx_overflow_status | Status bit for DMA buffer overflow and packet was dropped. | RW W1toClr | 0
19 | rx_hresp_err_status | Status bit for DMA hresp error (AHB only). | RW W1toClr | 0
18 | tx_hresp_err_status | Status bit for DMA hresp error (AHB only). | RW W1toClr | 0
17 | tx_buff_ex_mid_status | Status bit for Transmit buffers exhausted before end of packet. | RW W1toClr | 0
16 | tx_underrun_status | Status bit for Transmit DMA underrun occurred. | RW W1toClr | 0
15:9 | reserved_15_9 | Reserved, read as 0, ignored on write. | RO | 0x00
8 | tx_too_many_retries_status | Status bit for too many retry attempts after collision error (half duplex only). | RW W1toClr | 0
7 | rx_udp_ck_err_status | Status bit for RX packet UDP checksum error. | RW W1toClr | 0
6 | rx_tcp_ck_err_status | Status bit for RX packet TCP checksum error. | RW W1toClr | 0
5 | rx_ip_ck_err_status | Status bit for RX packet IP checksum error. | RW W1toClr | 0
4 | rx_length_err_status | Status bit for RX packet with length field error. | RW W1toClr | 0
3 | rx_symbol_err_status | Status bit for RX packet with symbol errors. | RW W1toClr | 0
2 | rx_long_err_status | Status bit for RX packet too long. | RW W1toClr | 0
1 | rx_short_err_status | Status bit for RX packet too short. | RW W1toClr | 0
0 | rx_crc_err_status | Status bit for RX packet with bad CRC. | RW W1toClr | 0

### gem_gxlmicrosemi : mmsl_control

Address offset | 0x0F00
Description | MMSL Control Register. This register contains the control bits for the 802.3br MAC Merge Sublayer (MMSL)
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7 | invert_mcrc | When set to 1 the generated mCRC will be inverted before transmission and the receive path will require the received mCRC to be inverted. Keep this bit 0 for normal operation. | RW | 0
6 | mmsl_debug_mode | This bit is used for test purposes only. When set, the verify_timer counter is sped up by a factor of 256. The main effect of this is that about 40 us are spent waiting for a response packet rather than 10 ms. | RW | 0
5 | route_rx_to_pmac | When set, the MMSL routes all received traffic to the pMAC rather than the eMAC when pre_active is 0 in the MMSL status register. | RW | 1
4 | restart_ver | Write a one to this bit to initiate the verification procedure. Writing a one to this bit has no effect if any of the following are true: pre_enable is zero, verify_disable is one or the verification procedure is already in progress. If pre-emption is active, route_rx_to_pmac should be set to zero before writing to the restart_ver bit otherwise express MAC frames will be sent to the pMAC and will be lost if they are interspersed between pMAC frame fragments. This bit always returns zero when read. | WO | 0
3 | pre_enable | This bit is for enabling/disabling the pre-emption operation. If set to zero pre-emption will not occur and verify mpackets will not be responded to or sent. If verify_disable is zero the verification process starts when this bit is written with one and pre-emption can occur once the verification process completes. If verify_disable is high pre-emption can occur as soon as this bit is set. If this bit is reset to zero from one and pre-emption is in progress, then pre-emption will complete and no more pre-emption will occur. | RW | 0
2 | verify_disable | This bit is for enabling/disabling the verification procedure that determine whether the link partner can support 802.3br. If disabled the link partner will not be verified and pre-emption is enabled as soon as pre_enable is set to one. Verify mpackets are responded to regardless of whether this bit is set. This bit is static and must be valid before pre_enable is set. | RW | 0
1:0 | add_frag_size | This bit field determines the minimum number of bytes which the pMAC sends before pre-emption is allowed. The vector is encoded as follows:, :, : 0: 64 bytes, : 1: 128 bytes, : 2: 192 bytes, : 3: 256 bytes, :, :These bits are static and must be valid before pre_enable is set. | RW | 0x0

### gem_gxlmicrosemi : mmsl_status

Address offset | 0x0F04
Description | MMSL Status Register. This register contains the MMSL status bits.
Type | RO

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | smd_error | This bit is set to 1 if an illegal SMD is received, that is if the SMD was not an Express, Verify, Response, Start Preemptible or Continuation Preemptible SMD. | RO RtoClr | 0
9 | frer_count_err | This bit is set to 1 if a frame count error occurs, that is if the SMD-C received indicates a different frame count than expected (i.e. the fragment belongs to another frame and not to the Start packet already received before this) or if a Fragment error happened, which means the field following the SMD-C received was encoding a different fragment count than it was supposed to be | RO RtoClr | 0
8 | smdc_error | This bit is set to 1 if an SMD-C is received when waiting for an SMD-S | RO RtoClr | 0
7 | smds_error | This is set to 1 if an SMD-S is received when waiting for an SMD-C | RO RtoClr | 0
6 | rcv_v_error | This bit is set to 1 if the verification m-packet received is incorrect | RO RtoClr | 0
5 | rcv_r_error | This bit is set to 1 if the response m-packet received is incorrect. If this occurs the verification process fails. | RO RtoClr | 0
4:2 | verify_status | These bits indicate the state of the verification state machine:, : 3'b000 - INIT_VERIFICATION, : 3'b001 - VERIFICATION_IDLE, : 3'b010 - SEND_VERIFY, : 3'b011 - WAIT_FOR_RESPONSE, : 3'b100 - VERIFIED, : 3'b101 - VERIFY_FAIL | RO | 0x0
1 | respond_status | This bit indicates the state of the respond state machine:, : 0 - R_IDLE, : 1 - SEND_RESPOND | RO | 0
0 | pre_active | This bit is set to one if pre-emption capability is active. It is set to one after the verification process completes, or if verify_disable is one when pre_enable is set to one. | RO | 0

### gem_gxlmicrosemi : mmsl_err_stats

Address offset | 0x0F08
Description | MMSL error statistics register. This register contains error counters for the MMSL. It is cleared on a read and does not roll if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | smd_err_count | A count of received MAC frames/MAC frame fragments rejected due to unknown SMD value or arriving with an SMD-C when no frame is in progress. | RO RtoClr | 0x00
15:8 | reserved_15_8 | Reserved, read as 0, ignored on write. | RO | 0x00
7:0 | ass_error_count | A count of MAC frames with reassembly errors. The counter is incremented by one every time the ASSEMBLY_ERROR state in the Receive Processing State Diagram is entered. | RO RtoClr | 0x00

### gem_gxlmicrosemi : mmsl_ass_ok_count

Address offset | 0x0F0C
Description | MMSL frames reassembled OK register. This register contains a count of MAC frames that were successfully reassembled and delivered to MAC. It is cleared on a read and does not roll if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | ass_ok_count | A count of MAC frames that were successfully reassembled and delivered to the MAC. | RO RtoClr | 0x0 0000

### gem_gxlmicrosemi : mmsl_frag_count_rx

Address offset | 0x0F10
Description | MMSL fragments received register. This register contains a count of the number of additional mPackets received due to preemption. It is cleared on a read and does not roll if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | frag_count_rx | A count of the number of additional mPackets received due to preemption. | RO RtoClr | 0x0 0000

### gem_gxlmicrosemi : mmsl_frag_count_tx

Address offset | 0x0F14
Description | MMSL fragments transmitted register. This register contains a count of the number of additional mPackets transmitted due to preemption. It is cleared on a read and does not roll if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | frag_count_tx | A count of the number of additional mPackets transmitted due to preemption. | RO RtoClr | 0x0 0000

### gem_gxlmicrosemi : mmsl_int_status

Address offset | 0x0F18
Description | MMSL Interrupt Status Register. This register indicates the source of an MMSL interrupt. The corresponding bit in the MMSL interrupt mask register must be clear for a bit to be set. If any bit is set in this register the ethernet_int signal will be asserted. For test purposes each bit can be set or reset by writing to the interrupt mask register. All interrupt status bits are reset to zero on read if the `gem_irq_read_clear define is set otherwise a one is written to the appropriate bit in order to clear it. In this mode reading has no effect on the status of the bit.
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved_31_6 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
5 | smd_err | Indicates an illegal SMD was received, that is the SMD was not an Express, Verify, Response, Start Pre-emptible or Continuation Pre-emptible SMD. | RW W1toClr | 0
4 | fr_count_err | Indicates a Frame Count error happened, that is the SMD-C received indicates a different frame count than expected (i.e. the fragment belongs to another frame and not to the Start packet already received before this) or if a Fragment error happened, which means the field following the SMD-C received was encoding a different fragment count than it was supposed to be | RW W1toClr | 0
3 | smdc_err | Indicates an SMD-C was received when waiting for an SMD-S | RW W1toClr | 0
2 | smds_err | Indicates an SMD-S was received when waiting for an SMD-C | RW W1toClr | 0
1 | rcv_v_err | Indicates an incorrect verification m-packet was received | RW W1toClr | 0
0 | rcv_r_err | Indicates an incorrect response m-packet was received. If this occurs the verification process fails. | RW W1toClr | 0

### gem_gxlmicrosemi : mmsl_int_enable

Address offset | 0x0F1C
Description | MMSL Interrupt Enable Register. At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved_31_6 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
5 | smd_error_int_en | Enable SMD error interrupt. | WO | 0
4 | fr_count_error_int_en | Enable frame count error interrupt. | WO | 0
3 | smdc_error_int_en | Enable SMD-C error interrupt. | WO | 0
2 | smds_error_int_en | Enable SMD-S error interrupt. | WO | 0
1 | rcv_v_error_int_en | Enable verify packet received error interrupt. | WO | 0
0 | rcv_r_error_int_en | Enable response packet received error interrupt. | WO | 0

### gem_gxlmicrosemi : mmsl_int_disable

Address offset | 0x0F20
Description | MMSL Interrupt Disable Register. Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved_31_6 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
5 | smd_error_int_dis | Disable SMD error interrupt. | WO | 0
4 | fr_count_error_int_dis | Disable frame count error interrupt. | WO | 0
3 | smdc_error_int_dis | Disable SMD-C error interrupt. | WO | 0
2 | smds_error_int_dis | Disable SMD-S error interrupt. | WO | 0
1 | rcv_v_error_int_dis | Disable verify packet received error interrupt. | WO | 0
0 | rcv_r_error_int_dis | Disable response packet received error interrupt. | WO | 0

### gem_gxlmicrosemi : mmsl_int_mask

Address offset | 0x0F24
Description | MMSL Interrupt Mask Register. The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.
Type | RO

Bits | Field Name | Description | Type | Reset
31:6 | reserved_31_6 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
5 | smd_error_mask | Mask bit for SMD error interrupt. | RO | 1
4 | fr_count_error_mask | Mask bit for frame count error interrupt. | RO | 1
3 | smdc_error_mask | Mask bit for SMD-C error interrupt. | RO | 1
2 | smds_error_mask | Mask bit for SMD-S error interrupt. | RO | 1
1 | rcv_v_error_mask | Mask bit for verify packet received error interrupt. | RO | 1
0 | rcv_r_error_mask | Mask bit for response packet received error interrupt. | RO | 1

### gem_gxlmicrosemi : emac_network_control

Address offset | 0x1000
Description | The network control register contains general MAC control functions for both receiver and transmitter.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved_31 | Reserved, read as 0, ignored on write. | RO | 0
30 | ifg_eats_qav_credit | Setting this bit high modifies the CBS algorithm so the IFG/IPG associated with a transmit frame counts towards its 802.1Qav credit. | RW | 0
29 | two_pt_five_gig | 2.5G operation selected - setting this bit high drives the speed_mode[3] top level output pin high and also adjusts the link timer in the PCS auto-negotiation block to ensure it delivers 10ms for 2500BASE-X and 1.6ms in SGMII mode, and also ensures int_moderation counts 800ns periods with the speeded up MAC clocks. | RW | 0
28 | sel_mii_on_rgmii | If the RGMII interface being used set this bit high to configure the interface for MII operation (in 802.3br configurations this bit has no effect for the eMAC). | RW | 0
27 | oss_correction_field | 1588 One Step Correction Field Update. Set this bit high to enable updating the correction field of PTP 1588 version 2 sync frames by adding current TSU timer value. | RW | 0
26 | ext_rxq_sel_en | Enable external selection of receive queue. When this bit is high the ext_match1, ext_match2, ext_match3 and ext_match4 inputs will determine which receive queue a frame is routed to. This will be the case regardless of the state of the external address match enable bit 9 of the network config register. Note that receive frames will be dropped unless they are matched by the internal frame filtering functionality. If the external address match enable bit 9 in the network config register is set frames may be matched by an external address match filter as long as one of the ext_match1, ext_match2, ext_match3 and ext_match4 inputs is asserted early enough. When set ext_rxq_sel_en takes precedence over the existing screener functionality. This bit is only relevant if priority queuing is configured. | RW | 0
25 | pfc_ctrl | Enable multiple PFC pause quantums, one per pause priority. | RW | 0
24 | one_step_sync_mode | 1588 One Step Sync Mode. Write 1 to enable. Replace timestamp field in the 1588 header for TX Sync Frames with current TSU timer value. | RW | 0
23 | ext_tsu_port_enable | External TSU timer port enable (1 = enable) - for the eMAC this should be enabled. | RW | 0
22 | store_udp_offset | Store UDP / TCP offset to memory. Setting this bit to one will cause the upper 16-bits of the CRC of every received frame to be replaced with the offset from start of frame to the beginning of the UDP or TCP header. The lower 16-bits of the CRC are replaced with zero and reserved for future use. The offset is measured in units of 2 bytes. Set to zero for normal operation. | RW | 0
21 | alt_sgmii_mode | Alternative sgmii mode. If asserted with sgmii_mode in the network control register the ACK bit is driven before ability detect during transfer of status information from the PHY to the MAC. | RW | 0
20 | ptp_unicast_ena | Enable detection of unicast PTP unicast frames. | RW | 0
19 | tx_lpi_en | LPI is supported by the pMAC not the eMAC. Do not set this bit in the eMAC. | RW | 0
18 | flush_rx_pkt_pclk | Flush the next packet from the external RX DPRAM. This bit flushes the frame that is the next in line to be pushed out to the AXI interface. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory. | WO | 0
17 | transmit_pfc_priority_based_pause_frame | Write a one to transmit PFC priority based pause frame. Takes the values stored in the Transmit PFC Pause Register. | WO | 0
16 | pfc_enable | Enable PFC Priority Based Pause Reception capabilities. Setting this bit will enable PFC negotiation and recognition of priority based pause frames. | RW | 0
15 | store_rx_ts | Store receive time stamp to memory. Setting this bit to one will cause the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time stamp point (for releases prior to 1p10 bits 31 and 30 of the value written to the CRC field were hardwired to zero, from release 1p10 onwards these bits represent the two least significant seconds bit of the captured timer value). Set to zero for normal operation. | RW | 0
14:13 | reserved_14_13 | Reserved, read as 0, ignored on write. | RO | 0x0
12 | tx_pause_frame_zero | Transmit zero quantum pause frame - writing one to this bit causes a pause frame with zero quantum to be transmitted. | WO | 0
11 | tx_pause_frame_req | Transmit pause frame - writing one to this bit causes a pause frame to be transmitted. | WO | 0
10 | transmit_halt | Transmit halt - writing one to this bit resets the tx_go variable and halts the dma from reading more transmit frames into the transmit SRAM buffer. Any frames already read into the transmit SRAM will still be transmitted. | WO | 0
9 | transmit_start | Start transmission - writing one to this bit starts transmission. | WO | 0
8 | back_pressure | Back pressure if set in 10M or 100M half-duplex mode will force collisions on all received frames. Ignored in gigabit half-duplex mode. | RW | 0
7 | stats_write_en | Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes. | RW | 0
6 | inc_all_stats_regs | Incremental statistics registers - this bit is write only. Writing a one increments all the statistics registers by one for test purposes. | WO | 0
5 | clear_all_stats_regs | Clear statistics registers - this bit is write only. Writing a one clears the statistics registers. | WO | 0
4 | man_port_en | Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low. | RW | 0
3 | enable_transmit | Transmit enable - when set, it enables the GEM transmitter to send data. When reset transmission will stop immediately, the transmit pipeline and control registers will be cleared and the transmit queue pointer register will reset to point to the start of the transmit descriptor list. This bit needs to be set before bit 9 the start transmission bit. (Setting this bit low resets the transmit queue pointer however reading the transmit queue pointer register through the APB interface may still return an old value until transmission is restarted.) | RW | 0
2 | enable_receive | Receive enable - when set, it enables the GEM to receive data. When reset frame reception will stop immediately and the receive pipeline will be cleared. The receive queue pointer register is unaffected. | RW | 0
1 | loopback_local | Loopback local - asserts the loopback_local signal to the system clock generator. Also connects txd to rxd, tx_en to rx_dv and forces full duplex mode. If the GEM configuration contains the PCS then bit 11 of the network configuration register must be set low to disable TBI mode when in internal loopback. rx_clk and tx_clk may malfunction as the GEM is switched into and out of internal loopback. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loopback. Local loopback functionality is optional and may not be supported by some instantiations of the GEM. | RW | 0
0 | loopback | Loopback - controls the loopback output pin. | RW | 0

### gem_gxlmicrosemi : emac_network_config

Address offset | 0x1004
Description | The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | uni_direction_enable | Uni-direction-enable. When low the PCS will transmit idle symbols if the link goes down. When high the PCS can transmit frame data when the link is down. | RW | 0
30 | ignore_ipg_rx_er | Ignore IPG rx_er. When set rx_er has no effect on the GEMs operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode. | RW | 0
29 | nsp_accept | Receive bad preamble. When set frames with non-standard preamble are not rejected (the first byte of preamble needs to be 55 and the last D5, bytes other than 55 or D5 may be inserted in between). | RW | 0
28 | ipg_stretch_enable | IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register. | RW | 0
27 | sgmii_mode_enable | SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms. | RW | 0
26 | ignore_rx_fcs | Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be set to zero. | RW | 0
25 | en_half_duplex_rx | Enable frames to be received in half-duplex mode while transmitting. | RW | 0
24 | receive_checksum_offload_enable | Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded. | RW | 0
23 | disable_copy_of_pause_frames | Disable copy of pause frames - set to one to prevent pause frames being copied to memory. When set, neither control frames with type id 8808, nor pause frames with destination address 010000c28001 are copied to memory, this functionality was enhanced in release 1p09. Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required. | RW | 0
22:21 | data_bus_width | Data bus width - set according to AMBA (AHB/AXI) or external FIFO data bus width. The reset value for this can be changed by defining a new value for gem_dma_bus_width_def in gem_defs. Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits., :00: 32 bit data bus width, :01: 64 bit AMBA (AHB/AXI) data bus width, :10: 128 bit AMBA (AHB/AXI) data bus width, :11: invalid, :Note. The reset value of this field is equal to the gem_dma_bus_width_def define, which is user configurable. | RW | 0x1
20:18 | mdc_clock_division | MDC clock division - set according to pclk speed. These three bits determine the number pclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). The reset value for this can be changed by defining a new value for gem_mdc_clock_div in gem_defs.v, :000: divide pclk by 8 (pclk up to 20 MHz), :001: divide pclk by 16 (pclk up to 40 MHz), :010: divide pclk by 32 (pclk up to 80 MHz), :011: divide pclk by 48 (pclk up to 120MHz), :100: divide pclk by 64 (pclk up to 160 MHz), :101: divide pclk by 96 (pclk up to 240 MHz), :110: divide pclk by 128 (pclk up to 320 MHz), :111: divide pclk by 224 (pclk up to 540 MHz)., :Note. The reset value of this field is equal to the gem_mdc_clock_div define, which is user configurable. | RW | 0x2
17 | fcs_remove | FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode. | RW | 0
16 | length_field_error_frame_discard | Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600. | RW | 0
15:14 | receive_buffer_offset | Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer. Note that when the define gem_pbuf_rsc has been set then these bits cannot be used. | RW | 0x0
13 | pause_enable | Pause enable - when set, transmission will pause if a non-zero 802.3 classic pause frame is received and PFC has not been negotiated. | RW | 0
12 | retry_test | Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every rx_clk cycle. | RW | 0
11 | pcs_select | PCS select - selects between MII/GMII and TBI. Must be set for SGMII operation., :0: GMII/MII interface enabled, TBI disabled, :1: TBI enabled, GMII/MII disabled, :(in 802.3br configurations this bit must be set identically in the eMAC and pMAC) | RW | 0
10 | gigabit_mode_enable | Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation., :0: 10/100 operation using MII or TBI interface, :1: Gigabit operation using GMII or TBI interface, :(in 802.3br configurations this bit must be set identically in the eMAC and pMAC) | RW | 0
9 | external_address_match_enable | External address match enable - when set the external address match interface can be used to copy frames to memory. | RW | 0
8 | receive_1536_byte_frames | Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes. | RW | 0
7 | unicast_hash_enable | Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register. | RW | 0
6 | multicast_hash_enable | Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register. | RW | 0
5 | no_broadcast | No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted. | RW | 0
4 | copy_all_frames | Copy all frames - when set to logic one, all valid frames will be accepted. | RW | 0
3 | jumbo_frames | Jumbo frames - set to one to enable jumbo frames up to `gem_jumbo_max_length bytes to be accepted. The default length is 10,240 bytes. | RW | 0
2 | discard_non_vlan_frames | Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic. | RW | 0
1 | full_duplex | Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin. | RW | 0
0 | speed | Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps. The value of this pin is reflected on the speed_mode[0] output pin (in 802.3br configurations this bit has no effect for the eMAC). | RW | 0

### gem_gxlmicrosemi : emac_network_status

Address offset | 0x1008
Description | The network status register returns status information with respect to the PHY management MDIO interface, the PCS, priority flow control, LPI and other status.
Type | RO

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10:9 | link_fault_indication | For 2.5GBASE-X operation these two bits return the state of link_fault in the LFSM defined in Figure 46-11 of IEEE 802.3:, : 00 - OK, : 01 - local fault, : 10 - remote fault, : 11 - link interruption, :If the link fault state machine is not enabled (by setting the 2.5G, AN enable, uni directional enable and tbi control bits) these two bits are set to zero. | RO | 0x0
8 | axi_xaction_outstanding | Outstanding AXI Transactions - This status bit is set when one or more AXI read or write transactions have been issued by the DUT but the responses have not yet been fully collected. | RO | 0
7 | lpi_indicate_pclk | LPI Indication - Low power idle has been detected on receive. This bit is set when LPI is detected and reset when normal idle is detected. An interrupt is generated when the state of this bit changes. | RO | 0
6 | pfc_negotiate_pclk | Set when PFC Priority Based Pause has been negotiated. | RO | 0
5 | mac_pause_tx_en | PCS auto-negotiation pause transmit resolution. | RO | 0
4 | mac_pause_rx_en | PCS auto-negotiation pause receive resolution. | RO | 0
3 | mac_full_duplex | PCS auto-negotiation duplex resolution. Set to one if the resolution function determines that both devices are capable of full duplex operation. If zero half-duplex operation is possible as long as bit 0 (PCS link state) is also one. | RO | 0
2 | man_done | The PHY management logic is idle (i.e. has completed). | RO | 1
1 | mdio_in | Returns status of the mdio_in pin. | RO | 0
0 | pcs_link_state | Returns status of PCS link state. If auto-negotiation is disabled this returns the synchronisation status. If auto-negotiation is enabled it is set in the LINK_OK state as long as a compatible duplex mode is resolved, it is always set in the LINK_OK state in SGMII mode. | RO | 0

### gem_gxlmicrosemi : emac_dma_config

Address offset | 0x1010
Description | DMA Configuration Register
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved_31 | Reserved, read as 0, ignored on write. | RO | 0
30 | dma_addr_bus_width_1 | DMA address bus width. 0 = 32b, 1 = 64b. | RW | 0
29 | tx_bd_extended_mode_en | Enable TX extended BD mode. See TX BD control register definition for description of feature. | RW | 0
28 | rx_bd_extended_mode_en | Enable RX extended BD mode. See RX BD control register definition for description of feature. | RW | 0
27 | reserved_27 | Reserved, read as 0, ignored on write. | RO | 0
26 | force_max_amba_burst_tx | Force max length bursts on TX. Force the TX DMA to always issue max length bursts on EOP (end of packet) or EOB (end of buffer) transfers as defined by bits 4:0 of this register, even when there is less than max burst data bytes to read. Residual data read is ignored. AHB only - does not apply on AXI bursts (prior to release 1p10) or bursts that break 1k boundary rule - supported on AXI from release 1p10. | RW | 0
25 | force_max_amba_burst_rx | Force max length bursts on RX. Force the RX DMA to always issue max length bursts on EOP (end of packet) or EOB (end of buffer) transfers, even if there is less than max burst real packet data required to write. Any extra bytes of pad data is set to 0x00. AHB only - does not apply on AXI bursts (prior to release 1p10) or bursts that break 1k boundary rule - supported on AXI from release 1p10. | RW | 0
24 | force_discard_on_err | Auto Discard RX frames during lack of resource. When set, the GEM DMA will automatically discard the next frame (that is the oldest frame) from the receiver packet buffer memory when a receive buffer descriptor is read with its used bit set. When low, then received frames will remain to be stored in the SRAM based packet buffer until AMBA (AHB/AXI) buffer resource next becomes available. In this case if the SRAM memory fills up then there will be a receive overflow condition and the most recently received frame (that is the newest) will be discarded. A write to this bit is ignored if the DMA is not configured in the packet buffer full store and forward mode. | RW | 0
23:16 | rx_buf_size | DMA receive buffer size in external AMBA (AHB/AXI) system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes., :0x01 corresponds to buffers of 64 bytes, :0x02 corresponds to 128 bytes etc., :For example:, :0x02: 128 byte., :0x18: 1536 byte (1*max length frame/buffer), :0xA0: 10240 byte (1*10K jumbo frame/buffer), :0xFF: 16320 byte , :Note that this value should never be written as zero., :Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. | RW | 0x02
15:14 | reserved_15_14 | Reserved, read as 0, ignored on write. | RO | 0x0
13 | crc_error_report | When the bit is set, bit 16 of the receive buffer descriptor will represent FCS/CRC error (only if frames with FCS are copied to memory as enabled by bit 26 in the network config register). When this bit is clear, bit 16 of the receive buffer descriptor will represent the Canonical format indicator (CFI) bit as extracted from the receive frame (if the receive buffer descriptor is pointing to the last data buffer of the receive frame and the received frame was VLAN tagged). | RW | 0
12 | infinite_last_dbuf_size_en | Forces the receive DMA to consider the data buffer pointed to by last descriptor in the descriptor list to be of elastic size (the last descriptor is the one with its wrap bit set). This means the first buffer pointed to in the list will always contain the beginning of a frame (this helps if there is a desire to build custom logic that interfaces with the receive buffer directly without software intervention). When set the rx_buf_size bits 23:16 in the dma configuration register are ignored for the last receive buffer in the descriptor list and data will be written into the buffer sequentially until the frame is completely received and the buffer descriptor status will be updated with the frame length as normal. | RW | 0
11 | tx_pbuf_tcp_en | Transmitter IP, TCP and UDP checksum generation offload enable (not supported when in TX Partial Store and Forward mode). When set, the transmitter checksum generation engine is enabled, to calculate and substitute checksums for transmit frames. When clear, frame data is unaffected. If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as 0, ignored on write. | RW | 0
10 | tx_pbuf_size | Transmitter packet buffer memory size select. Having this bit at zero halves the amount of memory used for the transmit packet buffer. This reduces the amount of memory used by the GEM. It is important to set this bit to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 4 Kbytes., :1: Use full configured addressable space (4 Kb), :0: Do not use top address bit (2 Kb), :If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as 0, ignored on write., :Note. The reset value of this field is equal to the gem_tx_pbuf_size_def define, which is user configurable. | RW | 1
9:8 | rx_pbuf_size | Receiver packet buffer memory size select. Having these bits at less than 11 reduces the amount of memory used for the receive packet buffer. This reduces the amount of memory used by the GEM. It is important to set these bits both to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 8 Kbytes., :11: Use full configured addressable space (8 Kb), :10: Do not use top address bit (4 Kb), :01: Do not use top two address bits (2 Kb), :00: Do not use top three address bits (1 Kb), :If the GEM is not configured to use the DMA packet buffer, these bits are not implemented and will be treated as reserved, read as 0, ignored on write., :Note. The reset value of this field is equal to the gem_rx_pbuf_size_def define, which is user configurable. | RW | 0x3
7 | endian_swap_packet | endian swap mode enable for packet data accesses. When set, selects swapped endianism for AMBA (AHB/AXI) transfers. When clear, selects little endian mode. | RW | 0
6 | endian_swap_management | endian swap mode enable for management descriptor accesses. When set, selects swapped endianism for AMBA (AHB/AXI) transfers. When clear, selects little endian mode. | RW | 0
5 | hdr_data_splitting_en | Enable header data Splitting. When set, receive frames will be forwarded to main memory using a minimum of two DMA data buffers. The first X data buffers will contain the frame header, consisting of the Ethernet,VLAN,(IPv4 or IPv6),(TCP or UDP). X= (frame header size divided by rx_buf_size as defined in bits 23:16 of this register). The last Y data buffers will contain the frame payload. Y= (frame payload size divided by rx_buf_size). Note that for non VLAN/IP/TCP/UDP frames, the header will always be 14 bytes. When this feature is disabled, the frame is forwarded to main memory in blocks of rx_buf_size. | RW | 0
4:0 | amba_burst_length | Selects the burst length to use on the AMBA (AHB/AXI) when transferring frame data. Not used for DMA management operations and only used where space and data size allow and respecting AXI/AHB burst boundary rules. One-hot priority encoding enforced automatically on register writes as follows, where x represents don't care:, :1xxxx: Attempt to use bursts of up to 16., :01xxx: Attempt to use bursts of up to 8., :001xx: Attempt to use bursts of up to 4., :0001x: Always use SINGLE bursts., :00001: Always use SINGLE bursts., :00000: Attempt to use bursts of up to 256. | RW | 0x04

### gem_gxlmicrosemi : emac_transmit_status

Address offset | 0x1014
Description | This register, when read, provides details of the status of the transmit path. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | tx_dma_lockup_detected | TX DMA lockup detected - set when lockup has been detected the transmit DMA lockup monitor. | RW W1toClr | 0
9 | tx_mac_lockup_detected | TX MAC lockup detected - set when lockup has been detected by the lockup monitor on the MAC transmit path. | RW W1toClr | 0
8 | resp_not_ok | bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit. | RW W1toClr | 0
7 | late_collision_occurred | Late collision occurred - only set if the condition occurs in gigabit mode, as retry is not attempted. Cleared by writing a one to this bit. | RW W1toClr | 0
6 | transmit_under_run | Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable. This bit is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for internal FIFO mode, this bit is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because a used bit was read. When using the DMA interface configured for packet buffer mode, this bit will never be set. When using the external FIFO interface, this bit is also set when the tx_r_underflow input is asserted during a frame transfer. Cleared by writing a 1. | RW W1toClr | 0
5 | transmit_complete | Transmit complete - set when a frame has been transmitted. Cleared by writing a one to this bit. | RW W1toClr | 0
4 | amba_error | Transmit frame corruption due to AMBA (AHB/AXI) errors. Set if an error occurs whilst midway through reading transmit frame from external memory including HRESP(AHB), RRESP or BRESP(AXI) errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Cleared by writing a one to this bit. | RW W1toClr | 0
3 | transmit_go | Transmit go - if high transmit is active. When using the exposed FIFO interface, this bit represents bit 3 of the network control register. When using the DMA interface this bit represents the tx_go variable as specified in the transmit buffer description. | RO | 0
2 | retry_limit_exceeded | Retry limit exceeded - cleared by writing a one to this bit. | RW W1toClr | 0
1 | collision_occurred | Collision occurred - set by the assertion of collision. Cleared by writing a one to this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. In gigabit mode, this status is not set for a late collision. | RW W1toClr | 0
0 | used_bit_read | Used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit. | RW W1toClr | 0

### gem_gxlmicrosemi : emac_receive_q_ptr

Address offset | 0x1018
Description | This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AHB/AXI) operation, the receive descriptors are read from memory using a single 32bit AHB/AXI access. When the datapath is configured at 64bit or 128bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AHB/AXI access. For 32bit datapaths, the receive descriptors should be aligned at 32-bit boundaries and are written to using two individual non sequential 32-bit accesses.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | dma_rx_q_ptr | Receive buffer queue base address - written with the address of the start of the receive queue. | RW | 0x0000 0000
1 | reserved_1 | Reserved, read as 0, ignored on write. | RO | 0
0 | dma_rx_dis_q | Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled. | RW | 0

### gem_gxlmicrosemi : emac_transmit_q_ptr

Address offset | 0x101C
Description | This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual 32-bit non sequential accesses.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | dma_tx_q_ptr | Transmit buffer queue base address - written with the address of the start of the transmit queue. | RW | 0x0000 0000
1 | reserved_1 | Reserved, read as 0, ignored on write. | RO | 0
0 | dma_tx_dis_q | Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. | RW | 0

### gem_gxlmicrosemi : emac_receive_status

Address offset | 0x1020
Description | This register, when read provides details of the status of the receive path. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved_31_6 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
5 | rx_dma_lockup_detected | RX DMA lockup detected - set when lockup has been detected the receive DMA lockup monitor. | RW W1toClr | 0
4 | rx_mac_lockup_detected | RX MAC lockup detected - set when lockup has been detected by the lockup monitor on the MAC receive path. | RW W1toClr | 0
3 | resp_not_ok | bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit. | RW W1toClr | 0
2 | receive_overrun | Receive overrun - this bit is set if either the gem_dma RX FIFO or external RX FIFO were unable to store the receive frame due to a FIFO overflow, or if the receive status, reported by the gem_rx module to the gem_dma was not taken at end of frame. This bit is also set in DMA packet buffer mode if the packet buffer overflows. For DMA operation the buffer will be recovered if an overrun occurs. This bit is cleared by writing a one to it. | RW W1toClr | 0
1 | frame_received | Frame received - one or more frames have been received and placed in memory. Cleared by writing a one to this bit. | RW W1toClr | 0
0 | buffer_not_available | Buffer not available - an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time an end of frame is received until a valid pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the meantime cleared the status flag. Cleared by writing a one to this bit. | RW W1toClr | 0

### gem_gxlmicrosemi : emac_int_status

Address offset | 0x1024
Description | If not configured for priority queuing, the GEM generates a single interrupt. This register indicates the source of this interrupt. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the ethernet_int signal will be asserted. For test purposes each bit can be set or reset by writing to the interrupt mask register. The default configuration is shown below whereby all bits are reset to zero on read. Changing the validity of the `gem_irq_read_clear define will instead require a one to be written to the appropriate bit in order to clear it. In this mode reading has no effect on the status of the bit.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | tx_lockup_detected | TX lockup detection - set when lockup has been detected by any of the lockup monitors on the transmit datapath. | RW W1toClr | 0
30 | rx_lockup_detected | RX lockup detection - set when lockup has been detected by any of the lockup monitors on the receive datapath. | RW W1toClr | 0
29 | tsu_timer_comparison_interrupt | TSU timer comparison interrupt. Indicates when TSU timer count value is equal to programmed value. | RW W1toClr | 0
28 | wol_interrupt | WOL interrupt. Indicates a WOL event has been received. | RW W1toClr | 0
27 | receive_lpi_indication_status_bit_change | Receive LPI indication status bit change | RW W1toClr | 0
26 | tsu_seconds_register_increment | TSU seconds register increment indicates the register has incremented. Cleared on read. | RW W1toClr | 0
25 | ptp_pdelay_resp_frame_transmitted | PTP pdelay_resp frame transmitted indicates a PTP pdelay_resp frame has been transmitted. Cleared on read. | RW W1toClr | 0
24 | ptp_pdelay_req_frame_transmitted | PTP pdelay_req frame transmitted indicates a PTP pdelay_req frame has been transmitted. Cleared on read. | RW W1toClr | 0
23 | ptp_pdelay_resp_frame_received | PTP pdelay_resp frame received indicates a PTP pdelay_resp frame has been received. Cleared on read. | RW W1toClr | 0
22 | ptp_pdelay_req_frame_received | PTP pdelay_req frame received indicates a PTP pdelay_req frame has been received. Cleared on read. | RW W1toClr | 0
21 | ptp_sync_frame_transmitted | PTP sync frame transmitted indicates a PTP sync frame has been transmitted. Cleared on read. | RW W1toClr | 0
20 | ptp_delay_req_frame_transmitted | PTP delay_req frame transmitted indicates a PTP delay_req frame has been transmitted. Cleared on read. | RW W1toClr | 0
19 | ptp_sync_frame_received | PTP sync frame received indicates a PTP sync frame has been received. Cleared on read. | RW W1toClr | 0
18 | ptp_delay_req_frame_received | PTP delay_req frame received indicates a PTP delay_req frame has been received. Cleared on read. | RW W1toClr | 0
17 | pcs_link_partner_page_received | PCS link partner page received - set when a new base page or next page is received from the link partner. The first time this interrupt is received, it will indicate base page received and subsequent reads will indicate next pages. The next page and base page registers should only be read when this interrupt is signalled. For next pages, the link partner next page register should be read first to avoid the register being over written. This interrupt also indicates when the host should write a new page into the next page register. If further next page exchange is only required by the link partner, this register should be written with a null message page (0x2001). Cleared on read. | RW W1toClr | 0
16 | pcs_auto_negotiation_complete | PCS auto-negotiation complete - set once the internal PCS layer has completed auto-negotiation. Cleared on read. | RW W1toClr | 0
15 | external_interrupt | External interrupt - set when a rising edge has been detected on the ext_interrupt_in input pin. Cleared on read. | RW W1toClr | 0
14 | pause_frame_transmitted | Pause frame transmitted - indicates a pause frame has been successfully transmitted after being initiated from the network control register or from the tx_pause control pin. Cleared on read. | RW W1toClr | 0
13 | pause_time_elapsed | Pause Time elapsed - set when either the pause time register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field. Not set for PFC pause frames. Cleared on read. | RW W1toClr | 0
12 | pause_frame_with_non_zero_pause_quantum_received | Pause frame with non-zero pause quantum received - indicates a valid legacy pause frame with a non-zero pause quantum field has been received or any valid PFC pause frame has been received. Cleared on read. | RW W1toClr | 0
11 | resp_not_ok | bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared on read. | RW W1toClr | 0
10 | receive_overrun | Receive overrun - set when the receive overrun status bit gets set. Cleared on read. | RW W1toClr | 0
9 | link_change | Link change - set when the PCS link status changes. If auto-negotiation is enabled then link status goes high when it completes. If AN is disabled link status goes high when synchronization is achieved. If 802.3cb link fault signalling is enabled a link change interrupt is triggered when the link fault indication as reported in the network status register changes. Cleared on read. | RW W1toClr | 0
8 | reserved_8 | Reserved, read as 0, ignored on write. | RO | 0
7 | transmit_complete | Transmit complete - set when a frame has been transmitted. Cleared on read. | RW W1toClr | 0
6 | amba_error | Transmit frame corruption due to AMBA (AHB/AXI) error. Set if an error occurs whilst midway through reading transmit frame from external system memory, including HRESP errors(AHB), RRESP or BRESP(AXI) errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Cleared on a read. | RW W1toClr | 0
5 | retry_limit_exceeded_or_late_collision | Retry limit exceeded or late collision - transmit error. Late collision will only cause this status bit to be set in gigabit mode (as a retry is not attempted). Cleared on read. | RW W1toClr | 0
4 | transmit_under_run | Transmit under run - this interrupt is set if the transmitter was forced to terminate a frame that it has already began transmitting due to further data being unavailable. If an under run occurs, the transmitter will force bad crc and tx_er high. This interrupt is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for internal FIFO mode, this interrupt is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB/AXI error response was returned by the connected slave, or because a used bit was read. When using the DMA interface configured for packet buffer mode, this bit will never be set. When using the external FIFO interface, this interrupt is also set when the tx_r_underflow input was asserted during a frame transfer. Cleared on read. | RW W1toClr | 0
3 | tx_used_bit_read | TX used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared on read. | RW W1toClr | 0
2 | rx_used_bit_read | RX used bit read - set when a receive buffer descriptor is read with its used bit set. Cleared on read. | RW W1toClr | 0
1 | receive_complete | Receive complete - a frame has been stored in memory. Cleared on read. | RW W1toClr | 0
0 | management_frame_sent | Management frame sent - the PHY management register has completed its operation. Cleared on read. | RW W1toClr | 0

### gem_gxlmicrosemi : emac_int_enable

Address offset | 0x1028
Description | At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | enable_tx_lockup_detected_interrupt | Enable TX lockup detection interrupt. | WO | 0
30 | enable_rx_lockup_detected_interrupt | Enable RX lockup detection interrupt. | WO | 0
29 | enable_tsu_timer_comparison_interrupt | Enable TSU timer comparison interrupt. | WO | 0
28 | enable_wol_event_received_interrupt | Enable WOL event received interrupt | WO | 0
27 | enable_rx_lpi_indication_interrupt | Enable RX LPI indication interrupt | WO | 0
26 | enable_tsu_seconds_register_increment | Enable TSU seconds register increment | WO | 0
25 | enable_ptp_pdelay_resp_frame_transmitted | Enable PTP pdelay_resp frame transmitted | WO | 0
24 | enable_ptp_pdelay_req_frame_transmitted | Enable PTP pdelay_req frame transmitted | WO | 0
23 | enable_ptp_pdelay_resp_frame_received | Enable PTP pdelay_resp frame received | WO | 0
22 | enable_ptp_pdelay_req_frame_received | Enable PTP pdelay_req frame received | WO | 0
21 | enable_ptp_sync_frame_transmitted | Enable PTP sync frame transmitted | WO | 0
20 | enable_ptp_delay_req_frame_transmitted | Enable PTP delay_req frame transmitted | WO | 0
19 | enable_ptp_sync_frame_received | Enable PTP sync frame received | WO | 0
18 | enable_ptp_delay_req_frame_received | Enable PTP delay_req frame received | WO | 0
17 | enable_pcs_link_partner_page_received | Enable PCS link partner page received | WO | 0
16 | enable_pcs_auto_negotiation_complete_interrupt | Enable PCS auto-negotiation complete interrupt | WO | 0
15 | enable_external_interrupt | Enable external interrupt | WO | 0
14 | enable_pause_frame_transmitted_interrupt | Enable pause frame transmitted interrupt | WO | 0
13 | enable_pause_time_zero_interrupt | Enable pause time zero interrupt | WO | 0
12 | enable_pause_frame_with_non_zero_pause_quantum_interrupt | Enable pause frame with non-zero pause quantum interrupt | WO | 0
11 | enable_resp_not_ok_interrupt | Enable bresp/hresp not OK interrupt | WO | 0
10 | enable_receive_overrun_interrupt | Enable receive overrun interrupt | WO | 0
9 | enable_link_change_interrupt | Enable link change interrupt | WO | 0
8 | reserved_8 | Reserved, read as 0, ignored on write. | RO | 0
7 | enable_transmit_complete_interrupt | Enable transmit complete interrupt | WO | 0
6 | enable_transmit_frame_corruption_due_to_amba_error_interrupt | Enable transmit frame corruption due to AMBA (AHB/AXI) error interrupt | WO | 0
5 | enable_retry_limit_exceeded_or_late_collision_interrupt | Enable retry limit exceeded or late collision interrupt | WO | 0
4 | enable_transmit_buffer_under_run_interrupt | Enable transmit buffer under run interrupt | WO | 0
3 | enable_transmit_used_bit_read_interrupt | Enable transmit used bit read interrupt | WO | 0
2 | enable_receive_used_bit_read_interrupt | Enable receive used bit read interrupt | WO | 0
1 | enable_receive_complete_interrupt | Enable receive complete interrupt | WO | 0
0 | enable_management_done_interrupt | Enable management done interrupt | WO | 0

### gem_gxlmicrosemi : emac_int_disable

Address offset | 0x102C
Description | Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | disable_tx_lockup_detected_interrupt | Disable TX lockup detection interrupt. | WO | 0
30 | disable_rx_lockup_detected_interrupt | Disable RX lockup detection interrupt. | WO | 0
29 | disable_tsu_timer_comparison_interrupt | Disable TSU timer comparison interrupt. | WO | 0
28 | disable_wol_event_received_interrupt | Disable WOL event received interrupt | WO | 0
27 | disable_rx_lpi_indication_interrupt | Disable RX LPI indication interrupt | WO | 0
26 | disable_tsu_seconds_register_increment | Disable TSU seconds register increment | WO | 0
25 | disable_ptp_pdelay_resp_frame_transmitted | Disable PTP pdelay_resp frame transmitted | WO | 0
24 | disable_ptp_pdelay_req_frame_transmitted | Disable PTP pdelay_req frame transmitted | WO | 0
23 | disable_ptp_pdelay_resp_frame_received | Disable PTP pdelay_resp frame received | WO | 0
22 | disable_ptp_pdelay_req_frame_received | Disable PTP pdelay_req frame received | WO | 0
21 | disable_ptp_sync_frame_transmitted | Disable PTP sync frame transmitted | WO | 0
20 | disable_ptp_delay_req_frame_transmitted | Disable PTP delay_req frame transmitted | WO | 0
19 | disable_ptp_sync_frame_received | Disable PTP sync frame received | WO | 0
18 | disable_ptp_delay_req_frame_received | Disable PTP delay_req frame received | WO | 0
17 | disable_pcs_link_partner_page_received | Disable PCS link partner page received | WO | 0
16 | disable_pcs_auto_negotiation_complete_interrupt | Disable PCS auto-negotiation complete interrupt | WO | 0
15 | disable_external_interrupt | Disable external interrupt | WO | 0
14 | disable_pause_frame_transmitted_interrupt | Disable pause frame transmitted interrupt | WO | 0
13 | disable_pause_time_zero_interrupt | Disable pause time zero interrupt | WO | 0
12 | disable_pause_frame_with_non_zero_pause_quantum_interrupt | Disable pause frame with non-zero pause quantum interrupt | WO | 0
11 | disable_resp_not_ok_interrupt | Disable bresp/hresp not OK interrupt | WO | 0
10 | disable_receive_overrun_interrupt | Disable receive overrun interrupt | WO | 0
9 | disable_link_change_interrupt | Disable link change interrupt | WO | 0
8 | reserved_8 | Reserved, read as 0, ignored on write. | RO | 0
7 | disable_transmit_complete_interrupt | Disable transmit complete interrupt | WO | 0
6 | disable_transmit_frame_corruption_due_to_amba_error_interrupt | Disable transmit frame corruption due to AMBA (AHB/AXI) error interrupt | WO | 0
5 | disable_retry_limit_exceeded_or_late_collision_interrupt | Disable retry limit exceeded or late collision interrupt | WO | 0
4 | disable_transmit_buffer_under_run_interrupt | Disable transmit buffer under run interrupt | WO | 0
3 | disable_transmit_used_bit_read_interrupt | Disable transmit used bit read interrupt | WO | 0
2 | disable_receive_used_bit_read_interrupt | Disable receive used bit read interrupt | WO | 0
1 | disable_receive_complete_interrupt | Disable receive complete interrupt | WO | 0
0 | disable_management_done_interrupt | Disable management done interrupt | WO | 0

### gem_gxlmicrosemi : emac_int_mask

Address offset | 0x1030
Description | The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.
Type | RO

Bits | Field Name | Description | Type | Reset
31 | tx_lockup_detected_mask | TX lockup interrupt mask. | RO | 1
30 | rx_lockup_detected_mask | RX lockup interrupt mask. | RO | 1
29 | tsu_timer_comparison_mask | Enable TSU timer comparison interrupt mask. | RO | 1
28 | wol_event_received_mask | A read of this register returns the value of the WOL event received mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
27 | rx_lpi_indication_mask | A read of this register returns the value of the RX LPI indication mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written | RO | 1
26 | tsu_seconds_register_increment_mask | A read of this register returns the value of the TSU seconds register increment mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
25 | ptp_pdelay_resp_frame_transmitted_mask | A read of this register returns the value of the PTP pdelay_resp frame transmitted mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
24 | ptp_pdelay_req_frame_transmitted_mask | A read of this register returns the value of the PTP pdelay_req frame transmitted mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
23 | ptp_pdelay_resp_frame_received_mask | A read of this register returns the value of the PTP pdelay_resp frame received mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
22 | ptp_pdelay_req_frame_received_mask | A read of this register returns the value of the PTP pdelay_req frame received mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
21 | ptp_sync_frame_transmitted_mask | A read of this register returns the value of the PTP sync frame transmitted mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
20 | ptp_delay_req_frame_transmitted_mask | A read of this register returns the value of the PTP delay_req frame transmitted mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
19 | ptp_sync_frame_received_mask | A read of this register returns the value of the PTP sync frame received mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
18 | ptp_delay_req_frame_received_mask | A read of this register returns the value of the PTP delay_req frame received mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
17 | pcs_link_partner_page_mask | A read of this register returns the value of the PCS link partner page mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
16 | pcs_auto_negotiation_complete_interrupt_mask | A read of this register returns the value of the PCS auto-negotiation complete interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
15 | external_interrupt_mask | External interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
14 | pause_frame_transmitted_interrupt_mask | Pause frame transmitted interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
13 | pause_time_zero_interrupt_mask | Pause time zero interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
12 | pause_frame_with_non_zero_pause_quantum_interrupt_mask | Pause frame with non-zero pause quantum interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
11 | resp_not_ok_interrupt_mask | bresp/hresp not OK interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
10 | receive_overrun_interrupt_mask | Receive overrun interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
9 | link_change_interrupt_mask | A read of this register returns the value of the link change interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
8 | reserved_8 | Reserved, read as 0, ignored on write. | RO | 0
7 | transmit_complete_interrupt_mask | Transmit complete interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
6 | amba_error_interrupt_mask | Transmit frame corruption due to AMBA (AHB/AXI) error interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
5 | retry_limit_exceeded_or_late_collision_mask | A read of this register returns the value of the retry limit exceeded or late collision (gigabit mode only) interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
4 | transmit_buffer_under_run_interrupt_mask | Transmit buffer under run interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
3 | transmit_used_bit_read_interrupt_mask | Transmit used bit read interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
2 | receive_used_bit_read_interrupt_mask | Receive used bit read interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
1 | receive_complete_interrupt_mask | Receive complete interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1
0 | management_done_interrupt_mask | Management done interrupt mask., :0: Interrupt is enabled., :1: Interrupt is disabled., :A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. | RO | 1

### gem_gxlmicrosemi : emac_phy_management

Address offset | 0x1034
Description | Do not use this register. The eMAC MDIO port is unconnected.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | write0 | Must be written with 0. | RW | 0
30 | write1 | Must be written to 1 for a valid Clause 22 frame and to 0 for a valid Clause 45 frame. | RW | 0
29:28 | operation | Operation. For a Clause 45 frame: 00 is an addr, 01 is a write, 10 is a post read increment, 11 is a read frame. For a Clause 22 frame: 10 is a read, 01 is a write. | RW | 0x0
27:23 | phy_address | PHY address. | RW | 0x00
22:18 | register_address | Register address - specifies the register in the PHY to access. | RW | 0x00
17:16 | write10 | Must be written with 10. | RW | 0x0
15:0 | phy_write_read_data | For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. | RW | 0x0000

### gem_gxlmicrosemi : emac_pause_time

Address offset | 0x1038
Description | Received Pause Quantum Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | quantum | Received pause quantum - stores the current value of the received pause quantum register which is decremented every 512 bit times. | RO | 0x0000

### gem_gxlmicrosemi : emac_tx_pause_quantum

Address offset | 0x103C
Description | Transmit Pause Quantum Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | quantum_p1 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 1. | RW | 0xFFFF
15:0 | quantum | Transmit pause quantum - written with the pause quantum value for pause frame transmission. | RW | 0xFFFF

### gem_gxlmicrosemi : emac_pbuf_txcutthru

Address offset | 0x1040
Description | Transmit Partial Store and Forward Register. Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. This register contains the enable bit and watermark value for transmit cut-through operation.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | dma_tx_cutthru | Enable TX partial store and forward operation | RW | 0
30:9 | reserved | Reserved, read as 0, ignored on write. | RO | 0x00 0000
8:0 | dma_tx_cutthru_threshold | Watermark value corresponding to number of SRAM locations. This value must be >= 0x14. The actual number of bytes for the watermark is obtained by multiplying the watermark value by the value of the gem_tx_pbuf_data define divided by 8. The reset value depends on the value of the configuration option `gem_emac_tx_pbuf_addr, which is defined in the verilog defs configuration file. | RW | 0x1FF

### gem_gxlmicrosemi : emac_pbuf_rxcutthru

Address offset | 0x1044
Description | Receive Partial Store and Forward Register. Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. This register contains the enable bit and watermark value for receive cut-through operation.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | dma_rx_cutthru | Enable RX partial store and forward operation | RW | 0
30:9 | reserved | Reserved, read as 0, ignored on write. | RO | 0x00 0000
8:0 | dma_rx_cutthru_threshold | Watermark value corresponding to number of SRAM locations. The actual number of bytes for the watermark is obtained by multiplying the watermark value by the value of the gem_rx_pbuf_data define divided by 8. The reset value depends on the value of the configuration option `gem_emac_rx_pbuf_addr, which is defined in the verilog defs configuration file. | RW | 0x1FF

### gem_gxlmicrosemi : emac_jumbo_max_length

Address offset | 0x1048
Description | Maximum Jumbo Frame Size.
Type | RW

Bits | Field Name | Description | Type | Reset
31:14 | reserved_31_14 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
13:0 | jumbo_max_length | Maximum Jumbo Frame Size - resets to the gem_jumbo_max_length define value. | RW | 0x2800

### gem_gxlmicrosemi : emac_axi_max_pipeline

Address offset | 0x1054
Description | Used to set the maximum amount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO (defined in verilog defs.v)
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved | Reserved, read as 0, ignored on write. | RO | 0x0000
16 | use_aw2b_fill | For the write issuing capability as defined in bits 15:8 of this register, select whether the max number of transactions operates between the AW to W AXI channel or the AW to B channel. Set to 0 to operate between the AW and W channels. Set to 1 to operate between the AW and B channels. | RW | 0
15:8 | aw2w_max_pipeline | Defines the maximum number of outstanding AXI write requests that can be issued by the DMA via the AW channel. This is effectively the write issuing capability. | RW | 0x01
7:0 | ar2r_max_pipeline | Defines the maximum number of outstanding AXI read requests that can be issued by the DMA via the AR channel. This is effectively the read issuing capability. | RW | 0x01

### gem_gxlmicrosemi : emac_int_moderation

Address offset | 0x105C
Description | Used to moderate the number of transmit and receive complete interrupts issued. With interrupt moderation enabled receive and transmit interrupts are not generated immediately a frame is transmitted or received. Instead when a receive or transmit event occurs a timer is started and the interrupt is asserted after it times out. This limits the frequency with which the CPU receives interrupts. When interrupt moderation is enabled interrupt status bit one is always used for receive and bit 7 is always used for transmit even when priority queuing is enabled. With interrupt moderation 800ns periods are counted. GEM determines what constitutes an 800ns period by looking at the tbi (bit 11), gigabit bit (10) and speed (bit 0) bits in the network configuration register and counting tx_clk cycles. Bit 0 needs to be set to 1 for 100M operation., :From release 1p11 onwards a frame threshold value may also be used to moderate interrupts. If both time based and frame threshold moderation is enabled the interrupt will be asserted as soon as the first moderation method expires.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | tx_int_mod_thresh | Count of transmitted frames before bit 7 is set in the interrupt status register. A non-zero value indicates transmit interrupt moderation will be performed. | RW | 0x00
23:16 | tx_int_moderation | Count of 800ns periods before bit 7 is set in the interrupt status register after a frame is transmitted. A non-zero value indicates transmit interrupt moderation will be performed. | RW | 0x00
15:8 | rx_int_mod_thresh | Count of received frames before bit 1 is set in the interrupt status register. A non-zero value indicates receive interrupt moderation will be performed. | RW | 0x00
7:0 | rx_int_moderation | Count of 800ns periods before bit 1 is set in the interrupt status register after a frame is received. A non-zero value indicates receive interrupt moderation will be performed. | RW | 0x00

### gem_gxlmicrosemi : emac_sys_wake_time

Address offset | 0x1060
Description | Used to pause transmission after deassertion of tx_lpi_en. Each unit in this register corresponds to 25.6ns in 2.5G mode, 64ns in gigabit mode, 320ns in 100M mode and 3200ns at 10M. After tx_lpi_en is deasserted transmission will pause for the set time.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | sys_wake_time | Count of 25.6ns, 64ns, 320ns or 3200ns intervals before transmission starts after deassertion of tx_lpi_en (each interval is equivalent to eight tx_clk periods and so varies with data rate). | RW | 0x0000

### gem_gxlmicrosemi : emac_lockup_config

Address offset | 0x1068
Description | The lockup detection and recovery configuration register.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | tx_dma_lockup_mon_en | Enable the TX DMA lockup detector. Enable the monitor that detects lockups in the transmit DMA. | RW | 0
30 | tx_mac_lockup_mon_en | Enable the TX MAC lockup detector. Enable the monitor that detects lockups in the MAC transmit path. | RW | 0
29 | rx_dma_lockup_mon_en | Enable the RX DMA lockup detector. Enable the monitor that detects lockups in the receive DMA. | RW | 0
28 | rx_mac_lockup_mon_en | Enable the RX MAC lockup detector. Enable the monitor that detects lockups in the MAC receive path. | RW | 0
27 | lockup_recovery_en | Lockup recovery. If this bit is set then the module will go into a soft reset state if a lockup is detected on the transmit or receive data paths. | RW | 0
26:16 | dma_lockup_time | Prior to release 1p11 this field was reserved. From release 1p11 onwards this field defines the timeout value for transmit and receive DMA lockup detection defined as a multiple of the prescaler value stored in bits 15:0 of this register. | RW | 0x7FF
15:0 | prescaler_value | For release 1p10 this field defined the time (measured in units of 1024 tx_clk periods) after which the lockup detection monitors would trigger, except for the receive MAC lock up detector which had its lockup time register. From release 1p11 onwards this field defines a prescaler value which is the number of tx_clk periods used to scale the timeout registers. | RW | 0xFFFF

### gem_gxlmicrosemi : emac_mac_lockup_time

Address offset | 0x106C
Description | MAC lockup detection time register. For receive this register specifies the maximum time between received frames. If no valid EOP is seen at the receive FIFO interface within the timer period then a lockup is considered to have occurred in the receive MAC. For transmit the MAC lockup time is simply the time it takes for data to be seen on the MII output pins after entering on the MAC FIFO interface.
Type | RW

Bits | Field Name | Description | Type | Reset
31:27 | reserved_31_27 | Reserved, read as 0, ignored on write. | RO | 0x00
26:16 | tx_mac_lockup_time | Prior to release 1p11 this field was reserved. From release 1p11 onwards this field defines the timeout value for transmit MAC lockup detection defined as a multiple of the prescaler value stored in bits 15:0 of the lockup config register. | RW | 0x7FF
15:0 | rx_mac_lockup_time | The time after which the receive MAC lockup detection monitor will trigger. For release 1p10 this was measured in units of 1024 tx_clk periods. From release 1p11 onwards it is used in conjunction with the prescaler stored in bits 15:0 of the lockup config register. | RW | 0xFFFF

### gem_gxlmicrosemi : emac_lockup_config3

Address offset | 0x1070
Description | eMAC DMA TX Lockup Enable Control Register. This register enables the lockup timer for queue 0.
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved_31_1 | Reserved, read as 0, ignored on write. | RO | 0x0000 0000
0 | dma_tx_lockup_en_q_0 | Enable DMA TX lockup timer for queue 0. | RW | 0

### gem_gxlmicrosemi : emac_rx_water_mark

Address offset | 0x107C
Description | rx_water_mark - Receive water mark register. This register contains the high and low water-marks for automatic transmission of pause frames. The water-marks are compared against the internal signal rx_dpram_fill_lvl which is readable in the dpram_fill_dbg register; rx_dpram_fill_lvl indicates the number of words used in the receive SRAM (word length is configuration dependent and may be 4, 8 and 16 bytes). A value of zero in a field disables the corresponding functionality.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | rx_low_watermark | If this field is non-zero and the last pause frame transmitted was non-zero then a zero length pause frame is transmitted when the receive SRAM fill level falls below this value. | RW | 0x0000
15:0 | rx_high_watermark | If this field is non-zero and the receive SRAM fill level exceeds this value then a pause frame is transmitted | RW | 0x0000

### gem_gxlmicrosemi : emac_hash_bottom

Address offset | 0x1080
Description | The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. Hash Register Bottom 31:0.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | The first 32 bits of the hash address register. | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_hash_top

Address offset | 0x1084
Description | Hash Register Top 63:32
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | The remaining 32 bits of the hash address register. | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_spec_add1_bottom

Address offset | 0x1088
Description | The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | Octets 3 to 0 of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. See the MAC Filtering Block of the user guide for more information on how to program this register. | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_spec_add1_top

Address offset | 0x108C
Description | Specific Address Top
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16 | filter_type | This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. | RW | 0
15:0 | address | Specific address 1. Octets 5 and 4 of the destination/source address that is to be compared, that is bits 47:32. See MAC Filtering Block of the user guide for more information. | RW | 0x0000

### gem_gxlmicrosemi : emac_spec_add2_bottom

Address offset | 0x1090
Description | The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | Octets 3 to 0 of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. See the MAC Filtering Block of the user guide for more information on how to program this register. | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_spec_add2_top

Address offset | 0x1094
Description | Specific Address Top
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:24 | filter_byte_mask | When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. | RW | 0x00
23:17 | reserved_23_17 | Reserved, read as 0, ignored on write. | RO | 0x00
16 | filter_type | This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. | RW | 0
15:0 | address | Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. See MAC Filtering Block of the user guide for more information. | RW | 0x0000

### gem_gxlmicrosemi : emac_spec_add3_bottom

Address offset | 0x1098
Description | The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | Octets 3 to 0 of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. See the MAC Filtering Block of the user guide for more information on how to program this register. | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_spec_add3_top

Address offset | 0x109C
Description | Specific Address Top
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:24 | filter_byte_mask | When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. | RW | 0x00
23:17 | reserved_23_17 | Reserved, read as 0, ignored on write. | RO | 0x00
16 | filter_type | This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. | RW | 0
15:0 | address | Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. See MAC Filtering Block of the user guide for more information. | RW | 0x0000

### gem_gxlmicrosemi : emac_spec_add4_bottom

Address offset | 0x10A0
Description | The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | Octets 3 to 0 of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. See the MAC Filtering Block of the user guide for more information on how to program this register. | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_spec_add4_top

Address offset | 0x10A4
Description | Specific Address Top
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:24 | filter_byte_mask | When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. | RW | 0x00
23:17 | reserved_23_17 | Reserved, read as 0, ignored on write. | RO | 0x00
16 | filter_type | This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. | RW | 0
15:0 | address | Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. See MAC Filtering Block of the user guide for more information. | RW | 0x0000

### gem_gxlmicrosemi : emac_spec_type1

Address offset | 0x10A8
Description | Type ID Match 1
Type | RW

Bits | Field Name | Description | Type | Reset
31 | enable_copy | Enable copying of type ID match 1 matched frames. | RW | 0
30:16 | reserved_30_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | match | Type ID match 1. For use in comparisons with received frames type ID/length field. | RW | 0x0000

### gem_gxlmicrosemi : emac_spec_type2

Address offset | 0x10AC
Description | Type ID Match 2
Type | RW

Bits | Field Name | Description | Type | Reset
31 | enable_copy | Enable copying of type ID match 2 matched frames. | RW | 0
30:16 | reserved_30_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | match | Type ID match 2. For use in comparisons with received frames type ID/length field. | RW | 0x0000

### gem_gxlmicrosemi : emac_spec_type3

Address offset | 0x10B0
Description | Type ID Match 3
Type | RW

Bits | Field Name | Description | Type | Reset
31 | enable_copy | Enable copying of type ID match 3 matched frames. | RW | 0
30:16 | reserved_30_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | match | Type ID match 3. For use in comparisons with received frames type ID/length field. | RW | 0x0000

### gem_gxlmicrosemi : emac_spec_type4

Address offset | 0x10B4
Description | Type ID Match 4
Type | RW

Bits | Field Name | Description | Type | Reset
31 | enable_copy | Enable copying of type ID match 4 matched frames. | RW | 0
30:16 | reserved_30_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | match | Type ID match 4. For use in comparisons with received frames type ID/length field. | RW | 0x0000

### gem_gxlmicrosemi : emac_wol_register

Address offset | 0x10B8
Description | Wake on LAN Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:20 | reserved_31_20 | Reserved - read 0, ignored when written. | RO | 0x000
19 | wol_mask_3 | Wake on LAN multicast hash event enable. When set multicast hash events will cause the wol output to be asserted. | RW | 0
18 | wol_mask_2 | Wake on LAN specific address register 1 event enable. When set specific address 1 events will cause the wol output to be asserted. | RW | 0
17 | wol_mask_1 | Wake on LAN ARP request event enable. When set ARP request events will cause the wol output to be asserted. | RW | 0
16 | wol_mask_0 | Wake on LAN magic packet event enable. When set magic packet events will cause the wol output to be asserted. | RW | 0
15:0 | addr | Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event, even if this is matched by the received frame. | RW | 0x0000

### gem_gxlmicrosemi : emac_stretch_ratio

Address offset | 0x10BC
Description | IPG stretch register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | ipg_stretch | IPG Stretch. Bits 7:0 are multiplied with the previously transmitted frame length (including preamble) bits 15:8 +1 divide the frame length. If the resulting number is greater than 96 and bit 28 is set in the network configuration register then the resulting number is used for the transmit inter-packet-gap. 1 is added to bits 15:8 to prevent a divide by zero. | RW | 0x0000

### gem_gxlmicrosemi : emac_stacked_vlan

Address offset | 0x10C0
Description | Stacked VLAN Register
Type | RW

Bits | Field Name | Description | Type | Reset
31 | enable_processing | Enable stacked VLAN processing mode | RW | 0
30:16 | reserved_30_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | match | User defined VLAN_TYPE field. When Stacked VLAN is enabled, the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type (0x8100). Note that the second VLAN tag of a Stacked VLAN packet will only be matched correctly if its VLAN_TYPE field equals 0x8100. | RW | 0x0000

### gem_gxlmicrosemi : emac_tx_pfc_pause

Address offset | 0x10C4
Description | Transmit PFC Pause Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:8 | vector | Priority Vector Pause Size. If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8], the PFC pause frame's pause quantum field associated with that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit PFC Pause Register [15:8], the pause quantum associated with that entry will be zero. | RW | 0x00
7:0 | vector_enable | Priority Vector Enable. If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0]. | RW | 0x00

### gem_gxlmicrosemi : emac_mask_add1_bottom

Address offset | 0x10C8
Description | Specific Address Mask 1 Bottom 31:0
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address_mask | Specific Address Mask. Setting a bit to one masks the corresponding bit in the specific address 1 register | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_mask_add1_top

Address offset | 0x10CC
Description | Specific Address Mask 1 Top 47:32
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | address_mask | Specific Address Mask. Setting a bit to one masks the corresponding bit in the specific address 1 register | RW | 0x0000

### gem_gxlmicrosemi : emac_dma_addr_or_mask

Address offset | 0x10D0
Description | Receive DMA Data Buffer Address Mask - only applies to AHB operation
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | mask_value | Data Buffer Address Mask Value. Values used to force bits 31:28 of the receive data buffer AHB address to a particular value when the associated enable bits stored in this register [3:0] are set. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external system memory. | RW | 0x0
27:4 | reserved_27_4 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
3:0 | mask_enable | Data Buffer Address Mask Enable. These bits are associated directly with bits[31:28].When bit 0 is set, the AHB address bit 28 used for accessing the receive data buffers will be forced to the value stored in bit 28 of this register. When bit 1 is set, the AHB address bit 29 used for accessing the receive data buffers will be forced to the value stored in bit 29 of this register. When bit 2 is set, the AHB address bit 30 used for accessing the receive data buffers will be forced to the value stored in bit 30 of this register. When bit 3 is set, the AHB address bit 31 used for accessing the receive data buffers will be forced to the value stored in bit 31 of this register. When these bits are clear, the associated value stored in bits 31:28 have no effect on the AHB address used for receive data buffer accesses. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external memory. | RW | 0x0

### gem_gxlmicrosemi : emac_rx_ptp_unicast

Address offset | 0x10D4
Description | PTP RX unicast IP destination address
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | Unicast IP destination address. Used for detection of PTP frames on receive path. | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_tx_ptp_unicast

Address offset | 0x10D8
Description | PTP TX unicast IP destination address
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | address | Unicast IP destination address. Used for detection of PTP frames on transmit path. | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_nsec_cmp

Address offset | 0x10DC
Description | TSU timer comparison value nanoseconds
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved_31_22 | Reserved, read as 0, ignored on write. | RO | 0x000
21:0 | comparison_value | TSU timer comparison value (ns). Value is compared to the bits[45:24] of the TSU timer count value (upper 22 bits of nanosecond value). The output tsu_timer_cmp_val is driven high when the timer comparison values match the TSU count value. From release 1p11 onwards this comparison only occurs once the nanosecond compare register has been written and when the match occurs tsu_timer_cmp_val will only be driven high for a single tsu_clk period. | RW | 0x00 0000

### gem_gxlmicrosemi : emac_tsu_sec_cmp

Address offset | 0x10E0
Description | TSU timer comparison value seconds 31:0
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | comparison_value | TSU timer comparison value (s). Value is compared to seconds value bits [31:0] of the TSU timer count value. | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_msb_sec_cmp

Address offset | 0x10E4
Description | TSU timer comparison value seconds 47:32
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | comparison_value | TSU timer comparison value (s). Value is compared to the top 16 bits (most significant 16-bits [47:32] of seconds value) of the TSU timer count value. | RW | 0x0000

### gem_gxlmicrosemi : emac_tsu_ptp_tx_msb_sec

Address offset | 0x10E8
Description | PTP Event Frame Transmitted Seconds Register 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | timer_seconds | PTP Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. | RO | 0x0000

### gem_gxlmicrosemi : emac_tsu_ptp_rx_msb_sec

Address offset | 0x10EC
Description | PTP Event Frame Received Seconds Register 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | timer_seconds | PTP Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. | RO | 0x0000

### gem_gxlmicrosemi : emac_tsu_peer_tx_msb_sec

Address offset | 0x10F0
Description | PTP Peer Event Frame Transmitted Seconds Register 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | timer_seconds | PTP Peer Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. | RO | 0x0000

### gem_gxlmicrosemi : emac_tsu_peer_rx_msb_sec

Address offset | 0x10F4
Description | PTP Peer Event Frame Received Seconds Register 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | timer_seconds | PTP Peer Event Frame RX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. | RO | 0x0000

### gem_gxlmicrosemi : emac_dpram_fill_dbg

Address offset | 0x10F8
Description | The fill levels for the TX and RX packet buffer SRAMs can be read using this register, including the fill level for each queue in the TX direction. The fill level is reported as the number of word locations used. The number of bytes will depend on the SRAM data width.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | dma_tx_rx_fill_level | Fill Level - TX or RX packet buffer fill level, selected by the tx_q_fill_level_select and tx_rx_fill_level_select registers. Read this register to determine the fill level. | RO | 0x0000
15:8 | reserved_15_8 | Reserved, read as 0, ignored on write. | RO | 0x00
7:4 | dma_tx_q_fill_level_select | TX queue fill level select - select what TX queue to report fill levels for. | RW | 0x0
3:1 | reserved_3_1 | Reserved, read as 0, ignored on write. | RO | 0x0
0 | dma_tx_rx_fill_level_select | TX/RX Fill Level select - report the fill level for the TX or RX packet buffer. Set 1 for transmit and 0 for receive. | RW | 0

### gem_gxlmicrosemi : emac_revision_reg

Address offset | 0x10FC
Description | This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | fix_number | Fix number - incremented for fix releases. | RO | 0x0
27:16 | module_identification_number | Module identification number - for the GEM, this value is fixed. | RO | 0x107
15:0 | module_revision | Module revision - fixed value specific to the revision of the design which is incremented for each non-fix release of the IP. | RO | 0x010C

### gem_gxlmicrosemi : emac_octets_txed_bottom

Address offset | 0x1100
Description | These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. In order to reduce overall design area, the statistics registers may be optionally removed in the configuration file if they are deemed unnecessary for a particular design. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. The statistics registers optionally have a snapshot capability which, when exercised, will simultaneously store and clear the current values of all the statistics registers into a snapshot register set in order to allow a consistent set of statistics to be read by the processor. The snapshot is controlled using bit 13 of the network control register. The read snapshot control indicated by bit 14 of the network control register determines whether the processor reads the snapshot registers (logic 1) or the incrementing registers (logic 0). The default GEM configuration does not support the snapshot capability. See Parameterization section under Implementation Application Notes for an explanation of how to enable this function. All the statistics registers are read only. For test purposes they may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared. When reading the octets transmitted and octets received registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. The statistics register block contains the following registers. Octets Transmitted [31:0]
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Transmitted octets in frame without errors [31:0]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_octets_txed_top

Address offset | 0x1104
Description | Octets Transmitted 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | count | Transmitted octets in frame without errors [47:32]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : emac_frames_txed_ok

Address offset | 0x1108
Description | Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Frames transmitted without error. A 32 bit register counting the number of frames successfully transmitted, i.e. no under run and not too many retries. Excludes pause frames. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_broadcast_txed

Address offset | 0x110C
Description | Broadcast Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Broadcast frames transmitted without error. A 32 bit register counting the number of broadcast frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_multicast_txed

Address offset | 0x1110
Description | Multicast Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Multicast frames transmitted without error. A 32 bit register counting the number of multicast frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_pause_frames_txed

Address offset | 0x1114
Description | Pause Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | count | Transmitted pause frames - a 16 bit register counting the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins or automatically when rx_water_mark is reached are counted as pause frames. Pause frames received through the external FIFO interface are counted in the frames transmitted counter. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : emac_frames_txed_64

Address offset | 0x1118
Description | 64 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 64 byte frames transmitted without error. A 32 bit register counting the number of 64 byte frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_frames_txed_65

Address offset | 0x111C
Description | 65 to 127 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 65 to127 byte frames transmitted without error. A 32 bit register counting the number of 65 to127 byte frames successfully transmitted without error, i.e. no under run and not too many retries. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_frames_txed_128

Address offset | 0x1120
Description | 128 to 255 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 128 to 255 byte frames transmitted without error. A 32 bit register counting the number of 128 to 255 byte frames successfully transmitted without error, i.e. no under run and not too many retries. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_frames_txed_256

Address offset | 0x1124
Description | 256 to 511 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 256 to 511 byte frames transmitted without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error, i.e. no under run and not too many retries. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_frames_txed_512

Address offset | 0x1128
Description | 512 to 1023 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 512 to 1023 byte frames transmitted without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully transmitted without error, i.e. no under run and not too many retries. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_frames_txed_1024

Address offset | 0x112C
Description | 1024 to 1518 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 1024 to 1518 byte frames transmitted without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully transmitted without error, i.e. no under run and not too many retries. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_frames_txed_1519

Address offset | 0x1130
Description | Greater Than 1518 Byte Frames Transmitted
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Greater than 1518 byte frames transmitted without error. A 32 bit register counting the number of 1518 or above byte frames successfully transmitted without error, i.e. no under run and not too many retries. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_tx_underruns

Address offset | 0x1134
Description | Transmit Under Runs
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Transmit under runs - a 10 bit register counting the number of frames not transmitted due to a transmit under run. If this register is incremented then no other statistics register is incremented. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_single_collisions

Address offset | 0x1138
Description | Single Collision Frames
Type | RO

Bits | Field Name | Description | Type | Reset
31:18 | reserved_31_18 | Reserved, read as 0, ignored on write. | RO | 0x0000
17:0 | count | Single collision frames - an 18 bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no under run. | RO RtoClr | 0x0 0000

### gem_gxlmicrosemi : emac_multiple_collisions

Address offset | 0x113C
Description | Multiple Collision Frames
Type | RO

Bits | Field Name | Description | Type | Reset
31:18 | reserved_31_18 | Reserved, read as 0, ignored on write. | RO | 0x0000
17:0 | count | Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no under run and not too many retries. | RO RtoClr | 0x0 0000

### gem_gxlmicrosemi : emac_excessive_collisions

Address offset | 0x1140
Description | Excessive Collisions
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Excessive collisions - a 10 bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_late_collisions

Address offset | 0x1144
Description | Late Collisions
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Late collisions - a 10 bit register counting the number of late collision occurring after the slot time (512 bits) has expired. In 10/100 mode, late collisions are counted twice i.e. both as a collision and a late collision. In gigabit mode, a late collision causes the transmission to be aborted, thus the single and multi collision registers are not updated. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_deferred_frames

Address offset | 0x1148
Description | Deferred Transmission Frames
Type | RO

Bits | Field Name | Description | Type | Reset
31:18 | reserved_31_18 | Reserved, read as 0, ignored on write. | RO | 0x0000
17:0 | count | Deferred transmission frames - an 18 bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit under run. | RO RtoClr | 0x0 0000

### gem_gxlmicrosemi : emac_crs_errors

Address offset | 0x114C
Description | Carrier Sense Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Carrier sense errors - a 10 bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no under run). Only incremented in half-duplex mode. The only effect of a carrier sense error is to increment this register. The behaviour of the other statistics registers is unaffected by the detection of a carrier sense error. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_octets_rxed_bottom

Address offset | 0x1150
Description | Octets Received 31:0
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_octets_rxed_top

Address offset | 0x1154
Description | Octets Received 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | count | Received octets in frame without errors [47:32]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : emac_frames_rxed_ok

Address offset | 0x1158
Description | Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Frames received without error. A 32 bit register counting the number of frames successfully received. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_broadcast_rxed

Address offset | 0x115C
Description | Broadcast Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Broadcast frames received without error. A 32 bit register counting the number of broadcast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_multicast_rxed

Address offset | 0x1160
Description | Multicast Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | Multicast frames received without error. A 32 bit register counting the number of multicast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_pause_frames_rxed

Address offset | 0x1164
Description | Pause Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | count | Received pause frames - a 16 bit register counting the number of pause frames received without error. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : emac_frames_rxed_64

Address offset | 0x1168
Description | 64 Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 64 byte frames received without error. A 32 bit register counting the number of 64 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_frames_rxed_65

Address offset | 0x116C
Description | 65 to 127 Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 65 to 127 byte frames received without error. A 32 bit register counting the number of 65 to 127 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_frames_rxed_128

Address offset | 0x1170
Description | 128 to 255 Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 128 to 255 byte frames received without error. A 32 bit register counting the number of 128 to 255 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_frames_rxed_256

Address offset | 0x1174
Description | 256 to 511 Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 256 to 511 byte frames received without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_frames_rxed_512

Address offset | 0x1178
Description | 512 to 1023 Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 512 to 1023 byte frames received without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_frames_rxed_1024

Address offset | 0x117C
Description | 1024 to 1518 Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 1024 to 1518 byte frames received without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_frames_rxed_1519

Address offset | 0x1180
Description | 1519 to maximum Byte Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | count | 1519 to maximum byte frames received without error. A 32 bit register counting the number of 1519 byte or above frames successfully received without error. Maximum frame size is determined by the network configuration register bit 8 (1536 maximum frame size) or bit 3 (jumbo frame size). Excludes pause frames, and is only incremented if the frame is successfully filtered. | RO RtoClr | 0x0000 0000

### gem_gxlmicrosemi : emac_undersize_frames

Address offset | 0x1184
Description | Undersized Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Undersize frames received - a 10 bit register counting the number of frames received less than 64 bytes in length (10/100 mode or gigabit mode, full duplex) that do not have either a CRC error or an alignment error. In gigabit mode, half-duplex, this register counts either frames not conforming to the minimum slot time of 512 bytes or frames not conforming to the minimum frame size once bursting is active. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_excessive_rx_length

Address offset | 0x1188
Description | Oversize Frames Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved read 0, ignored on write. | RO | 0x00 0000
9:0 | count | Oversize frames received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 bytes if bit 8 is set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register) in length but do not have either a CRC error, an alignment error nor a receive symbol error. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_rx_jabbers

Address offset | 0x118C
Description | Jabbers Received
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Jabbers received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_fcs_errors

Address offset | 0x1190
Description | Frame Check Sequence Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Frame check sequence errors - a 10 bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes. This register is incremented for a frame with bad FCS, regardless of whether it is copied to memory due to ignore FCS mode being enabled in bit 26 of the network configuration register. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_rx_length_errors

Address offset | 0x1194
Description | Length Field Frame Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Length field frame errors - this 10-bit register counts the number of frames received that have a measured length shorter than that extracted from the length field (bytes 13 and 14). This condition is only counted if the value of the length field is less than 0x0600, the frame is not of excessive length and checking is enabled through bit 16 of the network configuration register. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_rx_symbol_errors

Address offset | 0x1198
Description | Receive Symbol Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Receive symbol errors - a 10-bit register counting the number of frames that had rx_er asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks. For gigabit mode the frame must satisfy slot time requirements in order to count a symbol error. Additionally, in gigabit half-duplex mode, carrier extension errors are also recorded. Receive symbol errors will also be counted as an FCS or alignment error if the frame is between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register, 10240 bytes if bit 3 is set in the network configuration register). If the frame is larger it will be recorded as a jabber error. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_alignment_errors

Address offset | 0x119C
Description | Alignment Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Alignment errors - a 10 bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_rx_resource_errors

Address offset | 0x11A0
Description | Receive Resource Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:18 | reserved_31_18 | Reserved, read as 0, ignored on write. | RO | 0x0000
17:0 | count | Receive resource errors - an 18 bit register counting the number of times a receive buffer descriptor was read with its used bit set. This can be used as a means of checking the efficiency of the software in processing and releasing receive buffers. In an ideally configured system, this counter would not increase. | RO RtoClr | 0x0 0000

### gem_gxlmicrosemi : emac_rx_overruns

Address offset | 0x11A4
Description | Receive Overruns
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved_31_10 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
9:0 | count | Receive overruns - a 10 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive overrun. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_rx_ip_ck_errors

Address offset | 0x11A8
Description | IP Header Checksum Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:0 | count | IP header checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect IP header checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error. | RO RtoClr | 0x00

### gem_gxlmicrosemi : emac_rx_tcp_ck_errors

Address offset | 0x11AC
Description | TCP Checksum Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:0 | count | TCP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect TCP checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error. | RO RtoClr | 0x00

### gem_gxlmicrosemi : emac_rx_udp_ck_errors

Address offset | 0x11B0
Description | UDP Checksum Errors
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:0 | count | UDP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect UDP checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error. | RO RtoClr | 0x00

### gem_gxlmicrosemi : emac_auto_flushed_pkts

Address offset | 0x11B4
Description | Receive DMA Flushed Packets
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | count | Flushed RX packets counter. A 16 bit register counting the number of frames that have been flushed from the receive SRAM based packet buffer due to one of the following reasons:, :1. When either partial store and forward mode, bit 24 of the DMA configuration register, or the drop_on_resource_err mode of the traffic policing feature is active, and a packet is received while there is no AMBA (AHB/AXI) resource (no free descriptors for the DUT to use)., :2. When partial store and forward mode is enabled and an AMBA (AHB/AXI) error is encountered while writing the packet data to external memory., :3. When bit 18 of the network control register (software action to flush a packet from the head of the PBUF queue) is pulsed and the GEM DMA is not currently busy., :4. When a frame is dropped due to the policing actions defined in the rx_qX_flush registers located at 0x0b00-0x0b3c. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : emac_tsu_timer_incr_sub_nsec

Address offset | 0x11BC
Description | 1588 Timer Increment Register sub nsec. From release 1p08f1 onwards this register must be written before the tsu_timer_incr register and the value written will not take effect until the tsu_timer_incr register is written to.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | sub_ns_incr_lsb | These are the least significant bits [7:0] of the sub-ns value by which the 1588 timer will be incremented each clock cycle. | RW | 0x00
23:16 | reserved_23_16 | Reserved, read as 0, ignored on write. | RO | 0x00
15:0 | sub_ns_incr | These are the most significant bits [23:8] of the sub-ns value by which the 1588 timer will be incremented each clock cycle. 24 bits of sub nanosecond precision gives resolution of approximately 5.86E-17 seconds (16 bits gives 15.2 femtoseconds). | RW | 0x0000

### gem_gxlmicrosemi : emac_tsu_timer_msb_sec

Address offset | 0x11C0
Description | 1588 Timer Seconds Register 47:32
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | timer | TSU timer value (s). Most significant 16 bits of seconds timer count. The register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented or decremented when the timer adjust register is written (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF). Note: The value of this register is used only when the lower 32 bit register is written to. This is to ensure a single update of the 48 bit seconds value | RW | 0x0000

### gem_gxlmicrosemi : emac_tsu_strobe_msb_sec

Address offset | 0x11C4
Description | 1588 Timer Sync Strobe Seconds Register 47:32
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | strobe | 1588 Timer Sync Strobe Seconds. The most significant 16-bit value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero. | RO | 0x0000

### gem_gxlmicrosemi : emac_tsu_strobe_sec

Address offset | 0x11C8
Description | 1588 Timer Sync Strobe Seconds Register 31:0
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | strobe | 1588 Timer Sync Strobe Seconds. The lowest significant 32-bit value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero. | RO | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_strobe_nsec

Address offset | 0x11CC
Description | 1588 Timer Sync Strobe Nanoseconds Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:0 | strobe | 1588 Timer Sync Strobe Nanoseconds. The value of the Timer Nanoseconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero. | RO | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_timer_sec

Address offset | 0x11D0
Description | 1588 Timer Seconds Register 31:0
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | timer | 1588 Timer Seconds Register. TSU timer value (s). Least significant 32 bits of seconds timer count. This register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented or decremented when the timer adjust register is written (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF). | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_timer_nsec

Address offset | 0x11D4
Description | 1588 Timer Nanoseconds Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:0 | timer | Timer count in nanoseconds. This register is writeable. It can also be adjusted by writes to the 1588 timer adjust register. It increments by the value of the 1588 timer increment register each clock cycle (if this register is close to zero and a write to the timer adjust register causes a decrement the seconds register will be decremented if necessary and the nanoseconds register will roll back to 9999999xx (decimal)). | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_timer_adjust

Address offset | 0x11D8
Description | This register is used to adjust the value of the timer in the TSU. It allows an integral number of nanoseconds to be added or subtracted from the timer in a one-off operation. This register returns all zeroes when read.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | add_subtract | Write as one to subtract from the 1588 timer. Write as zero to add to it. | WO | 0
30 | reserved_30 | Reserved, read as 0, ignored on write. | RO | 0
29:0 | increment_value | Timer increment value. The number of nanoseconds to increment or decrement the 1588 timer nanoseconds register. If necessary the 1588 seconds register will be incremented or decremented. | WO | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_timer_incr

Address offset | 0x11DC
Description | 1588 Timer Increment Register. From release 1p08f1 onwards this register must be written after the tsu_timer_incr_sub_ns register and the write operation will cause the value written to the tsu_timer_incr_sub_ns register to take effect.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | num_incs | Number of incs before alt inc. The number of increments after which the alternative increment is used. | RW | 0x00
15:8 | alt_ns_incr | Alternative nanoseconds count. Alternative count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. | RW | 0x00
7:0 | ns_increment | A count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. These are the most significant 8 bits of the 32 bit timer_increment counter. The tsu_timer_incr_sub_nsec register holds the least significant 24 bits of the increment. | RW | 0x00

### gem_gxlmicrosemi : emac_tsu_ptp_tx_sec

Address offset | 0x11E0
Description | PTP Event Frame Transmitted Seconds Register 31:0
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | timer | PTP Event Frame Transmitted Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_ptp_tx_nsec

Address offset | 0x11E4
Description | PTP Event Frame Transmitted Nanoseconds Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:0 | timer | PTP Event Frame Transmitted Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_ptp_rx_sec

Address offset | 0x11E8
Description | PTP Event Frame Received Seconds Register 31:0
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | timer | PTP Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_ptp_rx_nsec

Address offset | 0x11EC
Description | PTP Event Frame Received Nanoseconds Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:0 | timer | PTP Event Frame Received Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_peer_tx_sec

Address offset | 0x11F0
Description | PTP Peer Event Frame Transmitted Seconds Register 31:0
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | timer | PTP Peer Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_peer_tx_nsec

Address offset | 0x11F4
Description | PTP Peer Event Frame Transmitted Nanoseconds Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:0 | timer | PTP Peer Event Frame Transmitted Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_peer_rx_sec

Address offset | 0x11F8
Description | PTP Peer Event Frame Received Seconds Register 31:0
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | timer | PTP Peer Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : emac_tsu_peer_rx_nsec

Address offset | 0x11FC
Description | PTP Peer Event Frame Received Nanoseconds Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Reserved, read as 0, ignored on write. | RO | 0x0
29:0 | timer | PTP Peer Event Frame Received Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. | RO | 0x0000 0000

### gem_gxlmicrosemi : emac_tx_pause_quantum1

Address offset | 0x1260
Description | Transmit Pause Quantum Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | quantum_p3 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 3. | RW | 0xFFFF
15:0 | quantum_p2 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 2. | RW | 0xFFFF

### gem_gxlmicrosemi : emac_tx_pause_quantum2

Address offset | 0x1264
Description | Transmit Pause Quantum Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | quantum_p5 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 5. | RW | 0xFFFF
15:0 | quantum_p4 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 4. | RW | 0xFFFF

### gem_gxlmicrosemi : emac_tx_pause_quantum3

Address offset | 0x1268
Description | Transmit Pause Quantum Register 3
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | quantum_p7 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 7. | RW | 0xFFFF
15:0 | quantum_p6 | Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 6. | RW | 0xFFFF

### gem_gxlmicrosemi : emac_pfc_status

Address offset | 0x126C
Description | Priority Flow Control status register - indicates whether PFC has been negotiated and the current state of the PFC counters for each priority.
Type | RO

Bits | Field Name | Description | Type | Reset
31:9 | reserved_31_9 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
8 | pfc_negotiate_pclk | Set when PFC Priority Based Pause has been negotiated. | RO | 0
7:0 | rx_pfc_paused | Reflects the state of the rx_pfc_paused signals. Each bit in the vector corresponds to a priority indicated within the received PFC priority based pause frame. A bit is set when a PFC priority based pause frame has been received, and the associated priority pause time quantum is non-zero. The bit is cleared when the associated pause time has elapsed. | RO | 0x00

### gem_gxlmicrosemi : emac_rx_lpi

Address offset | 0x1270
Description | Received LPI transitions
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Unused, read zero | RO | 0x0000
15:0 | count | Count of RX LPI transitions. A count of the number of times there is a transition from receiving normal idle to receiving low power idle. Cleared on read. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : emac_rx_lpi_time

Address offset | 0x1274
Description | Received LPI time
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Unused, read zero | RO | 0x00
23:0 | lpi_time | Time in LPI. This register increments once every 16 pclk cycles when the LPI indication bit 7 is set in the network status register. Cleared on read. | RO RtoClr | 0x00 0000

### gem_gxlmicrosemi : emac_tx_lpi

Address offset | 0x1278
Description | Transmit LPI transitions
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Unused, read zero | RO | 0x0000
15:0 | count | Count of TX LPI transmissions. A count of the number of times the enable LPI transmission bit 19 goes from low to high in the network control register. Cleared on read. | RO RtoClr | 0x0000

### gem_gxlmicrosemi : emac_tx_lpi_time

Address offset | 0x127C
Description | Transmit LPI time
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Unused, read zero | RO | 0x00
23:0 | lpi_time | Time in LPI. This register increments once every 16 pclk cycles when the enable LPI transmission bit 19 is set in the network control register. Cleared on read. | RO RtoClr | 0x00 0000

### gem_gxlmicrosemi : emac_designcfg_debug1

Address offset | 0x1280
Description | Design Configuration Register 1 - The GEM has many parameterisation options to configure the IP during compilation stage. This is achieved using Verilog define compiler directives in an include file called gem_defs.v. This configuration is readable through APB addressable designcfg_debug registers.
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | axi_cache_value | Takes the value of the `gem_axi_awcache_value DEFINE | RO | 0x0
27:25 | dma_bus_width | Takes the value of bits 7:5 of the `gem_dma_bus_width DEFINE. So if the define is set to decimal 64 this will return binary 010. | RO | 0x2
24 | exclude_cbs | Takes the value of the `gem_exclude_cbs DEFINE. | RO | 0
23 | irq_read_clear | Takes the value of the `gem_irq_read_clear DEFINE | RO | 0
22 | no_snapshot | Takes the value of the `gem_no_snapshot DEFINE | RO | 1
21 | no_stats | Takes the value of the `gem_no_stats DEFINE | RO | 0
20 | reserved_20 | Reserved, read as 1, ignored on write. | RO | 1
19:15 | user_in_width | Takes the value of the `gem_user_in_width DEFINE or 1 if user_io not defined | RO | 0x01
14:10 | user_out_width | Takes the value of the `gem_user_out_width DEFINE or 1 if user_io not defined | RO | 0x01
9 | user_io | user_io not defined for the eMAC | RO | 0
8 | reserved_8 | Reserved, read as 1, ignored on write. | RO | 1
7 | reserved_7 | Reserved, read as 0, ignored on write. | RO | 0
6 | ext_fifo_interface | Takes the value of the `gem_ext_fifo_interface DEFINE | RO | 0
5 | reserved_5 | Reserved, read as 0, ignored on write. | RO | 0
4 | int_loopback | Takes the value of the `gem_int_loopback DEFINE | RO | 1
3:2 | reserved_3_2 | Reserved, read as 0, ignored on write. | RO | 0x0
1 | exclude_qbv | Takes the value of the `gem_exclude_qbv DEFINE | RO | 0
0 | no_pcs | Takes the value of the `gem_no_pcs DEFINE | RO | 0

### gem_gxlmicrosemi : emac_designcfg_debug2

Address offset | 0x1284
Description | Design Configuration Register 2
Type | RO

Bits | Field Name | Description | Type | Reset
31 | spram | Takes the value of the `gem_spram DEFINE | RO | 0
30 | axi | Takes the value of the `gem_axi DEFINE | RO | 1
29:26 | tx_pbuf_addr | Takes the value of the `gem_emac_tx_pbuf_addr DEFINE or zero if pbuf_address is decimal 16 | RO | 0x9
25:22 | rx_pbuf_addr | Takes the value of the `gem_emac_rx_pbuf_addr DEFINE or zero if pbuf_address is decimal 16 | RO | 0x9
21 | tx_pkt_buffer | Takes the value of the `gem_tx_pkt_buffer DEFINE | RO | 1
20 | rx_pkt_buffer | Takes the value of the `gem_rx_pkt_buffer DEFINE | RO | 1
19:16 | hprot_value | Takes the value of the `gem_hprot_value DEFINE | RO | 0x1
15:14 | reserved_15_14 | Unused, read zero | RO | 0x0
13:0 | jumbo_max_length | Takes the value of the `gem_jumbo_max_length DEFINE | RO | 0x2800

### gem_gxlmicrosemi : emac_designcfg_debug3

Address offset | 0x1288
Description | Design Configuration Register 3
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved_31_30 | Unused, read zero | RO | 0x0
29:24 | num_spec_add_filters | Takes the value of the `num_spec_add_filters DEFINE | RO | 0x04
23:21 | reserved_23_21 | Unused, read zero | RO | 0x0
20:0 | reserved_20_0 | Unused, read zero - reserved for rx_base2_fifo_size and rx_fifo_size defines in internal FIFO mode | RO | 0x00 0000

### gem_gxlmicrosemi : emac_designcfg_debug4

Address offset | 0x128C
Description | Design Configuration Register 4
Type | RO

Bits | Field Name | Description | Type | Reset
31:20 | reserved_31_20 | Unused, read zero | RO | 0x000
19:0 | reserved_19_0 | Unused, read zero - reserved for tx_base2_fifo_size and tx_fifo_size defines in internal FIFO mode | RO | 0x0 0000

### gem_gxlmicrosemi : emac_designcfg_debug5

Address offset | 0x1290
Description | Design Configuration Register 5
Type | RO

Bits | Field Name | Description | Type | Reset
31:29 | axi_prot_value | Takes the value of the edma_axi_prot_value parameter which is set by the `gem_axi_prot_value DEFINE but will be zero if the FIFO interface has been configured | RO | 0x2
28 | tsu_clk | Takes the value of the `gem_tsu_clk DEFINE | RO | 1
27:20 | rx_buffer_length_def | Takes the value of the `gem_rx_buffer_length_def DEFINE | RO | 0x02
19 | tx_pbuf_size_def | Takes the value of the edma_tx_pbuf_size_def parameter which is set by the `gem_tx_pbuf_size_def DEFINE but will be zero if the FIFO inteface has been configured | RO | 1
18:17 | rx_pbuf_size_def | Takes the value of the `gem_rx_pbuf_size_def DEFINE | RO | 0x3
16:15 | endian_swap_def | Takes the value of the `gem_endian_swap_def DEFINE | RO | 0x0
14:12 | mdc_clock_div | Takes the value of the `gem_mdc_clock_div DEFINE | RO | 0x2
11:10 | dma_bus_width_def | Takes the value of the `gem_dma_bus_width_def DEFINE | RO | 0x1
9 | phy_ident | Indicates whether the top and bottom PHY_ID registers are present in the address map | RO | 1
8 | tsu | Takes the value of the `gem_tsu DEFINE | RO | 1
7:4 | tx_fifo_cnt_width | Takes the value of the `gem_tx_fifo_cnt_width DEFINE | RO | 0x4
3:0 | rx_fifo_cnt_width | Takes the value of the `gem_rx_fifo_cnt_width DEFINE | RO | 0x5

### gem_gxlmicrosemi : emac_designcfg_debug6

Address offset | 0x1294
Description | Design Configuration Register 6
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | reserved_31_28 | Reserved. Set to zero. | RO | 0x0
27 | pbuf_lso | Takes the value of the `gem_pbuf_lso DEFINE | RO | 1
26 | reserved_26 | Reserved. Set to zero. | RO | 0
25 | pbuf_cutthru | Takes the value of the `gem_pbuf_cutthru DEFINE | RO | 1
24 | pfc_multi_quantum | Takes the value of the `gem_pfc_multi_quantum DEFINE | RO | 1
23 | dma_addr_width_is_64b | Takes the value of the `gem_dma_addr_width_is_64b DEFINE | RO | 1
22 | host_if_soft_select | Takes the value of the `gem_host_if_soft_select DEFINE | RO | 0
21 | tx_add_fifo_if | Takes the value of the `gem_tx_add_fifo_if DEFINE | RO | 0
20 | ext_tsu_timer | Set to one to indicate external TSU | RO | 1
19:16 | tx_pbuf_queue_segment_size | Takes the value of the `gem_tx_pbuf_queue_segment_size DEFINE | RO | 0x2
15:0 | reserved_15_0 | Reserved. Set to zero. | RO | 0x0000

### gem_gxlmicrosemi : emac_designcfg_debug7

Address offset | 0x1298
Description | Design Configuration Register 7
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | tx_pbuf_num_segments_q7 | Takes the value of the `gem_tx_pbuf_num_segments_q7 DEFINE | RO | 0x0
27:24 | tx_pbuf_num_segments_q6 | Takes the value of the `gem_tx_pbuf_num_segments_q6 DEFINE | RO | 0x0
23:20 | tx_pbuf_num_segments_q5 | Takes the value of the `gem_tx_pbuf_num_segments_q5 DEFINE | RO | 0x0
19:16 | tx_pbuf_num_segments_q4 | Takes the value of the `gem_tx_pbuf_num_segments_q4 DEFINE | RO | 0x0
15:12 | tx_pbuf_num_segments_q3 | Takes the value of the `gem_tx_pbuf_num_segments_q3 DEFINE | RO | 0x0
11:8 | tx_pbuf_num_segments_q2 | Takes the value of the `gem_tx_pbuf_num_segments_q2 DEFINE | RO | 0x0
7:4 | tx_pbuf_num_segments_q1 | Takes the value of the `gem_tx_pbuf_num_segments_q1 DEFINE | RO | 0x0
3:0 | tx_pbuf_num_segments_q0 | Takes the value of the edma_tx_pbuf_num_segments_q0 parameter which is set by the `gem_tx_pbuf_num_segments_q0 DEFINE or is zero if priority queuing is not configured. | RO | 0x0

### gem_gxlmicrosemi : emac_designcfg_debug8

Address offset | 0x129C
Description | Design Configuration Register 8
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | num_type1_screeners | Set to 1 for the eMAC (express MAC) | RO | 0x01
23:16 | num_type2_screeners | Set to 2 for the eMAC (express MAC) | RO | 0x02
15:8 | num_scr2_ethtype_regs | Set to 0 for the eMAC (express MAC) | RO | 0x00
7:0 | num_scr2_compare_regs | Set to 6 for the eMAC (express MAC) | RO | 0x06

### gem_gxlmicrosemi : emac_designcfg_debug9

Address offset | 0x12A0
Description | Design Configuration Register 9
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | tx_pbuf_num_segments_q15 | Takes the value of the `gem_tx_pbuf_num_segments_q15 DEFINE | RO | 0x0
27:24 | tx_pbuf_num_segments_q14 | Takes the value of the `gem_tx_pbuf_num_segments_q14 DEFINE | RO | 0x0
23:20 | tx_pbuf_num_segments_q13 | Takes the value of the `gem_tx_pbuf_num_segments_q13 DEFINE | RO | 0x0
19:16 | tx_pbuf_num_segments_q12 | Takes the value of the `gem_tx_pbuf_num_segments_q12 DEFINE | RO | 0x0
15:12 | tx_pbuf_num_segments_q11 | Takes the value of the `gem_tx_pbuf_num_segments_q11 DEFINE | RO | 0x0
11:8 | tx_pbuf_num_segments_q10 | Takes the value of the `gem_tx_pbuf_num_segments_q10 DEFINE | RO | 0x0
7:4 | tx_pbuf_num_segments_q9 | Takes the value of the `gem_tx_pbuf_num_segments_q9 DEFINE | RO | 0x0
3:0 | tx_pbuf_num_segments_q8 | Takes the value of the `gem_tx_pbuf_num_segments_q8 DEFINE | RO | 0x0

### gem_gxlmicrosemi : emac_designcfg_debug10

Address offset | 0x12A4
Description | Design Configuration Register 10
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | emac_bus_width | Takes the value of the `gem_emac_bus_width DEFINE. 1 - The MAC has a datawidth of 32bits. 2 - The MAC has a datawidth of 64bits. 4 - The MAC has a datawidth of 128bits | RO | 0x2
27:24 | tx_pbuf_data | Takes the value of the `gem_tx_pbuf_data DEFINE. 1 - The TX DPRAM has a datawidth of 32bits. 2 - The TX DPRAM has a datawidth of 64bits. 4 - The TX DPRAM has a datawidth of 128bits | RO | 0x2
23:20 | rx_pbuf_data | Takes the value of the `gem_rx_pbuf_data DEFINE. 1 - The RX DPRAM has a datawidth of 32bits. 2 - The RX DPRAM has a datawidth of 64bits. 4 - RX The DPRAM has a datawidth of 128bits | RO | 0x2
19:16 | axi_access_pipeline_bits | Takes the value of the edma_axi_access_pipeline_bits parameter which is set by the `gem_axi_access_pipeline_bits DEFINE or is zero if the FIFO interface is configured. | RO | 0x4
15:12 | axi_tx_descr_rd_buff_bits | Takes the value of the edma_axi_tx_descr_rd_buff_bits parameter which is set by the `gem_axi_tx_descr_rd_buff_bits DEFINE or is zero if the FIFO interface is configured. | RO | 0x1
11:8 | axi_rx_descr_rd_buff_bits | Takes the value of the edma_axi_rx_descr_rd_buff_bits parameter which is set by the `gem_axi_rx_descr_rd_buff_bits DEFINE or is zero if the FIFO interface is configured. | RO | 0x1
7:4 | axi_tx_descr_wr_buff_bits | Takes the value of the edma_axi_tx_descr_wr_buff_bits parameter which is set by the `gem_axi_tx_descr_wr_buff_bits DEFINE or is zero if the FIFO interface is configured. | RO | 0x1
3:0 | axi_rx_descr_wr_buff_bits | Takes the value of the edma_axi_rx_descr_wr_buff_bits parameter which is set by the `gem_axi_rx_descr_wr_buff_bits DEFINE or is zero if the FIFO interface is configured. | RO | 0x1

### gem_gxlmicrosemi : emac_designcfg_debug11

Address offset | 0x12A8
Description | Design Configuration Register 11
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7 | asf_prot_tx_sched | Takes the value of the edma_asf_asf_prot_tx_sched parameter which is set by the `gem_asf_prot_tx_sched DEFINE. | RO | 0
6 | asf_host_par | Takes the value of the edma_asf_host_par parameter which is set by the `gem_asf_host_par DEFINE. | RO | 0
5 | asf_trans_to_prot | Takes the value of the edma_asf_trans_to_prot parameter which is set by the `gem_asf_enable DEFINE. | RO | 0
4 | asf_integrity_prot | Takes the value of the edma_asf_integrity_prot parameter which is set by the `gem_asf_enable DEFINE. | RO | 0
3 | protect_tsu | akes the value of the edma_asf_prot_tsu parameter which is set by the `gem_asf_prot_tsu DEFINE or is zero if no TSU is present. | RO | 0
2 | csr_protection | Takes the value of the edma_asf_csr_prot parameter which is set by the `gem_asf_enable DEFINE. | RO | 0
1 | dap_protection | Takes the value of the edma_asf_dap_prot parameter which is set by the `gem_asf_enable DEFINE. | RO | 0
0 | ecc_sram | Takes the value of the edma_asf_ecc_sram parameter which is set by the `gem_asf_ecc_sram DEFINE. | RO | 0

### gem_gxlmicrosemi : emac_designcfg_debug12

Address offset | 0x12AC
Description | Design Configuration Register 12
Type | RO

Bits | Field Name | Description | Type | Reset
31:26 | reserved_31_26 | Reserved, read as 0, ignored on write. | RO | 0x00
25 | gem_has_802p3_br | A value of one indicates that gem_has_802p3_br is defined. If defined the configuration contains both an express MAC (eMAC) and a pre-emptable MAC (pMAC) to allow 802.3br frame pre-emption. | RO | 1
24:21 | emac_tx_pbuf_addr | Takes the value of the `gem_emac_tx_pbuf_addr DEFINE - this defines the size of the transmit SRAM for express MAC (eMAC) when 802.3br is configured - will be zero if emac_tx_pbuf_address is decimal 16 | RO | 0x9
20:17 | emac_rx_pbuf_addr | Takes the value of the `gem_emac_rx_pbuf_addr DEFINE - this defines the size of the receive SRAM for express MAC (eMAC) when 802.3br is configured - will be zero if emac_tx_pbuf_address is decimal 16 | RO | 0x9
16 | gem_has_cb | Indicates whether gem has 802.1CB/FRER configured | RO | 1
15:8 | gem_cb_history_len | Takes the value of the `gem_seq_history_len DEFINE or 0x01 if undefined. | RO | 0x08
7:0 | gem_num_cb_streams | Set to 2 for the eMAC (express MAC) | RO | 0x02

### gem_gxlmicrosemi : emac_axi_qos_cfg

Address offset | 0x12E0
Description | eMAC AXI Quality of Service register. This register is only present if AXI is configured. This register contains 8-bits to control driving of the ARQOS and AWQOS outputs (4-bits each). The lower four bits are for data accesses and the upper four bits are for descriptor accesses.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:4 | emac_descr_qos | Determines what value to drive to the ARQOS and AWQOS outputs (4-bits each) for eMAC descriptor accesses. | RW | 0x0
3:0 | emac_data_qos | Determines what value to drive to the ARQOS and AWQOS outputs (4-bits each) for eMAC data accesses. | RW | 0x0

### gem_gxlmicrosemi : emac_cbs_control

Address offset | 0x14BC
Description | The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not exceed the portTransmitRate which is dependent on the speed of operation, eg, portTransmitRate: 1Gb/s = 32'h07735940 (125 Mbytes/s), 100Mb/sec = 32'h017D7840 (25 Mnibbles/s), 10Mb/sec = 32'h002625A0 (2.5 Mnibbles/s). If 50% of bandwidth was to be allocated to a particular queue in 1Gb/sec mode then the IdleSlope value for that queue would be calculated as 32'h07735940/2. Note: Credit-Based Shaping should be disabled prior to updating the IdleSlope values. As another example, for a 1722 audio packet with a payload of 6 samples per channel, the packet size would be: 7 (preamble) + 1 (SFD) + 50 (packet header) + 6x4x2(payload) + 4 (CRC) = 110 bytes. For a rate of 8000 packets per second, the desired rate would 110 x 8000 bytes per second, so the programmed idleSlope value would be 880000 for a 1Gb/s connection, or 1760000 for a 100Mb/s or 10Mbs connection. See Figure 6.3 in the IEEE 1722 standard. In practice, the actual transmission rate will be vary slightly from that calculated. In this case, the idleSlope value should be recalibrated based on the variance between the measured and expected rate, and in this case very accurate transmission rates can be achieved. (The idleslope value is scaled by 2.5 in 2.5G operation and so the port transmit rate is the same for 1G and 2.5G.)
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved_31_1 | Reserved, read as 0, ignored on write. | RO | 0x0000 0000
0 | cbs_enable_queue_a | Enable Credit-Based Shaping on the highest priority queue (queue A). Write 1 to enable | RW | 0

### gem_gxlmicrosemi : emac_cbs_idleslope_q_a

Address offset | 0x14C0
Description | Queue A is the highest priority queue. This is the highest indexed active queue, e.g. For a system with Q0 to Q7, this would be Q7 if all queues were active.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | idleslope_a | IdleSlope value for queue A in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_cbs_idleslope_q_b

Address offset | 0x14C4
Description | Queue B is the 2nd highest priority queue. This is the second highest indexed active queue, e.g. For a system with Q0 to Q7, this would be Q6 if all queues were active.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | idleslope_b | IdleSlope value for queue B in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_upper_tx_q_base_addr

Address offset | 0x14C8
Description | Upper 32 bits of transmit buffer descriptor queue base address.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | upper_tx_q_base_addr | Upper 32 bits of transmit buffer descriptor queue base address. Used when 64 bit addressing is enabled. (In releases earlier to 1p06f2 this register also affected the receive descriptor queue.) | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_tx_bd_control

Address offset | 0x14CC
Description | Transmit buffer descriptor control register - this register determines which transmit frames, with time stamps reported in the buffer descriptor status field in extended buffer descriptor mode, set bit 23 in transmit buffer descriptor word 1.
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved_31_6 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
5:4 | tx_bd_ts_mode | Transmit Descriptor Timestamp Insertion mode - bit 23 in transmit buffer descriptor word 1 when extended buffer descriptor mode is enabled,, : 00: Bit 23 always zero,, : 01: Bit 23 high for PTP Event Frames only,, : 10: Bit 23 high for all PTP Frames only,, : 11: Bit 23 always high | RW | 0x0
3:0 | reserved_3_0 | Reserved, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : emac_rx_bd_control

Address offset | 0x14D0
Description | Receive buffer descriptor control register - this register determines which receive frames have time stamps reported in the buffer descriptor status field
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved_31_6 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
5:4 | rx_bd_ts_mode | Receive Descriptor Timestamp Insertion mode,, : 00: TS insertion disable,, : 01: TS inserted for PTP Event Frames only,, : 10: TS inserted for All PTP Frames only,, : 11: TS insertion for All Frames | RW | 0x0
3:0 | reserved_3_0 | Reserved, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : emac_upper_rx_q_base_addr

Address offset | 0x14D4
Description | Upper 32 bits of receive buffer descriptor queue base address.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | upper_rx_q_base_addr | Upper 32 bits of receive buffer descriptor queue base address. Used when 64 bit addressing is enabled. | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_wd_counter

Address offset | 0x14EC
Description | Hidden control register - do not alter
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved_31_4 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
3:0 | rx_bd_reread_timer | Controls counter used to retry receive descriptor reads (retries may occur if there was a resource error and there are frames waiting in the internal SRAM buffer to be off-loaded to host memory) | RW | 0x7

### gem_gxlmicrosemi : emac_wd_axi_tx_full_thresh0

Address offset | 0x14F8
Description | Hidden control register - do not alter
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | axi_tx_full_adj_0 | AXI single port SRAM fine tuning | RW | 0x06
15:8 | reserved_15_8 | Reserved, read as 0, ignored on write. | RO | 0x00
7:0 | axi_tx_full_adj_1 | AXI single port SRAM fine tuning | RW | 0x08

### gem_gxlmicrosemi : emac_wd_axi_tx_full_thresh1

Address offset | 0x14FC
Description | Hidden control register - do not alter
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | axi_tx_full_adj_2 | AXI single port SRAM fine tuning | RW | 0x00
15:8 | reserved_15_8 | Reserved, read as 0, ignored on write. | RO | 0x00
7:0 | axi_tx_full_adj_3 | AXI single port SRAM fine tuning | RW | 0x00

### gem_gxlmicrosemi : emac_screening_type_1_register

Address offset | 0x1500
Description | Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TC field (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. The bit mappings for these registers are as follows:
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved_31 | Reserved, read as 0, ignored on write. | RO | 0
30 | drop_on_match | When set, if the frame matches it will be completely dropped. In this case the queue number is don't care. | RW | 0
29 | udp_port_match_enable | UDP port match enable | RW | 0
28 | dstc_enable | DS/TC Enable | RW | 0
27:12 | udp_port_match | UDP Port Match | RW | 0x0000
11:4 | dstc_match | DS/TC Match | RW | 0x00
3:0 | queue_number | Queue Number (0 to 15) | RW | 0x0

### gem_gxlmicrosemi : emac_screening_type_2_register_0

Address offset | 0x1540
Description | Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:
Type | RW

Bits | Field Name | Description | Type | Reset
31 | drop_on_match | When set, if the frame matches it will be completely dropped. In this case the queue number is don't care. | RW | 0
30 | compare_c_enable | Compare C Enable | RW | 0
29:25 | compare_c | Compare C - Index to screener type 2 Compare register | RW | 0x00
24 | compare_b_enable | Compare B Enable | RW | 0
23:19 | compare_b | Compare B - Index to screener type 2 Compare register | RW | 0x00
18 | compare_a_enable | Compare A Enable | RW | 0
17:13 | compare_a | Compare A - Index to screener type 2 Compare register | RW | 0x00
12 | ethertype_enable | EtherType Enable | RW | 0
11:9 | ethertype_reg_index | Index to screener type 2 EtherType register | RW | 0x0
8 | vlan_enable | VLAN Enable | RW | 0
7 | reserved_7 | Reserved and implemented as RW | RW | 0
6:4 | vlan_priority | VLAN Priority | RW | 0x0
3:0 | queue_number | Queue Number (0 to 15) | RW | 0x0

### gem_gxlmicrosemi : emac_screening_type_2_register_1

Address offset | 0x1544
Description | Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:, :1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself., :2) An enabled EtherType., :3) An enabled Field Compare A. , :4) An enabled Field Compare B. , :5) An enabled Field Compare C. , :All enabled comparisons are ANDed together to form the overall type 2 screener match. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C. The bit mappings for these registers are as follows:
Type | RW

Bits | Field Name | Description | Type | Reset
31 | drop_on_match | When set, if the frame matches it will be completely dropped. In this case the queue number is don't care. | RW | 0
30 | compare_c_enable | Compare C Enable | RW | 0
29:25 | compare_c | Compare C - Index to screener type 2 Compare register | RW | 0x00
24 | compare_b_enable | Compare B Enable | RW | 0
23:19 | compare_b | Compare B - Index to screener type 2 Compare register | RW | 0x00
18 | compare_a_enable | Compare A Enable | RW | 0
17:13 | compare_a | Compare A - Index to screener type 2 Compare register | RW | 0x00
12 | ethertype_enable | EtherType Enable | RW | 0
11:9 | ethertype_reg_index | Index to screener type 2 EtherType register | RW | 0x0
8 | vlan_enable | VLAN Enable | RW | 0
7 | reserved_7 | Reserved and implemented as RW | RW | 0
6:4 | vlan_priority | VLAN Priority | RW | 0x0
3:0 | queue_number | Queue Number (0 to 15) | RW | 0x0

### gem_gxlmicrosemi : emac_tx_sched_ctrl

Address offset | 0x1580
Description | This register controls the transmit scheduling algorithm the user can select for the eMAC.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved_31_2 | Reserved, read as 0, ignored on write. | RO | 0x0000 0000
1:0 | tx_sched | Transmit scheduling algorithm., : 00 : Normal Priority, : 01 : CBS Enabled only valid if CBS capability selected., : 10 : DWRR Enabled, : 11 : ETS Enabled | RW | 0x0

### gem_gxlmicrosemi : emac_bw_rate_limit

Address offset | 0x1590
Description | This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for the eMAC.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:0 | emac_dwrr_ets_weight | DWRR Weighting / ETS Bandwidth Allocation for the eMAC | RW | 0x00

### gem_gxlmicrosemi : emac_tx_q_seg_alloc_q_lower

Address offset | 0x15A0
Description | There should be no need to change this register for the eMAC.
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved_31_3 | Reserved, read as 0, ignored on write. | RO | 0x0000 0000
2:0 | segment_alloc | Number of segments allocated. This should be entered as a log 2, for example entering a value of 2 would grant 4 segments. A maximum of 16 segments can be granted. | RW | 0x0

### gem_gxlmicrosemi : emac_type2_compare_0_word_0

Address offset | 0x1700
Description | Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | compare_value | 2 byte Compare Value., :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3., :, :If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1., : | RW | 0x0000
15:0 | mask_value | These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. , :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. , :, :If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. A value of zero in a mask bit masks the corresponding data bit, a value of 1 enables the comparison. | RW | 0x0000

### gem_gxlmicrosemi : emac_type2_compare_0_word_1

Address offset | 0x1704
Description | Type2 Compare Word 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | compare_vlan_id | If set bits 9, 8 and 6:0 must be 0 and bit 7 of compare_offset is used as follows:, :0 Compare C-TAG VID (VLAN has EtherType of 0x8100), :1 Compare S-TAG VID comparison (VLAN has EtherType of the value in the stacked VLAN register at 0x00C0), :Note the byte order is such that if 81 00 00 20 is received to indicate a C-TAG frame with VID 020 0x00200FFF would be written to the compare register. So in the special case of VLAN comparison the last byte received is the least significant byte in the compare register | RW | 0
9 | disable_mask | This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value., :1 - 4-byte compare value, :0 - 2-byte compare, 2-byte mask | RW | 0
8:7 | compare_offset | Compare byte offset., :00 : Offset from beginning of the frame., :01 : Offset from byte after Ether Type., :10 : Offset from byte following end of IP header., :11 : Offset from byte following end of TCP/UDP header | RW | 0x0
6:0 | offset_value | Offset value in bytes | RW | 0x00

### gem_gxlmicrosemi : emac_type2_compare_1_word_0

Address offset | 0x1708
Description | Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | compare_value | 2 byte Compare Value., :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3., :, :If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1., : | RW | 0x0000
15:0 | mask_value | These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. , :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. , :, :If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. A value of zero in a mask bit masks the corresponding data bit, a value of 1 enables the comparison. | RW | 0x0000

### gem_gxlmicrosemi : emac_type2_compare_1_word_1

Address offset | 0x170C
Description | Type2 Compare Word 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | compare_vlan_id | If set bits 9, 8 and 6:0 must be 0 and bit 7 of compare_offset is used as follows:, :0 Compare C-TAG VID (VLAN has EtherType of 0x8100), :1 Compare S-TAG VID comparison (VLAN has EtherType of the value in the stacked VLAN register at 0x00C0), :Note the byte order is such that if 81 00 00 20 is received to indicate a C-TAG frame with VID 020 0x00200FFF would be written to the compare register. So in the special case of VLAN comparison the last byte received is the least significant byte in the compare register | RW | 0
9 | disable_mask | This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value., :1 - 4-byte compare value, :0 - 2-byte compare, 2-byte mask | RW | 0
8:7 | compare_offset | Compare byte offset., :00 : Offset from beginning of the frame., :01 : Offset from byte after Ether Type., :10 : Offset from byte following end of IP header., :11 : Offset from byte following end of TCP/UDP header | RW | 0x0
6:0 | offset_value | Offset value in bytes | RW | 0x00

### gem_gxlmicrosemi : emac_type2_compare_2_word_0

Address offset | 0x1710
Description | Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | compare_value | 2 byte Compare Value., :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3., :, :If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1., : | RW | 0x0000
15:0 | mask_value | These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. , :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. , :, :If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. A value of zero in a mask bit masks the corresponding data bit, a value of 1 enables the comparison. | RW | 0x0000

### gem_gxlmicrosemi : emac_type2_compare_2_word_1

Address offset | 0x1714
Description | Type2 Compare Word 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | compare_vlan_id | If set bits 9, 8 and 6:0 must be 0 and bit 7 of compare_offset is used as follows:, :0 Compare C-TAG VID (VLAN has EtherType of 0x8100), :1 Compare S-TAG VID comparison (VLAN has EtherType of the value in the stacked VLAN register at 0x00C0), :Note the byte order is such that if 81 00 00 20 is received to indicate a C-TAG frame with VID 020 0x00200FFF would be written to the compare register. So in the special case of VLAN comparison the last byte received is the least significant byte in the compare register | RW | 0
9 | disable_mask | This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value., :1 - 4-byte compare value, :0 - 2-byte compare, 2-byte mask | RW | 0
8:7 | compare_offset | Compare byte offset., :00 : Offset from beginning of the frame., :01 : Offset from byte after Ether Type., :10 : Offset from byte following end of IP header., :11 : Offset from byte following end of TCP/UDP header | RW | 0x0
6:0 | offset_value | Offset value in bytes | RW | 0x00

### gem_gxlmicrosemi : emac_type2_compare_3_word_0

Address offset | 0x1718
Description | Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | compare_value | 2 byte Compare Value., :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3., :, :If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1., : | RW | 0x0000
15:0 | mask_value | These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. , :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. , :, :If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. A value of zero in a mask bit masks the corresponding data bit, a value of 1 enables the comparison. | RW | 0x0000

### gem_gxlmicrosemi : emac_type2_compare_3_word_1

Address offset | 0x171C
Description | Type2 Compare Word 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | compare_vlan_id | If set bits 9, 8 and 6:0 must be 0 and bit 7 of compare_offset is used as follows:, :0 Compare C-TAG VID (VLAN has EtherType of 0x8100), :1 Compare S-TAG VID comparison (VLAN has EtherType of the value in the stacked VLAN register at 0x00C0), :Note the byte order is such that if 81 00 00 20 is received to indicate a C-TAG frame with VID 020 0x00200FFF would be written to the compare register. So in the special case of VLAN comparison the last byte received is the least significant byte in the compare register | RW | 0
9 | disable_mask | This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value., :1 - 4-byte compare value, :0 - 2-byte compare, 2-byte mask | RW | 0
8:7 | compare_offset | Compare byte offset., :00 : Offset from beginning of the frame., :01 : Offset from byte after Ether Type., :10 : Offset from byte following end of IP header., :11 : Offset from byte following end of TCP/UDP header | RW | 0x0
6:0 | offset_value | Offset value in bytes | RW | 0x00

### gem_gxlmicrosemi : emac_type2_compare_4_word_0

Address offset | 0x1720
Description | Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | compare_value | 2 byte Compare Value., :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3., :, :If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1., : | RW | 0x0000
15:0 | mask_value | These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. , :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. , :, :If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. A value of zero in a mask bit masks the corresponding data bit, a value of 1 enables the comparison. | RW | 0x0000

### gem_gxlmicrosemi : emac_type2_compare_4_word_1

Address offset | 0x1724
Description | Type2 Compare Word 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | compare_vlan_id | If set bits 9, 8 and 6:0 must be 0 and bit 7 of compare_offset is used as follows:, :0 Compare C-TAG VID (VLAN has EtherType of 0x8100), :1 Compare S-TAG VID comparison (VLAN has EtherType of the value in the stacked VLAN register at 0x00C0), :Note the byte order is such that if 81 00 00 20 is received to indicate a C-TAG frame with VID 020 0x00200FFF would be written to the compare register. So in the special case of VLAN comparison the last byte received is the least significant byte in the compare register | RW | 0
9 | disable_mask | This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value., :1 - 4-byte compare value, :0 - 2-byte compare, 2-byte mask | RW | 0
8:7 | compare_offset | Compare byte offset., :00 : Offset from beginning of the frame., :01 : Offset from byte after Ether Type., :10 : Offset from byte following end of IP header., :11 : Offset from byte following end of TCP/UDP header | RW | 0x0
6:0 | offset_value | Offset value in bytes | RW | 0x00

### gem_gxlmicrosemi : emac_type2_compare_5_word_0

Address offset | 0x1728
Description | Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | compare_value | 2 byte Compare Value., :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3., :, :If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1., : | RW | 0x0000
15:0 | mask_value | These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. , :, :If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. , :, :If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. A value of zero in a mask bit masks the corresponding data bit, a value of 1 enables the comparison. | RW | 0x0000

### gem_gxlmicrosemi : emac_type2_compare_5_word_1

Address offset | 0x172C
Description | Type2 Compare Word 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved_31_11 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
10 | compare_vlan_id | If set bits 9, 8 and 6:0 must be 0 and bit 7 of compare_offset is used as follows:, :0 Compare C-TAG VID (VLAN has EtherType of 0x8100), :1 Compare S-TAG VID comparison (VLAN has EtherType of the value in the stacked VLAN register at 0x00C0), :Note the byte order is such that if 81 00 00 20 is received to indicate a C-TAG frame with VID 020 0x00200FFF would be written to the compare register. So in the special case of VLAN comparison the last byte received is the least significant byte in the compare register | RW | 0
9 | disable_mask | This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value., :1 - 4-byte compare value, :0 - 2-byte compare, 2-byte mask | RW | 0
8:7 | compare_offset | Compare byte offset., :00 : Offset from beginning of the frame., :01 : Offset from byte after Ether Type., :10 : Offset from byte following end of IP header., :11 : Offset from byte following end of TCP/UDP header | RW | 0x0
6:0 | offset_value | Offset value in bytes | RW | 0x00

### gem_gxlmicrosemi : emac_enst_start_time

Address offset | 0x1800
Description | This register sets the absolute time at which queue q0 starts EnST transmit scheduling
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | start_time_sec | Bits 31:30 of the start time (seconds field), for q0 | RW | 0x0
29:0 | start_time_nsec | Bits 29:0 of the start time (nanoseconds field), for q0 | RW | 0x0000 0000

### gem_gxlmicrosemi : emac_enst_on_time

Address offset | 0x1820
Description | This register sets the time period for which queue q0 is to be open, (on_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| : on_time = on_time_nsec/8, : ||100Mbps|| : on_time = on_time_nsec/80, : ||10Mbps|| : on_time = on_time_nsec/800
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | on_time | on_time, for q0 | RW | 0x1 FFFF

### gem_gxlmicrosemi : emac_enst_off_time

Address offset | 0x1840
Description | This register sets the time period for which queue q0 is to be blocked, (off_time_nsec), this register has to be written according to the speed mode as:, : ||1Gbps or 2.5Gbps|| => off_time = off_time_nsec/8, : ||100Mbps|| => off_time = off_time_nsec/80, : ||10Mbps|| => off_time = off_time_nsec/800
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | reserved_31_17 | Reserved, read as 0, ignored on write. | RO | 0x0000
16:0 | off_time | Off_time, for q0 | RW | 0x0 0000

### gem_gxlmicrosemi : emac_enst_control

Address offset | 0x1880
Description | Enhancement for Scheduled Traffic control register. EnST scheduling can only be applied to a maximum number of 8 queues. If 802.3br operation has been configured and both an eMAC and pMAC are present then the eMAC only supports a single queue and EnST is enabled on the eMAC by writing to bit 0 of emac_enst_control.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved_31_8 | Reserved, read as 0, ignored on write. | RO | 0x00 0000
7:4 | reserved_7_4 | Reserved. | RW | 0x0
3 | enst_enable_q3 | Set to enable enhanced scheduler traffic (ENST), for q3 | RW | 0
2 | enst_enable_q2 | Set to enable enhanced scheduler traffic (ENST), for q2 | RW | 0
1 | enst_enable_q1 | Set to enable enhanced scheduler traffic (ENST), for q1 | RW | 0
0 | enst_enable_q0 | Set to enable enhanced scheduler traffic (ENST), for q0 | RW | 0

### gem_gxlmicrosemi : emac_frer_timeout

Address offset | 0x18A0
Description | FRER timeout register. This determines when the sequence recovery reset timers are reset and is used by all of the configured CB streams. It is programmed as a count of 8192 rx_clk periods. 8192 rx_clk periods is 65.536 microseconds at gigabit speeds and 327.68 microseconds at 100M speeds, this allows a max timeout value of about 4 seconds at gigabit speeds - for test purposes if bit 12 (retry_test) is set in the network configuration register at 0x004 then the timeout value just becomes a count of rx_clk periods (ie a speed-up of 8192 in the time-out process).
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | timeout | Count of 8192 rx_clk periods. | RW | 0x0000

### gem_gxlmicrosemi : emac_frer_red_tag

Address offset | 0x18A4
Description | FRER redundancy tag register. This defines the Ethertype used to identify the R-TAG (redundancy tag) and contains a control bit to enable stripping of the R-TAG from received frames. IEEE 802.1CB has defined the value of this Ethertype to be 0xF1C1. Whether or not a particular stream uses the redundancy tag to locate the sequence number is determined by bit 28 in that streams control register.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | strip_r_tag | If set the redundancy tag is stripped from received frames. If this bit is set then the receive octet counters reflect post deletion frame size so the FRER functionality is transparent to higher level management if the stripping function is enabled. If the statistics counters need to reflect the actual number of octets received, then the stripping functionality should be disabled. | RW | 0
30 | six_byte_tag | Draft 2.4 and earlier drafts of the 802.1CB standard defined a four-byte redundancy tag. Drafts 2.5 and later specified a six-byte tag. Releases 1p10 and 1p11 were implemented in accordance with draft 2.4 of the standard. Set this bit to zero to inter-operate with implementations that use a four-byte tag. | RW | 1
29:16 | reserved_29_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:0 | redundancy_tag | Ethertype value used to identify the redundancy tag (R-TAG). | RW | 0xF1C1

### gem_gxlmicrosemi : emac_frer_control_1_a

Address offset | 0x18C0
Description | FRER control register A
Type | RW

Bits | Field Name | Description | Type | Reset
31 | en_elimination | Enable 802.1CB elimination of received frames | RW | 0
30 | en_vector_rec_alg | Enable 802.1CB vector recovery algorithm, : 0 enables the match recovery algorithm, : 1 enables the vector recovery algorithm, :This bit should only be changed when bit 31 en_elimination is low | RW | 0
29 | en_seqrecrst_timer | Enable 802.1CB sequence recovery reset timer - this bit may be changed when bit 31 en_elimination is low | RW | 0
28 | use_r_tag | Set to one to use redundancy tag to identify sequence number otherwise use offset value to identify bottom of sequence number - this bit should only be changed when bit 31 en_elimination is low | RW | 0
27:17 | reserved_27_17 | Reserved, read as 0, ignored on write. | RO | 0x000
16:8 | offset_value | Offset value in bytes from the start packet delimiter to the most significant byte of the 802.1CB sequence number - 9 bits allow a maximum value of 511 - allowing a TCP sequence number to be used with IPv6 - this bit should only be changed when en_elimination is low | RW | 0x000
7:4 | member_stream_2 | Pointer to screener type 2 register used for member stream identification. The member stream 1 and 2 values may be programmed to identical values. - this bit should only be changed when en_elimination is low | RW | 0x0
3:0 | member_stream_1 | Pointer to screener type 2 register used for member stream identification. The member stream 1 and 2 values may be programmed to identical values. - this bit should only be changed when en_elimination is low | RW | 0x0

### gem_gxlmicrosemi : emac_frer_control_1_b

Address offset | 0x18C4
Description | FRER control register B. This register has default values where the sequence number length defaults to 16 and the vector recovery window defaults to the size of the history vector. It is not expected that the user will need to change these default values.
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | reserved_31_13 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
12:8 | seq_num_length | Number of significant bits of the 802.1CB sequence number. The value 0x00 or numbers greater than 16 bits are equivalent to 16, but the number written will still be read back if it is greater than 16. If a value of less than 16 is written, then the sequence recovery algorithm will only consider that number of LSBs of the sequence number. The minimum size of seq_num_length has to be such that 2^seq_num_len is at least 2xgem_seq_history_len otherwise the vector recovery algorithm will not work correctly - this bit should only be changed when en_elimination is low | RW | 0x00
7:6 | reserved_7_6 | Reserved, read as 0, ignored on write. | RO | 0x0
5:0 | seq_rec_window | Vector recovery window, defines the window size used by the vector recovery algorithm to determine whether to reject a packet. Six bits allow a window size of 63, for effective operation of FRER users should not write a value greater than the gem_seq_history_len configuration define, a value of zero means the entire history vector is used - this bit should only be changed when en_elimination is low. | RW | 0x00

### gem_gxlmicrosemi : emac_frer_statistics_1_a

Address offset | 0x18C8
Description | FRER statistics register A. This register is cleared on a read and does not roll over if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:26 | reserved_31_26 | Reserved, read as 0, ignored on write. | RO | 0x00
25:16 | vec_rec_rogue | Count of number of frames dropped by the vector recovery algorithm for being out of range | RO RtoClr | 0x000
15:10 | reserved_15_10 | Reserved, read as 0, ignored on write. | RO | 0x00
9:0 | latent_errors | Count of sequence numbers seen without a duplicate. The latent error count is updated when a frame is dropped from the history vector. So the update only happens after a new frame is received. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_frer_statistics_1_b

Address offset | 0x18CC
Description | FRER statistics register B. This register is cleared on a read and does not roll over if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | seqrst_count | Count of number of times the sequence recovery reset timer decrements to zero. | RO RtoClr | 0x00
15:10 | reserved_15_10 | Reserved, read as 0, ignored on write. | RO | 0x00
9:0 | out_of_order | Count of out of order sequence numbers received. Incremented when a frame is accepted but the sequence number is not +1 of the highest stored value. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_frer_control_2_a

Address offset | 0x18D0
Description | FRER control register A
Type | RW

Bits | Field Name | Description | Type | Reset
31 | en_elimination | Enable 802.1CB elimination of received frames | RW | 0
30 | en_vector_rec_alg | Enable 802.1CB vector recovery algorithm, : 0 enables the match recovery algorithm, : 1 enables the vector recovery algorithm, :This bit should only be changed when bit 31 en_elimination is low | RW | 0
29 | en_seqrecrst_timer | Enable 802.1CB sequence recovery reset timer - this bit may be changed when bit 31 en_elimination is low | RW | 0
28 | use_r_tag | Set to one to use redundancy tag to identify sequence number otherwise use offset value to identify bottom of sequence number - this bit should only be changed when bit 31 en_elimination is low | RW | 0
27:17 | reserved_27_17 | Reserved, read as 0, ignored on write. | RO | 0x000
16:8 | offset_value | Offset value in bytes from the start packet delimiter to the most significant byte of the 802.1CB sequence number - 9 bits allow a maximum value of 511 - allowing a TCP sequence number to be used with IPv6 - this bit should only be changed when en_elimination is low | RW | 0x000
7:4 | member_stream_2 | Pointer to screener type 2 register used for member stream identification. The member stream 1 and 2 values may be programmed to identical values. - this bit should only be changed when en_elimination is low | RW | 0x0
3:0 | member_stream_1 | Pointer to screener type 2 register used for member stream identification. The member stream 1 and 2 values may be programmed to identical values. - this bit should only be changed when en_elimination is low | RW | 0x0

### gem_gxlmicrosemi : emac_frer_control_2_b

Address offset | 0x18D4
Description | FRER control register B. This register has default values where the sequence number length defaults to 16 and the vector recovery window defaults to the size of the history vector. It is not expected that the user will need to change these default values.
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | reserved_31_13 | Reserved, read as 0, ignored on write. | RO | 0x0 0000
12:8 | seq_num_length | Number of significant bits of the 802.1CB sequence number. The value 0x00 or numbers greater than 16 bits are equivalent to 16, but the number written will still be read back if it is greater than 16. If a value of less than 16 is written, then the sequence recovery algorithm will only consider that number of LSBs of the sequence number. The minimum size of seq_num_length has to be such that 2^seq_num_len is at least 2xgem_seq_history_len otherwise the vector recovery algorithm will not work correctly - this bit should only be changed when en_elimination is low | RW | 0x00
7:6 | reserved_7_6 | Reserved, read as 0, ignored on write. | RO | 0x0
5:0 | seq_rec_window | Vector recovery window, defines the window size used by the vector recovery algorithm to determine whether to reject a packet. Six bits allow a window size of 63, for effective operation of FRER users should not write a value greater than the gem_seq_history_len configuration define, a value of zero means the entire history vector is used - this bit should only be changed when en_elimination is low. | RW | 0x00

### gem_gxlmicrosemi : emac_frer_statistics_2_a

Address offset | 0x18D8
Description | FRER statistics register A. This register is cleared on a read and does not roll over if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:26 | reserved_31_26 | Reserved, read as 0, ignored on write. | RO | 0x00
25:16 | vec_rec_rogue | Count of number of frames dropped by the vector recovery algorithm for being out of range | RO RtoClr | 0x000
15:10 | reserved_15_10 | Reserved, read as 0, ignored on write. | RO | 0x00
9:0 | latent_errors | Count of sequence numbers seen without a duplicate. The latent error count is updated when a frame is dropped from the history vector. So the update only happens after a new frame is received. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_frer_statistics_2_b

Address offset | 0x18DC
Description | FRER statistics register B. This register is cleared on a read and does not roll over if its maximum value is reached.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved_31_24 | Reserved, read as 0, ignored on write. | RO | 0x00
23:16 | seqrst_count | Count of number of times the sequence recovery reset timer decrements to zero. | RO RtoClr | 0x00
15:10 | reserved_15_10 | Reserved, read as 0, ignored on write. | RO | 0x00
9:0 | out_of_order | Count of out of order sequence numbers received. Incremented when a frame is accepted but the sequence number is not +1 of the highest stored value. | RO RtoClr | 0x000

### gem_gxlmicrosemi : emac_rx_q0_flush

Address offset | 0x1B00
Description | Receive Queue flush register. This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | max_val | This 16 bit vector is used when either bit 2 or 3 of this register is asserted. Refer to the description in those bits for details. | RW | 0x0000
15:4 | reserved_15_4 | Reserved, read as 0, ignored on write. | RO | 0x000
3 | limit_frame_size | When set max_val (bits 31:16) indicates the maximum frame-length in bytes that may be received. Frames exceeding this length will be dropped. This traffic policing function is relevant to the 802.1Qci standard which specifies stream filtering based on a maximum SDU (service data unit) size. | RW | 0
2 | limit_num_bytes | When set, the number of 128 byte chunks of data received for this queue and already stored in the SRAM awaiting DMA memory writes cannot exceed max_val (bits 31:16). | RW | 0
1 | drop_on_resource_err | When set, if a free DMA descriptor for this queue cannot be obtained (also referred to as lack of descriptor resource and occurs when the software either cannot free up descriptors quickly enough to meet the receive traffic rate or has deliberately decided not to free any descriptors), all new frames received on this queue will be automatically discarded. | RW | 0
0 | drop_all_frames | When set, all frames on this queue will be dropped. | RW | 0

### gem_gxlmicrosemi : emac_scr2_reg0_rate_limit

Address offset | 0x1B40
Description | Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | max_rate_val | This is the maximum number of bytes this screener is permitted to match in the programmed interval time. | RW | 0x0000
15:0 | interval_time | If during the interval time the total number of bytes of received frames matched by the screener exceeds max_rate_val then the current frame and frames subsequently matched will dropped until an interval time passes where max_rate_val is not exceeded. If this value is set to zero, then no rate limiting will be performed. The interval time is specified in units of 64 rx_clk periods. | RW | 0x0000

### gem_gxlmicrosemi : emac_scr2_reg1_rate_limit

Address offset | 0x1B44
Description | Screener type 2 maximum rate register. This register defines the maximum receive rate for the corresponding type 2 screener. This is a traffic policing function and is relevant to the 802.1Qci standard. If the maximum rate is exceeded all frames matched by the corresponding type 2 screener will be discarded until the receive rate falls below the specified value.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | max_rate_val | This is the maximum number of bytes this screener is permitted to match in the programmed interval time. | RW | 0x0000
15:0 | interval_time | If during the interval time the total number of bytes of received frames matched by the screener exceeds max_rate_val then the current frame and frames subsequently matched will dropped until an interval time passes where max_rate_val is not exceeded. If this value is set to zero, then no rate limiting will be performed. The interval time is specified in units of 64 rx_clk periods. | RW | 0x0000

### gem_gxlmicrosemi : emac_scr2_rate_status

Address offset | 0x1B80
Description | Screener rate limit exceeded status register. For each screener type 2 register configured a status bit will be set and cleared on read if the maximum receive rate is exceeded.
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved_31_16 | Reserved, read as 0, ignored on write. | RO | 0x0000
15:4 | reserved_15_4 | Reserved, read as 0, ignored on write. | RO | 0x000
3 | scr2_3_excess_rate | Set to 1 if screeners rate limiting mechanism has been triggered | RO RtoClr | 0
2 | scr2_2_excess_rate | Set to 1 if screeners rate limiting mechanism has been triggered | RO RtoClr | 0
1 | scr2_1_excess_rate | Set to 1 if screeners rate limiting mechanism has been triggered | RO RtoClr | 0
0 | scr2_0_excess_rate | Set to 1 if screeners rate limiting mechanism has been triggered | RO RtoClr | 0

### gem_gxlmicrosemi : emac_asf_int_status

Address offset | 0x1E00
Description | ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the asf_fatal or asf_nonfatal signal will be asserted. Writing to either raw or masked status registers, clear both registers. For test purposes, trigger signal interrupt event by writing to the ASF interrupt status test register.
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved_31_7 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
6 | reserved_6 | Reserved, read as 0, ignored on write. | RO | 0
5 | asf_protocol_err | Protocol error interrupt | RW W1toClr | 0
4 | asf_trans_to_err | Transaction timeouts error interrupt | RW W1toClr | 0
3 | reserved_3 | Reserved, read as 0, ignored on write. | RO | 0
2 | reserved_2 | Reserved, read as 0, ignored on write. | RO | 0
1:0 | reserved_1_0 | Reserved for SRAM ECC, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : emac_asf_int_raw_status

Address offset | 0x1E04
Description | ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the asf_fatal or asf_nonfatal signal will be asserted. Writing to either raw or masked status registers, clear both registers. For test purposes, trigger signal interrupt event by writing to the ASF interrupt status test register.
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved_31_7 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
6 | reserved_6 | Reserved, read as 0, ignored on write. | RO | 0
5 | asf_protocol_err | Protocol error interrupt | RW W1toClr | 0
4 | asf_trans_to_err | Transaction timeouts error interrupt | RW W1toClr | 0
3 | reserved_3 | Reserved, read as 0, ignored on write. | RO | 0
2 | reserved_2 | Reserved, read as 0, ignored on write. | RO | 0
1:0 | reserved_1_0 | Reserved for SRAM ECC, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : emac_asf_int_mask

Address offset | 0x1E08
Description | The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding interrupt.
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved_31_7 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
6 | reserved_6 | Reserved, read as 0, ignored on write. | RO | 0
5 | asf_protocol_err_mask | Mask bit for protocol error interrupt. | RW | 1
4 | asf_trans_to_err_mask | Mask bit for transaction timeouts error interrupt. | RW | 1
3 | reserved_3 | Reserved, read as 0, ignored on write. | RO | 0
2 | reserved_2 | Reserved, read as 0, ignored on write. | RO | 0
1:0 | reserved_1_0 | Reserved for SRAM ECC, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : emac_asf_int_test

Address offset | 0x1E0C
Description | The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly.
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved_31_7 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
6 | reserved_6 | Reserved, read as 0, ignored on write. | RO | 0
5 | asf_protocol_err_test | Test bit for protocol error interrupt. | WO | 0
4 | asf_trans_to_err_test | Test bit for transaction timeouts error interrupt. | WO | 0
3 | reserved_3 | Reserved, read as 0, ignored on write. | RO | 0
2 | reserved_2 | Reserved, read as 0, ignored on write. | RO | 0
1:0 | reserved_1_0 | Reserved for SRAM ECC, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : emac_asf_fatal_nonfatal_select

Address offset | 0x1E10
Description | The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then fatal interrupt (asf_int_fatal) will be triggered. Otherwise the non-fatal interrupt (asf_int_nonfatal) will be triggered.
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved_31_7 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
6 | reserved_6 | Reserved, read as 0, ignored on write. | RO | 0
5 | asf_protocol_err | Enable protocol error interrupt as fatal. | RW | 1
4 | asf_trans_to_err | Enable transaction timeouts error interrupt as fatal. | RW | 1
3 | reserved_3 | Reserved, read as 0, ignored on write. | RO | 0
2 | reserved_2 | Reserved, read as 0, ignored on write. | RO | 0
1:0 | reserved_1_0 | Reserved for SRAM ECC, read as 0, ignored on write. | RO | 0x0

### gem_gxlmicrosemi : emac_asf_trans_to_fault_mask

Address offset | 0x1E34
Description | Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset, all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source.
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved_31_5 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
4 | reserved_4 | Reserved, read as 0, ignored on write. | RO | 0
3 | dma_rx_to_mask | Mask register for DMA RX lockup detection. | RW | 1
2 | dma_tx_to_mask | Mask register for DMA TX lockup detection. | RW | 1
1 | mac_rx_to_mask | Mask register for MAC RX lockup detection. | RW | 1
0 | mac_tx_to_mask | Mask register for MAC TX lockup detection. | RW | 1

### gem_gxlmicrosemi : emac_asf_trans_to_fault_status

Address offset | 0x1E38
Description | Status register for transaction timeouts fault. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit.
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved_31_5 | Reserved, read as 0, ignored on write. | RO | 0x000 0000
4 | reserved_4 | Reserved, read as 0, ignored on write. | RO | 0
3 | dma_rx_to_status | Status bit for DMA RX lockup detection. | RW W1toClr | 0
2 | dma_tx_to_status | Status bit for DMA TX lockup detection. | RW W1toClr | 0
1 | mac_rx_to_status | Status bit for MAC RX lockup detection. | RW W1toClr | 0
0 | mac_tx_to_status | Status bit for MAC TX lockup detection. | RW W1toClr | 0

### gem_gxlmicrosemi : emac_asf_protocol_fault_mask

Address offset | 0x1E40
Description | Control register to mask out ASF Protocol faults from triggering interrupts. On reset, all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source.
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved_31_22 | Reserved, read as 0, ignored on write. | RO | 0x000
21 | rx_dma_pkt_flush_mask | Mask bit for RX packet was flushed from the DMA. | RW | 1
20 | rx_overflow_mask | Mask bit for DMA buffer overflow and packet was dropped. | RW | 1
19 | rx_hresp_err_mask | Mask bit for DMA hresp error (AHB only). | RW | 1
18 | tx_hresp_err_mask | Mask bit for DMA hresp error (AHB only). | RW | 1
17 | tx_buff_ex_mid_mask | Mask bit for Transmit buffers exhausted before end of packet. | RW | 1
16 | tx_underrun_mask | Mask bit for Transmit DMA underrun occurred. | RW | 1
15:9 | reserved_15_9 | Reserved, read as 0, ignored on write. | RO | 0x00
8 | tx_too_many_retries_mask | Mask bit for too many retry attempts after collision error (half duplex only). | RW | 1
7 | rx_udp_ck_err_mask | Mask bit for RX packet UDP checksum error. | RW | 1
6 | rx_tcp_ck_err_mask | Mask bit for RX packet TCP checksum error. | RW | 1
5 | rx_ip_ck_err_mask | Mask bit for RX packet IP checksum error. | RW | 1
4 | rx_length_err_mask | Mask bit for RX packet with length field error. | RW | 1
3 | rx_symbol_err_mask | Mask bit for RX packet with symbol errors. | RW | 1
2 | rx_long_err_mask | Mask bit for RX packet too long. | RW | 1
1 | rx_short_err_mask | Mask bit for RX packet too short. | RW | 1
0 | rx_crc_err_mask | Mask bit for RX packet with bad CRC. | RW | 1

### gem_gxlmicrosemi : emac_asf_protocol_fault_status

Address offset | 0x1E44
Description | Status register for protocol faults. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved_31_22 | Reserved, read as 0, ignored on write. | RO | 0x000
21 | rx_dma_pkt_flush_status | Status bit for RX packet was flushed from the DMA. | RW W1toClr | 0
20 | rx_overflow_status | Status bit for DMA buffer overflow and packet was dropped. | RW W1toClr | 0
19 | rx_hresp_err_status | Status bit for DMA hresp error (AHB only). | RW W1toClr | 0
18 | tx_hresp_err_status | Status bit for DMA hresp error (AHB only). | RW W1toClr | 0
17 | tx_buff_ex_mid_status | Status bit for Transmit buffers exhausted before end of packet. | RW W1toClr | 0
16 | tx_underrun_status | Status bit for Transmit DMA underrun occurred. | RW W1toClr | 0
15:9 | reserved_15_9 | Reserved, read as 0, ignored on write. | RO | 0x00
8 | tx_too_many_retries_status | Status bit for too many retry attempts after collision error (half duplex only). | RW W1toClr | 0
7 | rx_udp_ck_err_status | Status bit for RX packet UDP checksum error. | RW W1toClr | 0
6 | rx_tcp_ck_err_status | Status bit for RX packet TCP checksum error. | RW W1toClr | 0
5 | rx_ip_ck_err_status | Status bit for RX packet IP checksum error. | RW W1toClr | 0
4 | rx_length_err_status | Status bit for RX packet with length field error. | RW W1toClr | 0
3 | rx_symbol_err_status | Status bit for RX packet with symbol errors. | RW W1toClr | 0
2 | rx_long_err_status | Status bit for RX packet too long. | RW W1toClr | 0
1 | rx_short_err_status | Status bit for RX packet too short. | RW W1toClr | 0
0 | rx_crc_err_status | Status bit for RX packet with bad CRC. | RW W1toClr | 0

gem_gxlmicrosemi has no common memories.