## PF_PCIE_BRIDGE

This section provides information on the PF_PCIE_BRIDGE Module Instance. Each of the module registers is described below.

Return to mpfs250t_ioscb_memmap_dri

## PF_PCIE_BRIDGE Register Mapping Summary

### PF_PCIE_BRIDGE Common Register Mapping Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset
BRIDGE_VER | RO | 32 | 0x0251 1154 | 0x000 0000
BRIDGE_BUS | RO | 32 | 0x1188 5153 | 0x000 0004
BRIDGE_IMPL_IF | RO | 32 | 0x0000 032B | 0x000 0008
PCIE_IF_CONF | RO | 32 | 0x1144 0170 | 0x000 0010
PCIE_BASIC_CONF | RO | 32 | 0x0311 0307 | 0x000 0014
PCIE_BASIC_STATUS | RO | 32 | 0x2000 0100 | 0x000 0018
AXI_SLVL_CONF | RO | 32 | 0xBB00 2121 | 0x000 0024
AXI_MST0_CONF | RO | 32 | 0x1188 3442 | 0x000 0030
AXI_SLV0_CONF | RO | 32 | 0x4444 3443 | 0x000 0034
GEN_SETTINGS | RW | 32 | 0x0001 9300 | 0x000 0080
PCIE_CFGCTRL | RW | 32 | 0x0000 0000 | 0x000 0084
PCIE_PIPE_DW0 | RO | 32 | 0x2000 0000 | 0x000 0088
PCIE_PIPE_DW1 | RO | 32 | 0x0800 0001 | 0x000 008C
PCIE_VC_CRED_DW0 | RW | 32 | 0x1000 B818 | 0x000 0090
PCIE_VC_CRED_DW1 | RW | 32 | 0x0000 0001 | 0x000 0094
PCIE_PCI_IDS_DW0 | RW | 32 | 0x1100 1556 | 0x000 0098
PCIE_PCI_IDS_DW1 | RW | 32 | 0xFF00 0001 | 0x000 009C
PCIE_PCI_IDS_DW2 | RW | 32 | 0x1100 1556 | 0x000 00A0
PCIE_PCI_LPM | RW | 32 | 0xFE00 0000 | 0x000 00A4
PCIE_PCI_IRQ_DW0 | RW | 32 | 0x8000 0054 | 0x000 00A8
PCIE_PCI_IRQ_DW1 | RW | 32 | 0x0000 0000 | 0x000 00AC
PCIE_PCI_IRQ_DW2 | RW | 32 | 0x0000 0000 | 0x000 00B0
PCIE_PCI_IOV_DW0 | RW | 32 | 0x0000 000A | 0x000 00B4
PCIE_PCI_IOV_DW1 | RW | 32 | 0x0000 0000 | 0x000 00B8
PCIE_PEX_DEV | RW | 32 | 0x0000 0001 | 0x000 00C0
PCIE_PEX_DEV2 | RW | 32 | 0x0000 081F | 0x000 00C4
PCIE_PEX_LINK | RW | 32 | 0x0100 1C00 | 0x000 00C8
PCIE_PEX_SLOT | RO | 32 | 0x0000 007F | 0x000 00CC
PCIE_PEX_ROOT_VC | RW | 32 | 0x0000 0001 | 0x000 00D0
PCIE_PEX_SPC | RW | 32 | 0x8000 5000 | 0x000 00D4
PCIE_PEX_SPC2 | RW | 32 | 0x000C 6006 | 0x000 00D8
PCIE_PEX_NFTS | RW | 32 | 0x0020 2020 | 0x000 00DC
PCIE_PEX_L1SS | RO | 32 | 0x0028 0A1D | 0x000 00E0
PCIE_BAR_01_DW0 | RW | 32 | 0xFFFF F00C | 0x000 00E4
PCIE_BAR_01_DW1 | RW | 32 | 0xFFFF FFFF | 0x000 00E8
PCIE_BAR_23_DW0 | RW | 32 | 0xFFFF E00C | 0x000 00EC
PCIE_BAR_23_DW1 | RW | 32 | 0xFFFF FFFF | 0x000 00F0
PCIE_BAR_45_DW0 | RW | 32 | 0x0000 0000 | 0x000 00F4
PCIE_BAR_45_DW1 | RW | 32 | 0x0000 0000 | 0x000 00F8
PCIE_BAR_WIN | RW | 32 | 0x0000 0000 | 0x000 00FC
PCIE_EQ_PRESET_DW0 | RW | 32 | 0x0000 0000 | 0x000 0100
PCIE_EQ_PRESET_DW1 | RW | 32 | 0x0000 0000 | 0x000 0104
PCIE_EQ_PRESET_DW2 | RW | 32 | 0x0000 0000 | 0x000 0108
PCIE_EQ_PRESET_DW3 | RW | 32 | 0x0000 0000 | 0x000 010C
PCIE_EQ_PRESET_DW4 | RW | 32 | 0x0000 0000 | 0x000 0110
PCIE_EQ_PRESET_DW5 | RW | 32 | 0x0000 0000 | 0x000 0114
PCIE_EQ_PRESET_DW6 | RW | 32 | 0x0000 0000 | 0x000 0118
PCIE_EQ_PRESET_DW7 | RW | 32 | 0x0000 0000 | 0x000 011C
PCIE_SRIOV_DW0 | RO | 32 | 0x0000 0000 | 0x000 0120
PCIE_SRIOV_DW1 | RO | 32 | 0x0000 0000 | 0x000 0124
PCIE_SRIOV_DW2 | RO | 32 | 0x0000 0000 | 0x000 0128
PCIE_SRIOV_DW3 | RO | 32 | 0x0000 0000 | 0x000 012C
PCIE_SRIOV_DW4 | RO | 32 | 0x0000 0000 | 0x000 0130
PCIE_SRIOV_DW5 | RO | 32 | 0x0000 0000 | 0x000 0134
PCIE_SRIOV_DW6 | RO | 32 | 0x0000 0000 | 0x000 0138
PCIE_SRIOV_DW7 | RO | 32 | 0x0000 0000 | 0x000 013C
PCIE_CFGNUM | RO | 32 | 0x0000 0000 | 0x000 0140
PM_CONF_DW0 | RW | 32 | 0x0000 0000 | 0x000 0174
PM_CONF_DW1 | RW | 32 | 0x0000 0000 | 0x000 0178
PM_CONF_DW2 | RW | 32 | 0x0000 0000 | 0x000 017C
IMASK_LOCAL | RW | 32 | 0x0000 0000 | 0x000 0180
ISTATUS_LOCAL | RW | 32 | 0x0000 0000 | 0x000 0184
IMASK_HOST | RW | 32 | 0x0000 0000 | 0x000 0188
ISTATUS_HOST | RW | 32 | 0x0000 0000 | 0x000 018C
IMSI_ADDR | RO | 32 | 0x0000 0190 | 0x000 0190
ISTATUS_MSI | RW | 32 | 0x0000 0000 | 0x000 0194
ICMD_PM | RW | 32 | 0x0000 0000 | 0x000 0198
ISTATUS_PM | RO | 32 | 0x0000 0000 | 0x000 019C
ATS_PRI_REPORT | RW | 32 | 0x0000 0000 | 0x000 01A0
LTR_VALUES | RW | 32 | 0x0000 0000 | 0x000 01A4
ISTATUS_DMA0 | RO | 32 | 0x0000 0000 | 0x000 01B0
ISTATUS_DMA1 | RO | 32 | 0x0000 0000 | 0x000 01B4
ISTATUS_P_ADT_WIN0 | RO | 32 | 0x0000 0000 | 0x000 01D8
ISTATUS_P_ADT_WIN1 | RO | 32 | 0x0000 0000 | 0x000 01DC
ISTATUS_A_ADT_SLV0 | RO | 32 | 0x0000 0000 | 0x000 01E0
ISTATUS_A_ADT_SLV1 | RO | 32 | 0x0000 0000 | 0x000 01E4
ISTATUS_A_ADT_SLV2 | RO | 32 | 0x0000 0000 | 0x000 01E8
ISTATUS_A_ADT_SLV3 | RO | 32 | 0x0000 0000 | 0x000 01EC
ROUTING_RULES_R_DW0 | RO | 32 | 0x000B 0011 | 0x000 0200
ROUTING_RULES_R_DW1 | RO | 32 | 0x0000 0015 | 0x000 0204
ROUTING_RULES_R_DW2 | RO | 32 | 0x0000 0000 | 0x000 0208
ROUTING_RULES_R_DW3 | RO | 32 | 0x0000 0000 | 0x000 020C
ROUTING_RULES_R_DW4 | RO | 32 | 0x000E 0011 | 0x000 0210
ROUTING_RULES_R_DW5 | RO | 32 | 0x0000 0000 | 0x000 0214
ROUTING_RULES_R_DW6 | RO | 32 | 0x0000 0000 | 0x000 0218
ROUTING_RULES_R_DW7 | RO | 32 | 0x0000 0000 | 0x000 021C
ROUTING_RULES_R_DW8 | RO | 32 | 0x0000 0000 | 0x000 0220
ROUTING_RULES_R_DW9 | RO | 32 | 0x0000 0000 | 0x000 0224
ROUTING_RULES_R_DW10 | RO | 32 | 0x0000 0000 | 0x000 0228
ROUTING_RULES_R_DW11 | RO | 32 | 0x0000 0000 | 0x000 022C
ROUTING_RULES_R_DW12 | RO | 32 | 0x0000 0015 | 0x000 0230
ROUTING_RULES_R_DW13 | RO | 32 | 0x0000 0000 | 0x000 0234
ROUTING_RULES_R_DW14 | RO | 32 | 0x0000 0000 | 0x000 0238
ROUTING_RULES_R_DW15 | RO | 32 | 0x0000 0000 | 0x000 023C
ROUTING_RULES_W_DW0 | RO | 32 | 0x000F 0011 | 0x000 0240
ROUTING_RULES_W_DW1 | RO | 32 | 0x0000 0014 | 0x000 0244
ROUTING_RULES_W_DW2 | RO | 32 | 0x0000 0000 | 0x000 0248
ROUTING_RULES_W_DW3 | RO | 32 | 0x0000 0000 | 0x000 024C
ROUTING_RULES_W_DW4 | RO | 32 | 0x000B 0011 | 0x000 0250
ROUTING_RULES_W_DW5 | RO | 32 | 0x0000 0000 | 0x000 0254
ROUTING_RULES_W_DW6 | RO | 32 | 0x0000 0000 | 0x000 0258
ROUTING_RULES_W_DW7 | RO | 32 | 0x0000 0000 | 0x000 025C
ROUTING_RULES_W_DW8 | RO | 32 | 0x0000 0000 | 0x000 0260
ROUTING_RULES_W_DW9 | RO | 32 | 0x0000 0000 | 0x000 0264
ROUTING_RULES_W_DW10 | RO | 32 | 0x0000 0000 | 0x000 0268
ROUTING_RULES_W_DW11 | RO | 32 | 0x0000 0000 | 0x000 026C
ROUTING_RULES_W_DW12 | RO | 32 | 0x0000 0000 | 0x000 0270
ROUTING_RULES_W_DW13 | RO | 32 | 0x0000 0000 | 0x000 0274
ROUTING_RULES_W_DW14 | RO | 32 | 0x0000 0000 | 0x000 0278
ROUTING_RULES_W_DW15 | RO | 32 | 0x0000 0000 | 0x000 027C
ARBITRATION_RULES_DW0 | RW | 32 | 0x1111 1111 | 0x000 0280
ARBITRATION_RULES_DW1 | RW | 32 | 0x1111 1111 | 0x000 0284
ARBITRATION_RULES_DW2 | RW | 32 | 0x1111 1111 | 0x000 0288
ARBITRATION_RULES_DW3 | RW | 32 | 0x1111 1111 | 0x000 028C
ARBITRATION_RULES_DW4 | RW | 32 | 0x1111 1111 | 0x000 0290
ARBITRATION_RULES_DW5 | RW | 32 | 0x1111 1111 | 0x000 0294
ARBITRATION_RULES_DW6 | RW | 32 | 0x1111 1111 | 0x000 0298
ARBITRATION_RULES_DW7 | RW | 32 | 0x1111 1111 | 0x000 029C
ARBITRATION_RULES_DW8 | RW | 32 | 0x1111 1111 | 0x000 02A0
ARBITRATION_RULES_DW9 | RW | 32 | 0x1111 1111 | 0x000 02A4
ARBITRATION_RULES_DW10 | RW | 32 | 0x1111 1111 | 0x000 02A8
ARBITRATION_RULES_DW11 | RW | 32 | 0x1111 1111 | 0x000 02AC
ARBITRATION_RULES_DW12 | RW | 32 | 0x1111 1111 | 0x000 02B0
ARBITRATION_RULES_DW13 | RW | 32 | 0x1111 1111 | 0x000 02B4
ARBITRATION_RULES_DW14 | RW | 32 | 0x1111 1111 | 0x000 02B8
ARBITRATION_RULES_DW15 | RW | 32 | 0x1111 1111 | 0x000 02BC
PRIORITY_RULES_DW0 | RW | 32 | 0x0000 0000 | 0x000 02C0
PRIORITY_RULES_DW1 | RW | 32 | 0x0000 0000 | 0x000 02C4
PRIORITY_RULES_DW2 | RW | 32 | 0x0000 0000 | 0x000 02C8
PRIORITY_RULES_DW3 | RW | 32 | 0x0000 0000 | 0x000 02CC
PRIORITY_RULES_DW4 | RW | 32 | 0x0000 0000 | 0x000 02D0
PRIORITY_RULES_DW5 | RW | 32 | 0x0000 0000 | 0x000 02D4
PRIORITY_RULES_DW6 | RW | 32 | 0x0000 0000 | 0x000 02D8
PRIORITY_RULES_DW7 | RW | 32 | 0x0000 0000 | 0x000 02DC
PRIORITY_RULES_DW8 | RW | 32 | 0x0000 0000 | 0x000 02E0
PRIORITY_RULES_DW9 | RW | 32 | 0x0000 0000 | 0x000 02E4
PRIORITY_RULES_DW10 | RW | 32 | 0x0000 0000 | 0x000 02E8
PRIORITY_RULES_DW11 | RW | 32 | 0x0000 0000 | 0x000 02EC
PRIORITY_RULES_DW12 | RW | 32 | 0x0000 0000 | 0x000 02F0
PRIORITY_RULES_DW13 | RW | 32 | 0x0000 0000 | 0x000 02F4
PRIORITY_RULES_DW14 | RW | 32 | 0x0000 0000 | 0x000 02F8
PRIORITY_RULES_DW15 | RW | 32 | 0x0000 0000 | 0x000 02FC
P2A_TC_QOS_CONV | RW | 32 | 0x0000 0000 | 0x000 03C0
P2A_ATTR_CACHE_CONV | RW | 32 | 0x0000 0000 | 0x000 03C4
P2A_NC_BASE_ADDR_DW0 | RW | 32 | 0x0000 0000 | 0x000 03C8
P2A_NC_BASE_ADDR_DW1 | RW | 32 | 0x0000 0000 | 0x000 03CC
DMA0_SRC_PARAM | RW | 32 | 0x0000 0000 | 0x000 0400
DMA0_DESTPARAM | RW | 32 | 0x0000 0000 | 0x000 0404
DMA0_SRCADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 0408
DMA0_SRCADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 040C
DMA0_DESTADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 0410
DMA0_DESTADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 0414
DMA0_LENGTH | RW | 32 | 0x0000 0000 | 0x000 0418
DMA0_CONTROL | RW | 32 | 0x0300 0000 | 0x000 041C
DMA0_STATUS | RO | 32 | 0x0000 0000 | 0x000 0420
DMA0_PRC_LENGTH | RO | 32 | 0x0000 0000 | 0x000 0424
DMA0_SHARE_ACCESS | RO | 32 | 0x0000 0000 | 0x000 0428
DMA1_SRC_PARAM | RW | 32 | 0x0000 0004 | 0x000 0440
DMA1_DESTPARAM | RW | 32 | 0x0000 0000 | 0x000 0444
DMA1_SRCADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 0448
DMA1_SRCADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 044C
DMA1_DESTADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 0450
DMA1_DESTADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 0454
DMA1_LENGTH | RW | 32 | 0x0000 0000 | 0x000 0458
DMA1_CONTROL | RW | 32 | 0x0000 0000 | 0x000 045C
DMA1_STATUS | RO | 32 | 0x0000 0000 | 0x000 0460
DMA1_PRC_LENGTH | RO | 32 | 0x0000 0000 | 0x000 0464
DMA1_SHARE_ACCESS | RO | 32 | 0x0000 0000 | 0x000 0468
ATR0_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0017 | 0x000 0600
ATR0_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0604
ATR0_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0608
ATR0_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 060C
ATR0_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 000C | 0x000 0610
ATR0_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0618
ATR0_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 061C
ATR1_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 0620
ATR1_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0624
ATR1_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0628
ATR1_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 062C
ATR1_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0001 | 0x000 0630
ATR1_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0638
ATR1_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 063C
ATR2_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0019 | 0x000 0640
ATR2_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0644
ATR2_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0648
ATR2_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 064C
ATR2_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 0650
ATR2_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0658
ATR2_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 065C
ATR3_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 0660
ATR3_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0664
ATR3_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0668
ATR3_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 066C
ATR3_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0001 | 0x000 0670
ATR3_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0678
ATR3_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 067C
ATR4_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0680
ATR4_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0684
ATR4_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0688
ATR4_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 068C
ATR4_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 0690
ATR4_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0698
ATR4_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 069C
ATR5_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 06A0
ATR5_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 06A4
ATR5_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 06A8
ATR5_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 06AC
ATR5_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 06B0
ATR5_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 06B8
ATR5_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 06BC
ATR6_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 06C0
ATR6_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 06C4
ATR6_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 06C8
ATR6_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 06CC
ATR6_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 06D0
ATR6_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 06D8
ATR6_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 06DC
ATR7_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 06E0
ATR7_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 06E4
ATR7_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 06E8
ATR7_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 06EC
ATR7_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 06F0
ATR7_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 06F8
ATR7_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 06FC
ATR0_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0700
ATR0_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0704
ATR0_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0708
ATR0_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 070C
ATR0_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0710
ATR0_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0718
ATR0_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 071C
ATR1_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0720
ATR1_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0724
ATR1_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0728
ATR1_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 072C
ATR1_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0730
ATR1_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0738
ATR1_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 073C
ATR2_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0740
ATR2_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0744
ATR2_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0748
ATR2_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 074C
ATR2_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0750
ATR2_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0758
ATR2_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 075C
ATR3_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0760
ATR3_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0764
ATR3_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0768
ATR3_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 076C
ATR3_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0770
ATR3_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0778
ATR3_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 077C
ATR4_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0780
ATR4_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0784
ATR4_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0788
ATR4_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 078C
ATR4_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0790
ATR4_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0798
ATR4_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 079C
ATR5_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 07A0
ATR5_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 07A4
ATR5_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 07A8
ATR5_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 07AC
ATR5_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 07B0
ATR5_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 07B8
ATR5_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 07BC
ATR6_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 07C0
ATR6_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 07C4
ATR6_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 07C8
ATR6_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 07CC
ATR6_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 07D0
ATR6_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 07D8
ATR6_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 07DC
ATR7_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 07E0
ATR7_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 07E4
ATR7_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 07E8
ATR7_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 07EC
ATR7_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 07F0
ATR7_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 07F8
ATR7_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 07FC
ATR0_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0800
ATR0_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0804
ATR0_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0808
ATR0_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 080C
ATR0_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0810
ATR0_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0818
ATR0_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 081C
ATR1_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0820
ATR1_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0824
ATR1_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0828
ATR1_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 082C
ATR1_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0830
ATR1_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0838
ATR1_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 083C
ATR2_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0840
ATR2_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0844
ATR2_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0848
ATR2_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 084C
ATR2_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0850
ATR2_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0858
ATR2_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 085C
ATR3_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0860
ATR3_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0864
ATR3_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0868
ATR3_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 086C
ATR3_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0870
ATR3_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0878
ATR3_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 087C
ATR4_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0880
ATR4_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0884
ATR4_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0888
ATR4_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 088C
ATR4_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0890
ATR4_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0898
ATR4_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 089C
ATR5_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 08A0
ATR5_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 08A4
ATR5_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 08A8
ATR5_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 08AC
ATR5_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 08B0
ATR5_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 08B8
ATR5_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 08BC
ATR6_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 08C0
ATR6_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 08C4
ATR6_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 08C8
ATR6_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 08CC
ATR6_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 08D0
ATR6_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 08D8
ATR6_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 08DC
ATR7_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 08E0
ATR7_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 08E4
ATR7_AXI4_SLV0_TRSL_ADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 08E8
ATR7_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 08EC
ATR7_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 08F0
ATR7_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 08F8
ATR7_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 08FC

## PF_PCIE_BRIDGE Instances Mapping Summary

### PF_PCIE_BRIDGE : pcie_top_0_PF_PCIE_BRIDGE Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
BRIDGE_VER | RO | 32 | 0x0251 1154 | 0x000 0000 | 0x0300 4000
BRIDGE_BUS | RO | 32 | 0x1188 5153 | 0x000 0004 | 0x0300 4004
BRIDGE_IMPL_IF | RO | 32 | 0x0000 032B | 0x000 0008 | 0x0300 4008
PCIE_IF_CONF | RO | 32 | 0x1144 0170 | 0x000 0010 | 0x0300 4010
PCIE_BASIC_CONF | RO | 32 | 0x0311 0307 | 0x000 0014 | 0x0300 4014
PCIE_BASIC_STATUS | RO | 32 | 0x2000 0100 | 0x000 0018 | 0x0300 4018
AXI_SLVL_CONF | RO | 32 | 0xBB00 2121 | 0x000 0024 | 0x0300 4024
AXI_MST0_CONF | RO | 32 | 0x1188 3442 | 0x000 0030 | 0x0300 4030
AXI_SLV0_CONF | RO | 32 | 0x4444 3443 | 0x000 0034 | 0x0300 4034
GEN_SETTINGS | RW | 32 | 0x0001 9300 | 0x000 0080 | 0x0300 4080
PCIE_CFGCTRL | RW | 32 | 0x0000 0000 | 0x000 0084 | 0x0300 4084
PCIE_PIPE_DW0 | RO | 32 | 0x2000 0000 | 0x000 0088 | 0x0300 4088
PCIE_PIPE_DW1 | RO | 32 | 0x0800 0001 | 0x000 008C | 0x0300 408C
PCIE_VC_CRED_DW0 | RW | 32 | 0x1000 B818 | 0x000 0090 | 0x0300 4090
PCIE_VC_CRED_DW1 | RW | 32 | 0x0000 0001 | 0x000 0094 | 0x0300 4094
PCIE_PCI_IDS_DW0 | RW | 32 | 0x1100 1556 | 0x000 0098 | 0x0300 4098
PCIE_PCI_IDS_DW1 | RW | 32 | 0xFF00 0001 | 0x000 009C | 0x0300 409C
PCIE_PCI_IDS_DW2 | RW | 32 | 0x1100 1556 | 0x000 00A0 | 0x0300 40A0
PCIE_PCI_LPM | RW | 32 | 0xFE00 0000 | 0x000 00A4 | 0x0300 40A4
PCIE_PCI_IRQ_DW0 | RW | 32 | 0x8000 0054 | 0x000 00A8 | 0x0300 40A8
PCIE_PCI_IRQ_DW1 | RW | 32 | 0x0000 0000 | 0x000 00AC | 0x0300 40AC
PCIE_PCI_IRQ_DW2 | RW | 32 | 0x0000 0000 | 0x000 00B0 | 0x0300 40B0
PCIE_PCI_IOV_DW0 | RW | 32 | 0x0000 000A | 0x000 00B4 | 0x0300 40B4
PCIE_PCI_IOV_DW1 | RW | 32 | 0x0000 0000 | 0x000 00B8 | 0x0300 40B8
PCIE_PEX_DEV | RW | 32 | 0x0000 0001 | 0x000 00C0 | 0x0300 40C0
PCIE_PEX_DEV2 | RW | 32 | 0x0000 081F | 0x000 00C4 | 0x0300 40C4
PCIE_PEX_LINK | RW | 32 | 0x0100 1C00 | 0x000 00C8 | 0x0300 40C8
PCIE_PEX_SLOT | RO | 32 | 0x0000 007F | 0x000 00CC | 0x0300 40CC
PCIE_PEX_ROOT_VC | RW | 32 | 0x0000 0001 | 0x000 00D0 | 0x0300 40D0
PCIE_PEX_SPC | RW | 32 | 0x8000 5000 | 0x000 00D4 | 0x0300 40D4
PCIE_PEX_SPC2 | RW | 32 | 0x000C 6006 | 0x000 00D8 | 0x0300 40D8
PCIE_PEX_NFTS | RW | 32 | 0x0020 2020 | 0x000 00DC | 0x0300 40DC
PCIE_PEX_L1SS | RO | 32 | 0x0028 0A1D | 0x000 00E0 | 0x0300 40E0
PCIE_BAR_01_DW0 | RW | 32 | 0xFFFF F00C | 0x000 00E4 | 0x0300 40E4
PCIE_BAR_01_DW1 | RW | 32 | 0xFFFF FFFF | 0x000 00E8 | 0x0300 40E8
PCIE_BAR_23_DW0 | RW | 32 | 0xFFFF E00C | 0x000 00EC | 0x0300 40EC
PCIE_BAR_23_DW1 | RW | 32 | 0xFFFF FFFF | 0x000 00F0 | 0x0300 40F0
PCIE_BAR_45_DW0 | RW | 32 | 0x0000 0000 | 0x000 00F4 | 0x0300 40F4
PCIE_BAR_45_DW1 | RW | 32 | 0x0000 0000 | 0x000 00F8 | 0x0300 40F8
PCIE_BAR_WIN | RW | 32 | 0x0000 0000 | 0x000 00FC | 0x0300 40FC
PCIE_EQ_PRESET_DW0 | RW | 32 | 0x0000 0000 | 0x000 0100 | 0x0300 4100
PCIE_EQ_PRESET_DW1 | RW | 32 | 0x0000 0000 | 0x000 0104 | 0x0300 4104
PCIE_EQ_PRESET_DW2 | RW | 32 | 0x0000 0000 | 0x000 0108 | 0x0300 4108
PCIE_EQ_PRESET_DW3 | RW | 32 | 0x0000 0000 | 0x000 010C | 0x0300 410C
PCIE_EQ_PRESET_DW4 | RW | 32 | 0x0000 0000 | 0x000 0110 | 0x0300 4110
PCIE_EQ_PRESET_DW5 | RW | 32 | 0x0000 0000 | 0x000 0114 | 0x0300 4114
PCIE_EQ_PRESET_DW6 | RW | 32 | 0x0000 0000 | 0x000 0118 | 0x0300 4118
PCIE_EQ_PRESET_DW7 | RW | 32 | 0x0000 0000 | 0x000 011C | 0x0300 411C
PCIE_SRIOV_DW0 | RO | 32 | 0x0000 0000 | 0x000 0120 | 0x0300 4120
PCIE_SRIOV_DW1 | RO | 32 | 0x0000 0000 | 0x000 0124 | 0x0300 4124
PCIE_SRIOV_DW2 | RO | 32 | 0x0000 0000 | 0x000 0128 | 0x0300 4128
PCIE_SRIOV_DW3 | RO | 32 | 0x0000 0000 | 0x000 012C | 0x0300 412C
PCIE_SRIOV_DW4 | RO | 32 | 0x0000 0000 | 0x000 0130 | 0x0300 4130
PCIE_SRIOV_DW5 | RO | 32 | 0x0000 0000 | 0x000 0134 | 0x0300 4134
PCIE_SRIOV_DW6 | RO | 32 | 0x0000 0000 | 0x000 0138 | 0x0300 4138
PCIE_SRIOV_DW7 | RO | 32 | 0x0000 0000 | 0x000 013C | 0x0300 413C
PCIE_CFGNUM | RO | 32 | 0x0000 0000 | 0x000 0140 | 0x0300 4140
PM_CONF_DW0 | RW | 32 | 0x0000 0000 | 0x000 0174 | 0x0300 4174
PM_CONF_DW1 | RW | 32 | 0x0000 0000 | 0x000 0178 | 0x0300 4178
PM_CONF_DW2 | RW | 32 | 0x0000 0000 | 0x000 017C | 0x0300 417C
IMASK_LOCAL | RW | 32 | 0x0000 0000 | 0x000 0180 | 0x0300 4180
ISTATUS_LOCAL | RW | 32 | 0x0000 0000 | 0x000 0184 | 0x0300 4184
IMASK_HOST | RW | 32 | 0x0000 0000 | 0x000 0188 | 0x0300 4188
ISTATUS_HOST | RW | 32 | 0x0000 0000 | 0x000 018C | 0x0300 418C
IMSI_ADDR | RO | 32 | 0x0000 0190 | 0x000 0190 | 0x0300 4190
ISTATUS_MSI | RW | 32 | 0x0000 0000 | 0x000 0194 | 0x0300 4194
ICMD_PM | RW | 32 | 0x0000 0000 | 0x000 0198 | 0x0300 4198
ISTATUS_PM | RO | 32 | 0x0000 0000 | 0x000 019C | 0x0300 419C
ATS_PRI_REPORT | RW | 32 | 0x0000 0000 | 0x000 01A0 | 0x0300 41A0
LTR_VALUES | RW | 32 | 0x0000 0000 | 0x000 01A4 | 0x0300 41A4
ISTATUS_DMA0 | RO | 32 | 0x0000 0000 | 0x000 01B0 | 0x0300 41B0
ISTATUS_DMA1 | RO | 32 | 0x0000 0000 | 0x000 01B4 | 0x0300 41B4
ISTATUS_P_ADT_WIN0 | RO | 32 | 0x0000 0000 | 0x000 01D8 | 0x0300 41D8
ISTATUS_P_ADT_WIN1 | RO | 32 | 0x0000 0000 | 0x000 01DC | 0x0300 41DC
ISTATUS_A_ADT_SLV0 | RO | 32 | 0x0000 0000 | 0x000 01E0 | 0x0300 41E0
ISTATUS_A_ADT_SLV1 | RO | 32 | 0x0000 0000 | 0x000 01E4 | 0x0300 41E4
ISTATUS_A_ADT_SLV2 | RO | 32 | 0x0000 0000 | 0x000 01E8 | 0x0300 41E8
ISTATUS_A_ADT_SLV3 | RO | 32 | 0x0000 0000 | 0x000 01EC | 0x0300 41EC
ROUTING_RULES_R_DW0 | RO | 32 | 0x000B 0011 | 0x000 0200 | 0x0300 4200
ROUTING_RULES_R_DW1 | RO | 32 | 0x0000 0015 | 0x000 0204 | 0x0300 4204
ROUTING_RULES_R_DW2 | RO | 32 | 0x0000 0000 | 0x000 0208 | 0x0300 4208
ROUTING_RULES_R_DW3 | RO | 32 | 0x0000 0000 | 0x000 020C | 0x0300 420C
ROUTING_RULES_R_DW4 | RO | 32 | 0x000E 0011 | 0x000 0210 | 0x0300 4210
ROUTING_RULES_R_DW5 | RO | 32 | 0x0000 0000 | 0x000 0214 | 0x0300 4214
ROUTING_RULES_R_DW6 | RO | 32 | 0x0000 0000 | 0x000 0218 | 0x0300 4218
ROUTING_RULES_R_DW7 | RO | 32 | 0x0000 0000 | 0x000 021C | 0x0300 421C
ROUTING_RULES_R_DW8 | RO | 32 | 0x0000 0000 | 0x000 0220 | 0x0300 4220
ROUTING_RULES_R_DW9 | RO | 32 | 0x0000 0000 | 0x000 0224 | 0x0300 4224
ROUTING_RULES_R_DW10 | RO | 32 | 0x0000 0000 | 0x000 0228 | 0x0300 4228
ROUTING_RULES_R_DW11 | RO | 32 | 0x0000 0000 | 0x000 022C | 0x0300 422C
ROUTING_RULES_R_DW12 | RO | 32 | 0x0000 0015 | 0x000 0230 | 0x0300 4230
ROUTING_RULES_R_DW13 | RO | 32 | 0x0000 0000 | 0x000 0234 | 0x0300 4234
ROUTING_RULES_R_DW14 | RO | 32 | 0x0000 0000 | 0x000 0238 | 0x0300 4238
ROUTING_RULES_R_DW15 | RO | 32 | 0x0000 0000 | 0x000 023C | 0x0300 423C
ROUTING_RULES_W_DW0 | RO | 32 | 0x000F 0011 | 0x000 0240 | 0x0300 4240
ROUTING_RULES_W_DW1 | RO | 32 | 0x0000 0014 | 0x000 0244 | 0x0300 4244
ROUTING_RULES_W_DW2 | RO | 32 | 0x0000 0000 | 0x000 0248 | 0x0300 4248
ROUTING_RULES_W_DW3 | RO | 32 | 0x0000 0000 | 0x000 024C | 0x0300 424C
ROUTING_RULES_W_DW4 | RO | 32 | 0x000B 0011 | 0x000 0250 | 0x0300 4250
ROUTING_RULES_W_DW5 | RO | 32 | 0x0000 0000 | 0x000 0254 | 0x0300 4254
ROUTING_RULES_W_DW6 | RO | 32 | 0x0000 0000 | 0x000 0258 | 0x0300 4258
ROUTING_RULES_W_DW7 | RO | 32 | 0x0000 0000 | 0x000 025C | 0x0300 425C
ROUTING_RULES_W_DW8 | RO | 32 | 0x0000 0000 | 0x000 0260 | 0x0300 4260
ROUTING_RULES_W_DW9 | RO | 32 | 0x0000 0000 | 0x000 0264 | 0x0300 4264
ROUTING_RULES_W_DW10 | RO | 32 | 0x0000 0000 | 0x000 0268 | 0x0300 4268
ROUTING_RULES_W_DW11 | RO | 32 | 0x0000 0000 | 0x000 026C | 0x0300 426C
ROUTING_RULES_W_DW12 | RO | 32 | 0x0000 0000 | 0x000 0270 | 0x0300 4270
ROUTING_RULES_W_DW13 | RO | 32 | 0x0000 0000 | 0x000 0274 | 0x0300 4274
ROUTING_RULES_W_DW14 | RO | 32 | 0x0000 0000 | 0x000 0278 | 0x0300 4278
ROUTING_RULES_W_DW15 | RO | 32 | 0x0000 0000 | 0x000 027C | 0x0300 427C
ARBITRATION_RULES_DW0 | RW | 32 | 0x1111 1111 | 0x000 0280 | 0x0300 4280
ARBITRATION_RULES_DW1 | RW | 32 | 0x1111 1111 | 0x000 0284 | 0x0300 4284
ARBITRATION_RULES_DW2 | RW | 32 | 0x1111 1111 | 0x000 0288 | 0x0300 4288
ARBITRATION_RULES_DW3 | RW | 32 | 0x1111 1111 | 0x000 028C | 0x0300 428C
ARBITRATION_RULES_DW4 | RW | 32 | 0x1111 1111 | 0x000 0290 | 0x0300 4290
ARBITRATION_RULES_DW5 | RW | 32 | 0x1111 1111 | 0x000 0294 | 0x0300 4294
ARBITRATION_RULES_DW6 | RW | 32 | 0x1111 1111 | 0x000 0298 | 0x0300 4298
ARBITRATION_RULES_DW7 | RW | 32 | 0x1111 1111 | 0x000 029C | 0x0300 429C
ARBITRATION_RULES_DW8 | RW | 32 | 0x1111 1111 | 0x000 02A0 | 0x0300 42A0
ARBITRATION_RULES_DW9 | RW | 32 | 0x1111 1111 | 0x000 02A4 | 0x0300 42A4
ARBITRATION_RULES_DW10 | RW | 32 | 0x1111 1111 | 0x000 02A8 | 0x0300 42A8
ARBITRATION_RULES_DW11 | RW | 32 | 0x1111 1111 | 0x000 02AC | 0x0300 42AC
ARBITRATION_RULES_DW12 | RW | 32 | 0x1111 1111 | 0x000 02B0 | 0x0300 42B0
ARBITRATION_RULES_DW13 | RW | 32 | 0x1111 1111 | 0x000 02B4 | 0x0300 42B4
ARBITRATION_RULES_DW14 | RW | 32 | 0x1111 1111 | 0x000 02B8 | 0x0300 42B8
ARBITRATION_RULES_DW15 | RW | 32 | 0x1111 1111 | 0x000 02BC | 0x0300 42BC
PRIORITY_RULES_DW0 | RW | 32 | 0x0000 0000 | 0x000 02C0 | 0x0300 42C0
PRIORITY_RULES_DW1 | RW | 32 | 0x0000 0000 | 0x000 02C4 | 0x0300 42C4
PRIORITY_RULES_DW2 | RW | 32 | 0x0000 0000 | 0x000 02C8 | 0x0300 42C8
PRIORITY_RULES_DW3 | RW | 32 | 0x0000 0000 | 0x000 02CC | 0x0300 42CC
PRIORITY_RULES_DW4 | RW | 32 | 0x0000 0000 | 0x000 02D0 | 0x0300 42D0
PRIORITY_RULES_DW5 | RW | 32 | 0x0000 0000 | 0x000 02D4 | 0x0300 42D4
PRIORITY_RULES_DW6 | RW | 32 | 0x0000 0000 | 0x000 02D8 | 0x0300 42D8
PRIORITY_RULES_DW7 | RW | 32 | 0x0000 0000 | 0x000 02DC | 0x0300 42DC
PRIORITY_RULES_DW8 | RW | 32 | 0x0000 0000 | 0x000 02E0 | 0x0300 42E0
PRIORITY_RULES_DW9 | RW | 32 | 0x0000 0000 | 0x000 02E4 | 0x0300 42E4
PRIORITY_RULES_DW10 | RW | 32 | 0x0000 0000 | 0x000 02E8 | 0x0300 42E8
PRIORITY_RULES_DW11 | RW | 32 | 0x0000 0000 | 0x000 02EC | 0x0300 42EC
PRIORITY_RULES_DW12 | RW | 32 | 0x0000 0000 | 0x000 02F0 | 0x0300 42F0
PRIORITY_RULES_DW13 | RW | 32 | 0x0000 0000 | 0x000 02F4 | 0x0300 42F4
PRIORITY_RULES_DW14 | RW | 32 | 0x0000 0000 | 0x000 02F8 | 0x0300 42F8
PRIORITY_RULES_DW15 | RW | 32 | 0x0000 0000 | 0x000 02FC | 0x0300 42FC
P2A_TC_QOS_CONV | RW | 32 | 0x0000 0000 | 0x000 03C0 | 0x0300 43C0
P2A_ATTR_CACHE_CONV | RW | 32 | 0x0000 0000 | 0x000 03C4 | 0x0300 43C4
P2A_NC_BASE_ADDR_DW0 | RW | 32 | 0x0000 0000 | 0x000 03C8 | 0x0300 43C8
P2A_NC_BASE_ADDR_DW1 | RW | 32 | 0x0000 0000 | 0x000 03CC | 0x0300 43CC
DMA0_SRC_PARAM | RW | 32 | 0x0000 0000 | 0x000 0400 | 0x0300 4400
DMA0_DESTPARAM | RW | 32 | 0x0000 0000 | 0x000 0404 | 0x0300 4404
DMA0_SRCADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 0408 | 0x0300 4408
DMA0_SRCADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 040C | 0x0300 440C
DMA0_DESTADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 0410 | 0x0300 4410
DMA0_DESTADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 0414 | 0x0300 4414
DMA0_LENGTH | RW | 32 | 0x0000 0000 | 0x000 0418 | 0x0300 4418
DMA0_CONTROL | RW | 32 | 0x0300 0000 | 0x000 041C | 0x0300 441C
DMA0_STATUS | RO | 32 | 0x0000 0000 | 0x000 0420 | 0x0300 4420
DMA0_PRC_LENGTH | RO | 32 | 0x0000 0000 | 0x000 0424 | 0x0300 4424
DMA0_SHARE_ACCESS | RO | 32 | 0x0000 0000 | 0x000 0428 | 0x0300 4428
DMA1_SRC_PARAM | RW | 32 | 0x0000 0004 | 0x000 0440 | 0x0300 4440
DMA1_DESTPARAM | RW | 32 | 0x0000 0000 | 0x000 0444 | 0x0300 4444
DMA1_SRCADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 0448 | 0x0300 4448
DMA1_SRCADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 044C | 0x0300 444C
DMA1_DESTADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 0450 | 0x0300 4450
DMA1_DESTADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 0454 | 0x0300 4454
DMA1_LENGTH | RW | 32 | 0x0000 0000 | 0x000 0458 | 0x0300 4458
DMA1_CONTROL | RW | 32 | 0x0000 0000 | 0x000 045C | 0x0300 445C
DMA1_STATUS | RO | 32 | 0x0000 0000 | 0x000 0460 | 0x0300 4460
DMA1_PRC_LENGTH | RO | 32 | 0x0000 0000 | 0x000 0464 | 0x0300 4464
DMA1_SHARE_ACCESS | RO | 32 | 0x0000 0000 | 0x000 0468 | 0x0300 4468
ATR0_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0017 | 0x000 0600 | 0x0300 4600
ATR0_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0604 | 0x0300 4604
ATR0_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0608 | 0x0300 4608
ATR0_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 060C | 0x0300 460C
ATR0_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 000C | 0x000 0610 | 0x0300 4610
ATR0_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0618 | 0x0300 4618
ATR0_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 061C | 0x0300 461C
ATR1_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 0620 | 0x0300 4620
ATR1_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0624 | 0x0300 4624
ATR1_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0628 | 0x0300 4628
ATR1_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 062C | 0x0300 462C
ATR1_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0001 | 0x000 0630 | 0x0300 4630
ATR1_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0638 | 0x0300 4638
ATR1_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 063C | 0x0300 463C
ATR2_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0019 | 0x000 0640 | 0x0300 4640
ATR2_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0644 | 0x0300 4644
ATR2_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0648 | 0x0300 4648
ATR2_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 064C | 0x0300 464C
ATR2_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 0650 | 0x0300 4650
ATR2_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0658 | 0x0300 4658
ATR2_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 065C | 0x0300 465C
ATR3_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 0660 | 0x0300 4660
ATR3_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0664 | 0x0300 4664
ATR3_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0668 | 0x0300 4668
ATR3_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 066C | 0x0300 466C
ATR3_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0001 | 0x000 0670 | 0x0300 4670
ATR3_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0678 | 0x0300 4678
ATR3_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 067C | 0x0300 467C
ATR4_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0680 | 0x0300 4680
ATR4_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0684 | 0x0300 4684
ATR4_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0688 | 0x0300 4688
ATR4_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 068C | 0x0300 468C
ATR4_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 0690 | 0x0300 4690
ATR4_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0698 | 0x0300 4698
ATR4_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 069C | 0x0300 469C
ATR5_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 06A0 | 0x0300 46A0
ATR5_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 06A4 | 0x0300 46A4
ATR5_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 06A8 | 0x0300 46A8
ATR5_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 06AC | 0x0300 46AC
ATR5_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 06B0 | 0x0300 46B0
ATR5_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 06B8 | 0x0300 46B8
ATR5_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 06BC | 0x0300 46BC
ATR6_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 06C0 | 0x0300 46C0
ATR6_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 06C4 | 0x0300 46C4
ATR6_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 06C8 | 0x0300 46C8
ATR6_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 06CC | 0x0300 46CC
ATR6_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 06D0 | 0x0300 46D0
ATR6_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 06D8 | 0x0300 46D8
ATR6_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 06DC | 0x0300 46DC
ATR7_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 06E0 | 0x0300 46E0
ATR7_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 06E4 | 0x0300 46E4
ATR7_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 06E8 | 0x0300 46E8
ATR7_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 06EC | 0x0300 46EC
ATR7_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 06F0 | 0x0300 46F0
ATR7_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 06F8 | 0x0300 46F8
ATR7_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 06FC | 0x0300 46FC
ATR0_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0700 | 0x0300 4700
ATR0_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0704 | 0x0300 4704
ATR0_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0708 | 0x0300 4708
ATR0_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 070C | 0x0300 470C
ATR0_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0710 | 0x0300 4710
ATR0_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0718 | 0x0300 4718
ATR0_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 071C | 0x0300 471C
ATR1_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0720 | 0x0300 4720
ATR1_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0724 | 0x0300 4724
ATR1_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0728 | 0x0300 4728
ATR1_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 072C | 0x0300 472C
ATR1_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0730 | 0x0300 4730
ATR1_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0738 | 0x0300 4738
ATR1_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 073C | 0x0300 473C
ATR2_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0740 | 0x0300 4740
ATR2_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0744 | 0x0300 4744
ATR2_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0748 | 0x0300 4748
ATR2_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 074C | 0x0300 474C
ATR2_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0750 | 0x0300 4750
ATR2_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0758 | 0x0300 4758
ATR2_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 075C | 0x0300 475C
ATR3_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0760 | 0x0300 4760
ATR3_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0764 | 0x0300 4764
ATR3_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0768 | 0x0300 4768
ATR3_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 076C | 0x0300 476C
ATR3_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0770 | 0x0300 4770
ATR3_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0778 | 0x0300 4778
ATR3_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 077C | 0x0300 477C
ATR4_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0780 | 0x0300 4780
ATR4_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0784 | 0x0300 4784
ATR4_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0788 | 0x0300 4788
ATR4_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 078C | 0x0300 478C
ATR4_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0790 | 0x0300 4790
ATR4_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0798 | 0x0300 4798
ATR4_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 079C | 0x0300 479C
ATR5_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 07A0 | 0x0300 47A0
ATR5_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 07A4 | 0x0300 47A4
ATR5_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 07A8 | 0x0300 47A8
ATR5_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 07AC | 0x0300 47AC
ATR5_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 07B0 | 0x0300 47B0
ATR5_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 07B8 | 0x0300 47B8
ATR5_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 07BC | 0x0300 47BC
ATR6_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 07C0 | 0x0300 47C0
ATR6_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 07C4 | 0x0300 47C4
ATR6_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 07C8 | 0x0300 47C8
ATR6_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 07CC | 0x0300 47CC
ATR6_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 07D0 | 0x0300 47D0
ATR6_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 07D8 | 0x0300 47D8
ATR6_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 07DC | 0x0300 47DC
ATR7_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 07E0 | 0x0300 47E0
ATR7_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 07E4 | 0x0300 47E4
ATR7_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 07E8 | 0x0300 47E8
ATR7_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 07EC | 0x0300 47EC
ATR7_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 07F0 | 0x0300 47F0
ATR7_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 07F8 | 0x0300 47F8
ATR7_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 07FC | 0x0300 47FC
ATR0_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0800 | 0x0300 4800
ATR0_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0804 | 0x0300 4804
ATR0_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0808 | 0x0300 4808
ATR0_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 080C | 0x0300 480C
ATR0_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0810 | 0x0300 4810
ATR0_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0818 | 0x0300 4818
ATR0_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 081C | 0x0300 481C
ATR1_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0820 | 0x0300 4820
ATR1_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0824 | 0x0300 4824
ATR1_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0828 | 0x0300 4828
ATR1_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 082C | 0x0300 482C
ATR1_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0830 | 0x0300 4830
ATR1_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0838 | 0x0300 4838
ATR1_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 083C | 0x0300 483C
ATR2_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0840 | 0x0300 4840
ATR2_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0844 | 0x0300 4844
ATR2_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0848 | 0x0300 4848
ATR2_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 084C | 0x0300 484C
ATR2_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0850 | 0x0300 4850
ATR2_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0858 | 0x0300 4858
ATR2_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 085C | 0x0300 485C
ATR3_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0860 | 0x0300 4860
ATR3_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0864 | 0x0300 4864
ATR3_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0868 | 0x0300 4868
ATR3_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 086C | 0x0300 486C
ATR3_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0870 | 0x0300 4870
ATR3_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0878 | 0x0300 4878
ATR3_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 087C | 0x0300 487C
ATR4_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0880 | 0x0300 4880
ATR4_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0884 | 0x0300 4884
ATR4_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0888 | 0x0300 4888
ATR4_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 088C | 0x0300 488C
ATR4_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0890 | 0x0300 4890
ATR4_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0898 | 0x0300 4898
ATR4_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 089C | 0x0300 489C
ATR5_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 08A0 | 0x0300 48A0
ATR5_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 08A4 | 0x0300 48A4
ATR5_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 08A8 | 0x0300 48A8
ATR5_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 08AC | 0x0300 48AC
ATR5_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 08B0 | 0x0300 48B0
ATR5_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 08B8 | 0x0300 48B8
ATR5_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 08BC | 0x0300 48BC
ATR6_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 08C0 | 0x0300 48C0
ATR6_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 08C4 | 0x0300 48C4
ATR6_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 08C8 | 0x0300 48C8
ATR6_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 08CC | 0x0300 48CC
ATR6_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 08D0 | 0x0300 48D0
ATR6_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 08D8 | 0x0300 48D8
ATR6_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 08DC | 0x0300 48DC
ATR7_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 08E0 | 0x0300 48E0
ATR7_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 08E4 | 0x0300 48E4
ATR7_AXI4_SLV0_TRSL_ADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 08E8 | 0x0300 48E8
ATR7_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 08EC | 0x0300 48EC
ATR7_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 08F0 | 0x0300 48F0
ATR7_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 08F8 | 0x0300 48F8
ATR7_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 08FC | 0x0300 48FC

### PF_PCIE_BRIDGE : pcie_top_1_PF_PCIE_BRIDGE Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
BRIDGE_VER | RO | 32 | 0x0251 1154 | 0x000 0000 | 0x0300 8000
BRIDGE_BUS | RO | 32 | 0x1188 5153 | 0x000 0004 | 0x0300 8004
BRIDGE_IMPL_IF | RO | 32 | 0x0000 032B | 0x000 0008 | 0x0300 8008
PCIE_IF_CONF | RO | 32 | 0x1144 0170 | 0x000 0010 | 0x0300 8010
PCIE_BASIC_CONF | RO | 32 | 0x0311 0307 | 0x000 0014 | 0x0300 8014
PCIE_BASIC_STATUS | RO | 32 | 0x2000 0100 | 0x000 0018 | 0x0300 8018
AXI_SLVL_CONF | RO | 32 | 0xBB00 2121 | 0x000 0024 | 0x0300 8024
AXI_MST0_CONF | RO | 32 | 0x1188 3442 | 0x000 0030 | 0x0300 8030
AXI_SLV0_CONF | RO | 32 | 0x4444 3443 | 0x000 0034 | 0x0300 8034
GEN_SETTINGS | RW | 32 | 0x0001 9300 | 0x000 0080 | 0x0300 8080
PCIE_CFGCTRL | RW | 32 | 0x0000 0000 | 0x000 0084 | 0x0300 8084
PCIE_PIPE_DW0 | RO | 32 | 0x2000 0000 | 0x000 0088 | 0x0300 8088
PCIE_PIPE_DW1 | RO | 32 | 0x0800 0001 | 0x000 008C | 0x0300 808C
PCIE_VC_CRED_DW0 | RW | 32 | 0x1000 B818 | 0x000 0090 | 0x0300 8090
PCIE_VC_CRED_DW1 | RW | 32 | 0x0000 0001 | 0x000 0094 | 0x0300 8094
PCIE_PCI_IDS_DW0 | RW | 32 | 0x1100 1556 | 0x000 0098 | 0x0300 8098
PCIE_PCI_IDS_DW1 | RW | 32 | 0xFF00 0001 | 0x000 009C | 0x0300 809C
PCIE_PCI_IDS_DW2 | RW | 32 | 0x1100 1556 | 0x000 00A0 | 0x0300 80A0
PCIE_PCI_LPM | RW | 32 | 0xFE00 0000 | 0x000 00A4 | 0x0300 80A4
PCIE_PCI_IRQ_DW0 | RW | 32 | 0x8000 0054 | 0x000 00A8 | 0x0300 80A8
PCIE_PCI_IRQ_DW1 | RW | 32 | 0x0000 0000 | 0x000 00AC | 0x0300 80AC
PCIE_PCI_IRQ_DW2 | RW | 32 | 0x0000 0000 | 0x000 00B0 | 0x0300 80B0
PCIE_PCI_IOV_DW0 | RW | 32 | 0x0000 000A | 0x000 00B4 | 0x0300 80B4
PCIE_PCI_IOV_DW1 | RW | 32 | 0x0000 0000 | 0x000 00B8 | 0x0300 80B8
PCIE_PEX_DEV | RW | 32 | 0x0000 0001 | 0x000 00C0 | 0x0300 80C0
PCIE_PEX_DEV2 | RW | 32 | 0x0000 081F | 0x000 00C4 | 0x0300 80C4
PCIE_PEX_LINK | RW | 32 | 0x0100 1C00 | 0x000 00C8 | 0x0300 80C8
PCIE_PEX_SLOT | RO | 32 | 0x0000 007F | 0x000 00CC | 0x0300 80CC
PCIE_PEX_ROOT_VC | RW | 32 | 0x0000 0001 | 0x000 00D0 | 0x0300 80D0
PCIE_PEX_SPC | RW | 32 | 0x8000 5000 | 0x000 00D4 | 0x0300 80D4
PCIE_PEX_SPC2 | RW | 32 | 0x000C 6006 | 0x000 00D8 | 0x0300 80D8
PCIE_PEX_NFTS | RW | 32 | 0x0020 2020 | 0x000 00DC | 0x0300 80DC
PCIE_PEX_L1SS | RO | 32 | 0x0028 0A1D | 0x000 00E0 | 0x0300 80E0
PCIE_BAR_01_DW0 | RW | 32 | 0xFFFF F00C | 0x000 00E4 | 0x0300 80E4
PCIE_BAR_01_DW1 | RW | 32 | 0xFFFF FFFF | 0x000 00E8 | 0x0300 80E8
PCIE_BAR_23_DW0 | RW | 32 | 0xFFFF E00C | 0x000 00EC | 0x0300 80EC
PCIE_BAR_23_DW1 | RW | 32 | 0xFFFF FFFF | 0x000 00F0 | 0x0300 80F0
PCIE_BAR_45_DW0 | RW | 32 | 0x0000 0000 | 0x000 00F4 | 0x0300 80F4
PCIE_BAR_45_DW1 | RW | 32 | 0x0000 0000 | 0x000 00F8 | 0x0300 80F8
PCIE_BAR_WIN | RW | 32 | 0x0000 0000 | 0x000 00FC | 0x0300 80FC
PCIE_EQ_PRESET_DW0 | RW | 32 | 0x0000 0000 | 0x000 0100 | 0x0300 8100
PCIE_EQ_PRESET_DW1 | RW | 32 | 0x0000 0000 | 0x000 0104 | 0x0300 8104
PCIE_EQ_PRESET_DW2 | RW | 32 | 0x0000 0000 | 0x000 0108 | 0x0300 8108
PCIE_EQ_PRESET_DW3 | RW | 32 | 0x0000 0000 | 0x000 010C | 0x0300 810C
PCIE_EQ_PRESET_DW4 | RW | 32 | 0x0000 0000 | 0x000 0110 | 0x0300 8110
PCIE_EQ_PRESET_DW5 | RW | 32 | 0x0000 0000 | 0x000 0114 | 0x0300 8114
PCIE_EQ_PRESET_DW6 | RW | 32 | 0x0000 0000 | 0x000 0118 | 0x0300 8118
PCIE_EQ_PRESET_DW7 | RW | 32 | 0x0000 0000 | 0x000 011C | 0x0300 811C
PCIE_SRIOV_DW0 | RO | 32 | 0x0000 0000 | 0x000 0120 | 0x0300 8120
PCIE_SRIOV_DW1 | RO | 32 | 0x0000 0000 | 0x000 0124 | 0x0300 8124
PCIE_SRIOV_DW2 | RO | 32 | 0x0000 0000 | 0x000 0128 | 0x0300 8128
PCIE_SRIOV_DW3 | RO | 32 | 0x0000 0000 | 0x000 012C | 0x0300 812C
PCIE_SRIOV_DW4 | RO | 32 | 0x0000 0000 | 0x000 0130 | 0x0300 8130
PCIE_SRIOV_DW5 | RO | 32 | 0x0000 0000 | 0x000 0134 | 0x0300 8134
PCIE_SRIOV_DW6 | RO | 32 | 0x0000 0000 | 0x000 0138 | 0x0300 8138
PCIE_SRIOV_DW7 | RO | 32 | 0x0000 0000 | 0x000 013C | 0x0300 813C
PCIE_CFGNUM | RO | 32 | 0x0000 0000 | 0x000 0140 | 0x0300 8140
PM_CONF_DW0 | RW | 32 | 0x0000 0000 | 0x000 0174 | 0x0300 8174
PM_CONF_DW1 | RW | 32 | 0x0000 0000 | 0x000 0178 | 0x0300 8178
PM_CONF_DW2 | RW | 32 | 0x0000 0000 | 0x000 017C | 0x0300 817C
IMASK_LOCAL | RW | 32 | 0x0000 0000 | 0x000 0180 | 0x0300 8180
ISTATUS_LOCAL | RW | 32 | 0x0000 0000 | 0x000 0184 | 0x0300 8184
IMASK_HOST | RW | 32 | 0x0000 0000 | 0x000 0188 | 0x0300 8188
ISTATUS_HOST | RW | 32 | 0x0000 0000 | 0x000 018C | 0x0300 818C
IMSI_ADDR | RO | 32 | 0x0000 0190 | 0x000 0190 | 0x0300 8190
ISTATUS_MSI | RW | 32 | 0x0000 0000 | 0x000 0194 | 0x0300 8194
ICMD_PM | RW | 32 | 0x0000 0000 | 0x000 0198 | 0x0300 8198
ISTATUS_PM | RO | 32 | 0x0000 0000 | 0x000 019C | 0x0300 819C
ATS_PRI_REPORT | RW | 32 | 0x0000 0000 | 0x000 01A0 | 0x0300 81A0
LTR_VALUES | RW | 32 | 0x0000 0000 | 0x000 01A4 | 0x0300 81A4
ISTATUS_DMA0 | RO | 32 | 0x0000 0000 | 0x000 01B0 | 0x0300 81B0
ISTATUS_DMA1 | RO | 32 | 0x0000 0000 | 0x000 01B4 | 0x0300 81B4
ISTATUS_P_ADT_WIN0 | RO | 32 | 0x0000 0000 | 0x000 01D8 | 0x0300 81D8
ISTATUS_P_ADT_WIN1 | RO | 32 | 0x0000 0000 | 0x000 01DC | 0x0300 81DC
ISTATUS_A_ADT_SLV0 | RO | 32 | 0x0000 0000 | 0x000 01E0 | 0x0300 81E0
ISTATUS_A_ADT_SLV1 | RO | 32 | 0x0000 0000 | 0x000 01E4 | 0x0300 81E4
ISTATUS_A_ADT_SLV2 | RO | 32 | 0x0000 0000 | 0x000 01E8 | 0x0300 81E8
ISTATUS_A_ADT_SLV3 | RO | 32 | 0x0000 0000 | 0x000 01EC | 0x0300 81EC
ROUTING_RULES_R_DW0 | RO | 32 | 0x000B 0011 | 0x000 0200 | 0x0300 8200
ROUTING_RULES_R_DW1 | RO | 32 | 0x0000 0015 | 0x000 0204 | 0x0300 8204
ROUTING_RULES_R_DW2 | RO | 32 | 0x0000 0000 | 0x000 0208 | 0x0300 8208
ROUTING_RULES_R_DW3 | RO | 32 | 0x0000 0000 | 0x000 020C | 0x0300 820C
ROUTING_RULES_R_DW4 | RO | 32 | 0x000E 0011 | 0x000 0210 | 0x0300 8210
ROUTING_RULES_R_DW5 | RO | 32 | 0x0000 0000 | 0x000 0214 | 0x0300 8214
ROUTING_RULES_R_DW6 | RO | 32 | 0x0000 0000 | 0x000 0218 | 0x0300 8218
ROUTING_RULES_R_DW7 | RO | 32 | 0x0000 0000 | 0x000 021C | 0x0300 821C
ROUTING_RULES_R_DW8 | RO | 32 | 0x0000 0000 | 0x000 0220 | 0x0300 8220
ROUTING_RULES_R_DW9 | RO | 32 | 0x0000 0000 | 0x000 0224 | 0x0300 8224
ROUTING_RULES_R_DW10 | RO | 32 | 0x0000 0000 | 0x000 0228 | 0x0300 8228
ROUTING_RULES_R_DW11 | RO | 32 | 0x0000 0000 | 0x000 022C | 0x0300 822C
ROUTING_RULES_R_DW12 | RO | 32 | 0x0000 0015 | 0x000 0230 | 0x0300 8230
ROUTING_RULES_R_DW13 | RO | 32 | 0x0000 0000 | 0x000 0234 | 0x0300 8234
ROUTING_RULES_R_DW14 | RO | 32 | 0x0000 0000 | 0x000 0238 | 0x0300 8238
ROUTING_RULES_R_DW15 | RO | 32 | 0x0000 0000 | 0x000 023C | 0x0300 823C
ROUTING_RULES_W_DW0 | RO | 32 | 0x000F 0011 | 0x000 0240 | 0x0300 8240
ROUTING_RULES_W_DW1 | RO | 32 | 0x0000 0014 | 0x000 0244 | 0x0300 8244
ROUTING_RULES_W_DW2 | RO | 32 | 0x0000 0000 | 0x000 0248 | 0x0300 8248
ROUTING_RULES_W_DW3 | RO | 32 | 0x0000 0000 | 0x000 024C | 0x0300 824C
ROUTING_RULES_W_DW4 | RO | 32 | 0x000B 0011 | 0x000 0250 | 0x0300 8250
ROUTING_RULES_W_DW5 | RO | 32 | 0x0000 0000 | 0x000 0254 | 0x0300 8254
ROUTING_RULES_W_DW6 | RO | 32 | 0x0000 0000 | 0x000 0258 | 0x0300 8258
ROUTING_RULES_W_DW7 | RO | 32 | 0x0000 0000 | 0x000 025C | 0x0300 825C
ROUTING_RULES_W_DW8 | RO | 32 | 0x0000 0000 | 0x000 0260 | 0x0300 8260
ROUTING_RULES_W_DW9 | RO | 32 | 0x0000 0000 | 0x000 0264 | 0x0300 8264
ROUTING_RULES_W_DW10 | RO | 32 | 0x0000 0000 | 0x000 0268 | 0x0300 8268
ROUTING_RULES_W_DW11 | RO | 32 | 0x0000 0000 | 0x000 026C | 0x0300 826C
ROUTING_RULES_W_DW12 | RO | 32 | 0x0000 0000 | 0x000 0270 | 0x0300 8270
ROUTING_RULES_W_DW13 | RO | 32 | 0x0000 0000 | 0x000 0274 | 0x0300 8274
ROUTING_RULES_W_DW14 | RO | 32 | 0x0000 0000 | 0x000 0278 | 0x0300 8278
ROUTING_RULES_W_DW15 | RO | 32 | 0x0000 0000 | 0x000 027C | 0x0300 827C
ARBITRATION_RULES_DW0 | RW | 32 | 0x1111 1111 | 0x000 0280 | 0x0300 8280
ARBITRATION_RULES_DW1 | RW | 32 | 0x1111 1111 | 0x000 0284 | 0x0300 8284
ARBITRATION_RULES_DW2 | RW | 32 | 0x1111 1111 | 0x000 0288 | 0x0300 8288
ARBITRATION_RULES_DW3 | RW | 32 | 0x1111 1111 | 0x000 028C | 0x0300 828C
ARBITRATION_RULES_DW4 | RW | 32 | 0x1111 1111 | 0x000 0290 | 0x0300 8290
ARBITRATION_RULES_DW5 | RW | 32 | 0x1111 1111 | 0x000 0294 | 0x0300 8294
ARBITRATION_RULES_DW6 | RW | 32 | 0x1111 1111 | 0x000 0298 | 0x0300 8298
ARBITRATION_RULES_DW7 | RW | 32 | 0x1111 1111 | 0x000 029C | 0x0300 829C
ARBITRATION_RULES_DW8 | RW | 32 | 0x1111 1111 | 0x000 02A0 | 0x0300 82A0
ARBITRATION_RULES_DW9 | RW | 32 | 0x1111 1111 | 0x000 02A4 | 0x0300 82A4
ARBITRATION_RULES_DW10 | RW | 32 | 0x1111 1111 | 0x000 02A8 | 0x0300 82A8
ARBITRATION_RULES_DW11 | RW | 32 | 0x1111 1111 | 0x000 02AC | 0x0300 82AC
ARBITRATION_RULES_DW12 | RW | 32 | 0x1111 1111 | 0x000 02B0 | 0x0300 82B0
ARBITRATION_RULES_DW13 | RW | 32 | 0x1111 1111 | 0x000 02B4 | 0x0300 82B4
ARBITRATION_RULES_DW14 | RW | 32 | 0x1111 1111 | 0x000 02B8 | 0x0300 82B8
ARBITRATION_RULES_DW15 | RW | 32 | 0x1111 1111 | 0x000 02BC | 0x0300 82BC
PRIORITY_RULES_DW0 | RW | 32 | 0x0000 0000 | 0x000 02C0 | 0x0300 82C0
PRIORITY_RULES_DW1 | RW | 32 | 0x0000 0000 | 0x000 02C4 | 0x0300 82C4
PRIORITY_RULES_DW2 | RW | 32 | 0x0000 0000 | 0x000 02C8 | 0x0300 82C8
PRIORITY_RULES_DW3 | RW | 32 | 0x0000 0000 | 0x000 02CC | 0x0300 82CC
PRIORITY_RULES_DW4 | RW | 32 | 0x0000 0000 | 0x000 02D0 | 0x0300 82D0
PRIORITY_RULES_DW5 | RW | 32 | 0x0000 0000 | 0x000 02D4 | 0x0300 82D4
PRIORITY_RULES_DW6 | RW | 32 | 0x0000 0000 | 0x000 02D8 | 0x0300 82D8
PRIORITY_RULES_DW7 | RW | 32 | 0x0000 0000 | 0x000 02DC | 0x0300 82DC
PRIORITY_RULES_DW8 | RW | 32 | 0x0000 0000 | 0x000 02E0 | 0x0300 82E0
PRIORITY_RULES_DW9 | RW | 32 | 0x0000 0000 | 0x000 02E4 | 0x0300 82E4
PRIORITY_RULES_DW10 | RW | 32 | 0x0000 0000 | 0x000 02E8 | 0x0300 82E8
PRIORITY_RULES_DW11 | RW | 32 | 0x0000 0000 | 0x000 02EC | 0x0300 82EC
PRIORITY_RULES_DW12 | RW | 32 | 0x0000 0000 | 0x000 02F0 | 0x0300 82F0
PRIORITY_RULES_DW13 | RW | 32 | 0x0000 0000 | 0x000 02F4 | 0x0300 82F4
PRIORITY_RULES_DW14 | RW | 32 | 0x0000 0000 | 0x000 02F8 | 0x0300 82F8
PRIORITY_RULES_DW15 | RW | 32 | 0x0000 0000 | 0x000 02FC | 0x0300 82FC
P2A_TC_QOS_CONV | RW | 32 | 0x0000 0000 | 0x000 03C0 | 0x0300 83C0
P2A_ATTR_CACHE_CONV | RW | 32 | 0x0000 0000 | 0x000 03C4 | 0x0300 83C4
P2A_NC_BASE_ADDR_DW0 | RW | 32 | 0x0000 0000 | 0x000 03C8 | 0x0300 83C8
P2A_NC_BASE_ADDR_DW1 | RW | 32 | 0x0000 0000 | 0x000 03CC | 0x0300 83CC
DMA0_SRC_PARAM | RW | 32 | 0x0000 0000 | 0x000 0400 | 0x0300 8400
DMA0_DESTPARAM | RW | 32 | 0x0000 0000 | 0x000 0404 | 0x0300 8404
DMA0_SRCADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 0408 | 0x0300 8408
DMA0_SRCADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 040C | 0x0300 840C
DMA0_DESTADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 0410 | 0x0300 8410
DMA0_DESTADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 0414 | 0x0300 8414
DMA0_LENGTH | RW | 32 | 0x0000 0000 | 0x000 0418 | 0x0300 8418
DMA0_CONTROL | RW | 32 | 0x0300 0000 | 0x000 041C | 0x0300 841C
DMA0_STATUS | RO | 32 | 0x0000 0000 | 0x000 0420 | 0x0300 8420
DMA0_PRC_LENGTH | RO | 32 | 0x0000 0000 | 0x000 0424 | 0x0300 8424
DMA0_SHARE_ACCESS | RO | 32 | 0x0000 0000 | 0x000 0428 | 0x0300 8428
DMA1_SRC_PARAM | RW | 32 | 0x0000 0004 | 0x000 0440 | 0x0300 8440
DMA1_DESTPARAM | RW | 32 | 0x0000 0000 | 0x000 0444 | 0x0300 8444
DMA1_SRCADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 0448 | 0x0300 8448
DMA1_SRCADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 044C | 0x0300 844C
DMA1_DESTADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 0450 | 0x0300 8450
DMA1_DESTADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 0454 | 0x0300 8454
DMA1_LENGTH | RW | 32 | 0x0000 0000 | 0x000 0458 | 0x0300 8458
DMA1_CONTROL | RW | 32 | 0x0000 0000 | 0x000 045C | 0x0300 845C
DMA1_STATUS | RO | 32 | 0x0000 0000 | 0x000 0460 | 0x0300 8460
DMA1_PRC_LENGTH | RO | 32 | 0x0000 0000 | 0x000 0464 | 0x0300 8464
DMA1_SHARE_ACCESS | RO | 32 | 0x0000 0000 | 0x000 0468 | 0x0300 8468
ATR0_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0017 | 0x000 0600 | 0x0300 8600
ATR0_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0604 | 0x0300 8604
ATR0_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0608 | 0x0300 8608
ATR0_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 060C | 0x0300 860C
ATR0_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 000C | 0x000 0610 | 0x0300 8610
ATR0_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0618 | 0x0300 8618
ATR0_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 061C | 0x0300 861C
ATR1_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 0620 | 0x0300 8620
ATR1_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0624 | 0x0300 8624
ATR1_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0628 | 0x0300 8628
ATR1_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 062C | 0x0300 862C
ATR1_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0001 | 0x000 0630 | 0x0300 8630
ATR1_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0638 | 0x0300 8638
ATR1_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 063C | 0x0300 863C
ATR2_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0019 | 0x000 0640 | 0x0300 8640
ATR2_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0644 | 0x0300 8644
ATR2_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0648 | 0x0300 8648
ATR2_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 064C | 0x0300 864C
ATR2_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 0650 | 0x0300 8650
ATR2_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0658 | 0x0300 8658
ATR2_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 065C | 0x0300 865C
ATR3_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 0660 | 0x0300 8660
ATR3_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0664 | 0x0300 8664
ATR3_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0668 | 0x0300 8668
ATR3_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 066C | 0x0300 866C
ATR3_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0001 | 0x000 0670 | 0x0300 8670
ATR3_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0678 | 0x0300 8678
ATR3_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 067C | 0x0300 867C
ATR4_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0680 | 0x0300 8680
ATR4_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0684 | 0x0300 8684
ATR4_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0688 | 0x0300 8688
ATR4_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 068C | 0x0300 868C
ATR4_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 0690 | 0x0300 8690
ATR4_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 0698 | 0x0300 8698
ATR4_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 069C | 0x0300 869C
ATR5_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 06A0 | 0x0300 86A0
ATR5_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 06A4 | 0x0300 86A4
ATR5_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 06A8 | 0x0300 86A8
ATR5_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 06AC | 0x0300 86AC
ATR5_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 06B0 | 0x0300 86B0
ATR5_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 06B8 | 0x0300 86B8
ATR5_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 06BC | 0x0300 86BC
ATR6_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 06C0 | 0x0300 86C0
ATR6_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 06C4 | 0x0300 86C4
ATR6_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 06C8 | 0x0300 86C8
ATR6_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 06CC | 0x0300 86CC
ATR6_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 06D0 | 0x0300 86D0
ATR6_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 06D8 | 0x0300 86D8
ATR6_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 06DC | 0x0300 86DC
ATR7_PCIE_WIN0_SRCADDR_PARAM | RW | 32 | 0x0000 0016 | 0x000 06E0 | 0x0300 86E0
ATR7_PCIE_WIN0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 06E4 | 0x0300 86E4
ATR7_PCIE_WIN0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 06E8 | 0x0300 86E8
ATR7_PCIE_WIN0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 06EC | 0x0300 86EC
ATR7_PCIE_WIN0_TRSL_PARAM | RW | 32 | 0x0000 0004 | 0x000 06F0 | 0x0300 86F0
ATR7_PCIE_WIN0_TRSL_MASK_DW0 | RO | 32 | 0xFFFF F000 | 0x000 06F8 | 0x0300 86F8
ATR7_PCIE_WIN0_TRSL_MASK_DW1 | RO | 32 | 0xFFFF FFFF | 0x000 06FC | 0x0300 86FC
ATR0_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0700 | 0x0300 8700
ATR0_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0704 | 0x0300 8704
ATR0_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0708 | 0x0300 8708
ATR0_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 070C | 0x0300 870C
ATR0_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0710 | 0x0300 8710
ATR0_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0718 | 0x0300 8718
ATR0_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 071C | 0x0300 871C
ATR1_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0720 | 0x0300 8720
ATR1_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0724 | 0x0300 8724
ATR1_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0728 | 0x0300 8728
ATR1_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 072C | 0x0300 872C
ATR1_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0730 | 0x0300 8730
ATR1_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0738 | 0x0300 8738
ATR1_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 073C | 0x0300 873C
ATR2_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0740 | 0x0300 8740
ATR2_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0744 | 0x0300 8744
ATR2_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0748 | 0x0300 8748
ATR2_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 074C | 0x0300 874C
ATR2_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0750 | 0x0300 8750
ATR2_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0758 | 0x0300 8758
ATR2_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 075C | 0x0300 875C
ATR3_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0760 | 0x0300 8760
ATR3_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0764 | 0x0300 8764
ATR3_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0768 | 0x0300 8768
ATR3_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 076C | 0x0300 876C
ATR3_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0770 | 0x0300 8770
ATR3_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0778 | 0x0300 8778
ATR3_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 077C | 0x0300 877C
ATR4_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0780 | 0x0300 8780
ATR4_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0784 | 0x0300 8784
ATR4_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0788 | 0x0300 8788
ATR4_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 078C | 0x0300 878C
ATR4_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0790 | 0x0300 8790
ATR4_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0798 | 0x0300 8798
ATR4_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 079C | 0x0300 879C
ATR5_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 07A0 | 0x0300 87A0
ATR5_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 07A4 | 0x0300 87A4
ATR5_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 07A8 | 0x0300 87A8
ATR5_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 07AC | 0x0300 87AC
ATR5_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 07B0 | 0x0300 87B0
ATR5_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 07B8 | 0x0300 87B8
ATR5_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 07BC | 0x0300 87BC
ATR6_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 07C0 | 0x0300 87C0
ATR6_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 07C4 | 0x0300 87C4
ATR6_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 07C8 | 0x0300 87C8
ATR6_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 07CC | 0x0300 87CC
ATR6_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 07D0 | 0x0300 87D0
ATR6_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 07D8 | 0x0300 87D8
ATR6_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 07DC | 0x0300 87DC
ATR7_PCIE_WIN1_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 07E0 | 0x0300 87E0
ATR7_PCIE_WIN1_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 07E4 | 0x0300 87E4
ATR7_PCIE_WIN1_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 07E8 | 0x0300 87E8
ATR7_PCIE_WIN1_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 07EC | 0x0300 87EC
ATR7_PCIE_WIN1_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 07F0 | 0x0300 87F0
ATR7_PCIE_WIN1_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 07F8 | 0x0300 87F8
ATR7_PCIE_WIN1_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 07FC | 0x0300 87FC
ATR0_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0800 | 0x0300 8800
ATR0_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0804 | 0x0300 8804
ATR0_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0808 | 0x0300 8808
ATR0_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 080C | 0x0300 880C
ATR0_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0810 | 0x0300 8810
ATR0_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0818 | 0x0300 8818
ATR0_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 081C | 0x0300 881C
ATR1_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0820 | 0x0300 8820
ATR1_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0824 | 0x0300 8824
ATR1_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0828 | 0x0300 8828
ATR1_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 082C | 0x0300 882C
ATR1_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0830 | 0x0300 8830
ATR1_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0838 | 0x0300 8838
ATR1_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 083C | 0x0300 883C
ATR2_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0840 | 0x0300 8840
ATR2_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0844 | 0x0300 8844
ATR2_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0848 | 0x0300 8848
ATR2_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 084C | 0x0300 884C
ATR2_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0850 | 0x0300 8850
ATR2_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0858 | 0x0300 8858
ATR2_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 085C | 0x0300 885C
ATR3_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0860 | 0x0300 8860
ATR3_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0864 | 0x0300 8864
ATR3_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0868 | 0x0300 8868
ATR3_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 086C | 0x0300 886C
ATR3_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0870 | 0x0300 8870
ATR3_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0878 | 0x0300 8878
ATR3_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 087C | 0x0300 887C
ATR4_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 0880 | 0x0300 8880
ATR4_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 0884 | 0x0300 8884
ATR4_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 0888 | 0x0300 8888
ATR4_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 088C | 0x0300 888C
ATR4_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 0890 | 0x0300 8890
ATR4_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 0898 | 0x0300 8898
ATR4_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 089C | 0x0300 889C
ATR5_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 08A0 | 0x0300 88A0
ATR5_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 08A4 | 0x0300 88A4
ATR5_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 08A8 | 0x0300 88A8
ATR5_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 08AC | 0x0300 88AC
ATR5_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 08B0 | 0x0300 88B0
ATR5_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 08B8 | 0x0300 88B8
ATR5_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 08BC | 0x0300 88BC
ATR6_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 08C0 | 0x0300 88C0
ATR6_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 08C4 | 0x0300 88C4
ATR6_AXI4_SLV0_TRSL_ADDR_LSB | RW | 32 | 0x0000 0000 | 0x000 08C8 | 0x0300 88C8
ATR6_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 08CC | 0x0300 88CC
ATR6_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 08D0 | 0x0300 88D0
ATR6_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 08D8 | 0x0300 88D8
ATR6_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 08DC | 0x0300 88DC
ATR7_AXI4_SLV0_SRCADDR_PARAM | RW | 32 | 0x0000 0000 | 0x000 08E0 | 0x0300 88E0
ATR7_AXI4_SLV0_SRC_ADDR | RW | 32 | 0x0000 0000 | 0x000 08E4 | 0x0300 88E4
ATR7_AXI4_SLV0_TRSL_ADDR_LDW | RW | 32 | 0x0000 0000 | 0x000 08E8 | 0x0300 88E8
ATR7_AXI4_SLV0_TRSL_ADDR_UDW | RW | 32 | 0x0000 0000 | 0x000 08EC | 0x0300 88EC
ATR7_AXI4_SLV0_TRSL_PARAM | RW | 32 | 0x0000 0000 | 0x000 08F0 | 0x0300 88F0
ATR7_AXI4_SLV0_TRSL_MASK_DW0 | RO | 32 | 0x0000 0000 | 0x000 08F8 | 0x0300 88F8
ATR7_AXI4_SLV0_TRSL_MASK_DW1 | RO | 32 | 0x0000 0000 | 0x000 08FC | 0x0300 88FC

## PF_PCIE_BRIDGE Register Descriptions

### PF_PCIE_BRIDGE : BRIDGE_VER

Address offset | 0x000 0000
Physical address | 0x0300 4000 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8000 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Bridge IP Version & Revision
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 |  | RO | 0x0
27:24 | DMA_NUM | Indicates the number of DMA Engines implemented in the Core. | RO | 0x2
23:12 | PRODUCT_ID | Provides the Bridge IP Product ID, equal to 12?h511 | RO | 0x511
11:0 | VERSION | Provides the Bridge IP Core version | RO | 0x154

### PF_PCIE_BRIDGE : BRIDGE_BUS

Address offset | 0x000 0004
Physical address | 0x0300 4004 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8004 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Bridge Internal Bus
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | MAXRREQSIZE | Provides the maximum Read Request Size of the Bridge Internal Bus | RO | 0x1
|  | Read 0x0 | [MAXRREQSIZE_128] MAXRREQSIZE Size is 128 bytes |  |
|  | Read 0x1 | [MAXRREQSIZE_256] MAXRREQSIZE Size is 256 bytes |  |
|  | Read 0x2 | [MAXRREQSIZE_512] MAXRREQSIZE Size is 512 bytes |  |
|  | Read 0x3 | [MAXRREQSIZE_1024] MAXRREQSIZE Size is 1024 bytes |  |
|  | Read 0x4 | [MAXRREQSIZE_2048] MAXRREQSIZE Size is 2048 bytes |  |
|  | Read 0x5 | [MAXRREQSIZE_4096] MAXRREQSIZE Size is 4096 bytes |  |
27:24 | MAXPAYLOAD | Provides the maximum Payload of the Bridge Internal Bus | RO | 0x1
|  | Read 0x0 | [MAXPAYLOAD_128] MAXPAYLOAD Size is 128 bytes |  |
|  | Read 0x1 | [MAXPAYLOAD_256] MAXPAYLOAD Size is 256 bytes |  |
|  | Read 0x2 | [MAXPAYLOAD_512] MAXPAYLOAD Size is 512 bytes |  |
|  | Read 0x3 | [MAXPAYLOAD_1024] MAXPAYLOAD Size is 1024 bytes |  |
|  | Read 0x4 | [MAXPAYLOAD_2048] MAXPAYLOAD Size is 2048 bytes |  |
|  | Read 0x5 | [MAXPAYLOAD_4096] MAXPAYLOAD Size is 4096 bytes |  |
23:20 | WR_OUTREQ_N | Number of outstanding write requests | RO | 0x8
|  | Read 0x8 | [OUT_WR_RQ_256] Number of Outstanding Write Requests is 256 |  |
19:16 | RD_OUTREQ_N | Number of outstanding read requests | RO | 0x8
|  | Read 0x8 | [OUT_RD_RQ_256] Number of Outstanding Read Requests is 256 |  |
15:12 | DATAPATH | Indicates the Bridge Internal Bus Data Path width: #5 indicates 256-bits | RO | 0x5
|  | Read 0x5 | [DATAPATH_256] 256-bits |  |
11:0 | VERSION | Provides the Bridge Internal Bus version; for example, | RO | 0x153

### PF_PCIE_BRIDGE : BRIDGE_IMPL_IF

Address offset | 0x000 0008
Physical address | 0x0300 4008 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8008 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Describes the Bridge implemented interface: More detailed information on PCIe Interface is provided at addresses 0x0010 - 0x001B, and more detailed information on AXI Interfaces is provided at addresses 0x0020 - 0x006F
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved24 | Reserved | RO | 0x00
23 | AXI4_STREAM_IN_3 | Indicates if AXI4 Stream In 3 Interface is implemented | RO | 0
22 | AXI4_STREAM_OUT_3 | Indicates if AXI4 Stream Out 3 Interface is implemented | RO | 0
21 | AXI4_STREAM_IN_2 | Indicates if AXI4 Stream In 2 Interface is implemented | RO | 0
20 | AXI4_STREAM_OUT_2 | Indicates if AXI4 Stream Out 2 Interface is implemented | RO | 0
19 | AXI4_STREAM_IN_1 | Indicates if AXI4 Stream In 1 Interface is implemented | RO | 0
18 | AXI4_STREAM_OUT_1 | Indicates if AXI4 Stream Out 1 Interface is implemented | RO | 0
17 | AXI4_STREAM_IN_0 | Indicates if AXI4 Stream In 0 Interface is implemented | RO | 0
16 | AXI4_STREAM_OUT_0 | Indicates if AXI4 Stream Out 0 Interface is implemented | RO | 0
15 | AXI4_SLAVE_3 | Indicates if AXI4 Slave 3 Interface is implemented | RO | 0
14 | AXI4_MASTER_3 | Indicates if AXI4 Master 3 Interface is implemented | RO | 0
13 | AXI4_SLAVE_2 | Indicates if AXI4 Slave 2 Interface is implemented | RO | 0
12 | AXI4_MASTER_2 | Indicates if AXI4 Master 2 Interface is implemented | RO | 0
11 | AXI4_SLAVE_1 | Indicates if AXI4 Slave 1 Interface is implemented | RO | 0
10 | AXI4_MASTER_1 | Indicates if AXI4 Master 1 Interface is implemented | RO | 0
9 | AXI4_SLAVE_0 | Indicates if AXI4 Slave 0 Interface is implemented | RO | 1
8 | AXI4_MASTER_0 | Indicates if AXI4 Master 0 Interface is implemented | RO | 1
7 | reserved7 | Reserved | RO | 0
6 | AXI4_MASTER_DESCRIPTOR | Indicates if AXI4 Master Descriptor Interface is implemented | RO | 0
5 | AXI4L_SLAVE | Indicates if AXI4-Lite Slave Interface is implemented | RO | 1
4 | AXI4L_MASTER | Indicates if AXI4-Lite Master Interface is implemented | RO | 0
3 | PCIE_CONFIG | Indicates if PCIe Configuration Interface is implemented | RO | 1
2 | PCIE_IF_WINDOW_1 | Indicates if PCIe Interface Window 1 is implemented | RO | 0
1 | PCIE_IF_WINDOW_0 | Indicates if PCIe Interface Window 0 is implemented | RO | 1
0 | PCIE_IF | Indicates if PCIe Interface is implemented | RO | 1

### PF_PCIE_BRIDGE : PCIE_IF_CONF

Address offset | 0x000 0010
Physical address | 0x0300 4010 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8010 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Interface Configuration
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | MAXRREQSIZE | Provides the maximum Read Request Size of the PCIe Interface | RO | 0x1
|  | Read 0x0 | [MAXRREQSIZE_128] MAXRREQSIZE Size is 128 bytes |  |
|  | Read 0x1 | [MAXRREQSIZE_256] MAXRREQSIZE Size is 256 bytes |  |
|  | Read 0x2 | [MAXRREQSIZE_512] MAXRREQSIZE Size is 512 bytes |  |
|  | Read 0x3 | [MAXRREQSIZE_1024] MAXRREQSIZE Size is 1024 bytes |  |
|  | Read 0x4 | [MAXRREQSIZE_2048] MAXRREQSIZE Size is 2048 bytes |  |
|  | Read 0x5 | [MAXRREQSIZE_4096] MAXRREQSIZE Size is 4096 bytes |  |
27:24 | MAXPAYLOAD | Provides the maximum Payload of the PCIe Interface | RO | 0x1
|  | Read 0x0 | [MAXPAYLOAD_128] MAXPAYLOAD Size is 128 bytes |  |
|  | Read 0x1 | [MAXPAYLOAD_256] MAXPAYLOAD Size is 256 bytes |  |
|  | Read 0x2 | [MAXPAYLOAD_512] MAXPAYLOAD Size is 512 bytes |  |
|  | Read 0x3 | [MAXPAYLOAD_1024] MAXPAYLOAD Size is 1024 bytes |  |
|  | Read 0x4 | [MAXPAYLOAD_2048] MAXPAYLOAD Size is 2048 bytes |  |
|  | Read 0x5 | [MAXPAYLOAD_4096] MAXPAYLOAD Size is 4096 bytes |  |
23:20 | P2B_MRD_OUTREQ_N | Number of Outstanding Read Requests from the PCIe domain the Bridge can handle simultaneously | RO | 0x4
|  | Read 0x0 | [OUT_RD_RQ_1] 1 Outstanding Read Request |  |
|  | Read 0x1 | [OUT_RD_RQ_2] 2 Outstanding Read Requests |  |
|  | Read 0x2 | [OUT_RD_RQ_4] 4 Outstanding Read Requests |  |
|  | Read 0x3 | [OUT_RD_RQ_8] 8 Outstanding Read Requests |  |
|  | Read 0x4 | [OUT_RD_RQ_16] 16 Outstanding Read Requests |  |
|  | Read 0x5 | [OUT_RD_RQ_32] 32 Outstanding Read Requests |  |
|  | Read 0x6 | [OUT_RD_RQ_64] 64 Outstanding Read Requests |  |
|  | Read 0x7 | [OUT_RD_RQ_128] 128 Outstanding Read Requests |  |
19:16 | B2P_MRD_OUTREQ_N | Number of Outstanding Read Requests the Bridge can issue to the PCIe domain | RO | 0x4
|  | Read 0x0 | [OUT_RD_RQ_1] 1 Outstanding Read Request |  |
|  | Read 0x1 | [OUT_RD_RQ_2] 2 Outstanding Read Requests |  |
|  | Read 0x2 | [OUT_RD_RQ_4] 4 Outstanding Read Requests |  |
|  | Read 0x3 | [OUT_RD_RQ_8] 8 Outstanding Read Requests |  |
|  | Read 0x4 | [OUT_RD_RQ_16] 16 Outstanding Read Requests |  |
|  | Read 0x5 | [OUT_RD_RQ_32] 32 Outstanding Read Requests |  |
|  | Read 0x6 | [OUT_RD_RQ_64] 64 Outstanding Read Requests |  |
|  | Read 0x7 | [OUT_RD_RQ_128] 128 Outstanding Read Requests |  |
15:12 | IF_ID | Provides the ID used to target this interface. This ID is used to specify the TRSL_ID fields of the DMA Engines and Address Translation registers (see Section 17.6) | RO | 0x0
|  | Read 0x0 | [IF_ID_0] ID number 0 is used to target this interface. |  |
11:0 | VERSION | Provides the PCI Express Controller Core version | RO | 0x170

### PF_PCIE_BRIDGE : PCIE_BASIC_CONF

Address offset | 0x000 0014
Physical address | 0x0300 4014 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8014 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe IP Basic Configuration. Note: Several LINK_WIDTH_[] can be asserted at the same time, same applies to LINK_SPEED_[].
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | TYPE | Advertises the PCI Express Core type | RO | 0x0
|  | Read 0x0 | [ENDPOINT] Native EndPoint |  |
|  | Read 0x1 | [ROOTPORT] Root Port |  |
27:24 | COMPL | Advertises the Core compliance to PCI Express 3.1 specification. The only supported value is 4'h3; other values are reserved. | RO | 0x3
23:20 | VC_NUM | Advertises the number of Virtual Channels implemented in the Core. The only supported value is 4'h; other values are reserved | RO | 0x1
19:16 | FUNC_NUM | Advertises the number of functions implemented in the Core. Supported values are between 4'h1 and 4'h8. Other values are reserved. | RO | 0x1
15:11 | reserved11 |  | RO | 0x00
10 | LINK_SPEED_8G | 8.0 Gbps link speed is supported | RO | 0
9 | LINK_SPEED_5G | 5.0 Gbps link speed is supported | RO | 1
8 | LINK_SPEED_2p5G | 2.5 Gbps link speed is supported | RO | 1
7:4 | reserved4 |  | RO | 0x0
3 | LINK_WIDTH_x8 | Advertises the supported link width: x8 configuration is supported | RO | 0
2 | LINK_WIDTH_x4 | Advertises the supported link width: x4 configuration is supported | RO | 1
1 | LINK_WIDTH_x2 | Advertises the supported link width: x2 configuration is supported | RO | 1
0 | LINK_WIDTH_x1 | Advertises the supported link width: x1 configuration is supported. (This bit is always asserted.) | RO | 1

### PF_PCIE_BRIDGE : PCIE_BASIC_STATUS

Address offset | 0x000 0018
Physical address | 0x0300 4018 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8018 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe IP Basic Status
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | NEG_MAXRREQSIZE | Reports the negotiated maximum Read Request Size of the PCIe link | RO | 0x2
|  | Read 0x0 | [NEG_MAXRREQSIZE_128] Negotiated maximum read request size is 128 bytes |  |
|  | Read 0x1 | [NEG_MAXRREQSIZE_256] Negotiated maximum read request size is 256 bytes |  |
|  | Read 0x2 | [NEG_MAXRREQSIZE_512] Negotiated maximum read request size is 512 bytes |  |
|  | Read 0x3 | [NEG_MAXRREQSIZE_1024] Negotiated maximum read request size is 1024 bytes |  |
|  | Read 0x4 | [NEG_MAXRREQSIZE_2048] Negotiated maximum read request size is 2048 bytes |  |
|  | Read 0x5 | [NEG_MAXRREQSIZE_4096] Negotiated maximum read request size is 4096 bytes |  |
27:24 | NEG_MAXPAYLOAD | Reports the negotiated maximum Payload of the PCIe link. | RO | 0x0
|  | Read 0x0 | [NEG_MAXPAYLOAD_128] Negotiated maximum payload of the PCIe link is 128 Bytes |  |
|  | Read 0x1 | [NEG_MAXPAYLOAD_256] Negotiated maximum payload of the PCIe link is 256 Bytes |  |
|  | Read 0x2 | [NEG_MAXPAYLOAD_512] Negotiated maximum payload of the PCIe link is 512 Bytes |  |
|  | Read 0x3 | [NEG_MAXPAYLOAD_1024] Negotiated maximum payload of the PCIe link is 1024 Bytes |  |
|  | Read 0x4 | [NEG_MAXPAYLOAD_2048] Negotiated maximum payload of the PCIe link is 2048 Bytes |  |
|  | Read 0x5 | [NEG_MAXPAYLOAD_4096] Negotiated maximum payload of the PCIe link is 4096 Bytes |  |
23:12 | reserved12 |  | RO | 0x000
11:8 | NEG_LINK_SPEED | Reports the negotiated link speed of the PCIe link. Supported values are: | RO | 0x1
|  | Read 0x1 | [NEG_LINK_SPEED_2p5G] Negotiated Link speed of the PCIe link is 2.5 Gbps |  |
|  | Read 0x2 | [NEG_LINK_SPEED_5G] Negotiated Link speed of the PCIe link is 5.0 Gbps |  |
|  | Read 0x3 | [NEG_LINK_SPEED_8G] Negotiated Link speed of the PCIe link is 8.0 Gbps |  |
7:0 | NEG_LINK_WIDTH | Reports the negotiated link width of the PCIe link. Supported values are: | RO | 0x00
|  | Read 0x01 | [NEG_LINK_WIDTH_x1] Negotiated Link Width of the PCIe link is x1 |  |
|  | Read 0x02 | [NEG_LINK_WIDTH_x2] Negotiated Link Width of the PCIe link is x2 |  |
|  | Read 0x04 | [NEG_LINK_WIDTH_x4] Negotiated Link Width of the PCIe link is x4 |  |
|  | Read 0x08 | [NEG_LINK_WIDTH_x8] Negotiated Link Width of the PCIe link is x8 |  |
|  | Read 0x10 | [NEG_LINK_WIDTH_x16] Negotiated Link Width of the PCIe link is x16 |  |

### PF_PCIE_BRIDGE : AXI_SLVL_CONF

Address offset | 0x000 0024
Physical address | 0x0300 4024 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8024 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | AXI4-Lite Slave Interface Configuration
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | MAXRREQSIZE | Provides the maximum Read Request Size of the AXI Interface | RO | 0xB
|  | Read 0xB | [MAXRREQSIZE_4] MAXRREQSIZE Size is 4 bytes |  |
27:24 | MAXPAYLOAD | Provides the maximum Payload of the AXI Interface | RO | 0xB
|  | Read 0xB | [MAXPAYLOAD_4] MAXPAYLOAD Size is 4 bytes |  |
23:20 | WR_OUTREQ_N | Number of outstanding write requests | RO | 0x0
|  | Read 0x0 | [WR_OUTREQ_N_1] Supports one outstanding write request |  |
19:16 | RD_OUTREQ_N | Number of outstanding read requests | RO | 0x0
|  | Read 0x0 | [RD_OUTREQ_N_1] Supports one outstanding read request |  |
15:12 | DATA_PATH | Provides the AXI interface Data Path Width | RO | 0x2
|  | Read 0x2 | [DATA_PATH_32] Supported AXI interface Data Path Width is 32 bits |  |
11:8 | CLK_DOM | Sets the Clock Domain of the AXI interface | RO | 0x1
|  | Read 0x1 | [CLK_DOM_CDC] CDC is implemented |  |
7:4 | IF_ID | Provides the ID used to target this interface: 2. This ID is used to specify the TRSL_ID fields of the DMA Engines and Address Translation registers | RO | 0x2
3:0 | IF_TYPE | Specifies the AXI Interface type | RO | 0x1
|  | Read 0x1 | [IF_TYPE_M] AXI4-Lite Slave |  |

### PF_PCIE_BRIDGE : AXI_MST0_CONF

Address offset | 0x000 0030
Physical address | 0x0300 4030 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8030 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | AXI4 Master 0 Interface Configuration
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | MAXRREQSIZE | Provides the maximum Read Request Size of the AXI Interface | RO | 0x1
|  | Read 0x0 | [MAXRREQSIZE_128] MAXRREQSIZE Size is 128 bytes |  |
|  | Read 0x1 | [MAXRREQSIZE_256] MAXRREQSIZE Size is 256 bytes |  |
|  | Read 0x2 | [MAXRREQSIZE_512] MAXRREQSIZE Size is 512 bytes |  |
|  | Read 0x3 | [MAXRREQSIZE_1024] MAXRREQSIZE Size is 1024 bytes |  |
|  | Read 0x4 | [MAXRREQSIZE_2048] MAXRREQSIZE Size is 2048 bytes |  |
|  | Read 0x5 | [MAXRREQSIZE_4096] MAXRREQSIZE Size is 4096 bytes |  |
27:24 | MAXPAYLOAD | Provides the maximum Payload of the AXI Interface | RO | 0x1
|  | Read 0x0 | [MAXPAYLOAD_128] MAXPAYLOAD Size is 128 bytes |  |
|  | Read 0x1 | [MAXPAYLOAD_256] MAXPAYLOAD Size is 256 bytes |  |
|  | Read 0x2 | [MAXPAYLOAD_512] MAXPAYLOAD Size is 512 bytes |  |
|  | Read 0x3 | [MAXPAYLOAD_1024] MAXPAYLOAD Size is 1024 bytes |  |
|  | Read 0x4 | [MAXPAYLOAD_2048] MAXPAYLOAD Size is 2048 bytes |  |
|  | Read 0x5 | [MAXPAYLOAD_4096] MAXPAYLOAD Size is 4096 bytes |  |
23:20 | WR_OUTREQ_N | Maximum number of outstanding write requests. This is a static value of embedded IP core | RO | 0x8
|  | Read 0x0 | [WR_OUTREQ_N_1] Supports 1 outstanding write request |  |
|  | Read 0x1 | [WR_OUTREQ_N_2] Supports 2 outstanding write request |  |
|  | Read 0x2 | [WR_OUTREQ_N_4] Supports 4 outstanding write request |  |
|  | Read 0x3 | [WR_OUTREQ_N_8] Supports 8 outstanding write request |  |
|  | Read 0x4 | [WR_OUTREQ_N_16] Supports 16 outstanding write request |  |
19:16 | RD_OUTREQ_N | Maximum number of outstanding read requests. This is a static value of embedded IP core | RO | 0x8
|  | Read 0x0 | [RD_OUTREQ_N_1] Supports 1 outstanding read request |  |
|  | Read 0x1 | [RD_OUTREQ_N_2] Supports 2 outstanding read request |  |
|  | Read 0x2 | [RD_OUTREQ_N_4] Supports 4 outstanding read request |  |
|  | Read 0x3 | [RD_OUTREQ_N_8] Supports 8 outstanding read request |  |
|  | Read 0x4 | [RD_OUTREQ_N_16] Supports 16 outstanding read request |  |
15:12 | DATA_PATH | Provides the AXI interface Data Path Width | RO | 0x3
|  | Read 0x3 | [DATA_PATH_64] Supported AXI interface Data Path Width is 64 bits |  |
|  | Read 0x4 | [DATA_PATH_128] Supported AXI interface Data Path Width is 128 bits |  |
|  | Read 0x5 | [DATA_PATH_256] Supported AXI interface Data Path Width is 256 bits |  |
11:8 | CLK_DOM | Sets the Clock Domain of the AXI interface | RO | 0x4
|  | Read 0x0 | [CLK_DOM_0] CDC is bypassed |  |
|  | Read 0x1 | [CLK_DOM_1] CDC is implemented with fifo depth equal to 2 |  |
|  | Read 0x2 | [CLK_DOM_2] CDC is implemented with fifo depth equal to 4 |  |
|  | Read 0x3 | [CLK_DOM_3] CDC is implemented with fifo depth equal to 8 |  |
|  | Read 0x4 | [CLK_DOM_4] CDC is implemented with fifo depth equal to 16 |  |
7:4 | IF_ID | Provides the ID used to target this interface. This ID is used to specify the SRC/DEST_ID, SG/SG2_ID and the TRSL_ID fields of the DMA Engines and Address Translation registers | RO | 0x4
|  | Read 0x4 | [IF_ID_4] ID number 4 is used to target this interface. |  |
3:0 | IF_TYPE | Specifies the AXI Interface type | RO | 0x2
|  | Read 0x2 | [IF_TYPE_AXI4M] AXI4 Master |  |
|  | Read 0x6 | [IF_TYPE_AXI3M] AXI3 Master |  |

### PF_PCIE_BRIDGE : AXI_SLV0_CONF

Address offset | 0x000 0034
Physical address | 0x0300 4034 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8034 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | AXI4 Slave 0 Interface Configuration
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | MAXRREQSIZE | Provides the maximum Read Request Size of the AXI Interface | RO | 0x4
|  | Read 0x0 | [MAXRREQSIZE_128] MAXRREQSIZE Size is 128 bytes |  |
|  | Read 0x1 | [MAXRREQSIZE_256] MAXRREQSIZE Size is 256 bytes |  |
|  | Read 0x2 | [MAXRREQSIZE_512] MAXRREQSIZE Size is 512 bytes |  |
|  | Read 0x3 | [MAXRREQSIZE_1024] MAXRREQSIZE Size is 1024 bytes |  |
|  | Read 0x4 | [MAXRREQSIZE_2048] MAXRREQSIZE Size is 2048 bytes |  |
|  | Read 0x5 | [MAXRREQSIZE_4096] MAXRREQSIZE Size is 4096 bytes |  |
27:24 | MAXPAYLOAD | Provides the maximum Payload of the AXI Interface | RO | 0x4
|  | Read 0x0 | [MAXPAYLOAD_128] MAXPAYLOAD Size is 128 bytes |  |
|  | Read 0x1 | [MAXPAYLOAD_256] MAXPAYLOAD Size is 256 bytes |  |
|  | Read 0x2 | [MAXPAYLOAD_512] MAXPAYLOAD Size is 512 bytes |  |
|  | Read 0x3 | [MAXPAYLOAD_1024] MAXPAYLOAD Size is 1024 bytes |  |
|  | Read 0x4 | [MAXPAYLOAD_2048] MAXPAYLOAD Size is 2048 bytes |  |
|  | Read 0x5 | [MAXPAYLOAD_4096] MAXPAYLOAD Size is 4096 bytes |  |
23:20 | WR_OUTREQ_N | Number of outstanding write requests | RO | 0x4
|  | Read 0x0 | [WR_OUTREQ_N_1] Supports 1 outstanding write request |  |
|  | Read 0x1 | [WR_OUTREQ_N_2] Supports 2 outstanding write request |  |
|  | Read 0x2 | [WR_OUTREQ_N_4] Supports 4 outstanding write request |  |
|  | Read 0x3 | [WR_OUTREQ_N_8] Supports 8 outstanding write request |  |
|  | Read 0x4 | [WR_OUTREQ_N_16] Supports 16 outstanding write request |  |
19:16 | RD_OUTREQ_N | Number of outstanding read requests | RO | 0x4
|  | Read 0x0 | [RD_OUTREQ_N_1] Supports 1 outstanding read request |  |
|  | Read 0x1 | [RD_OUTREQ_N_2] Supports 2 outstanding read request |  |
|  | Read 0x2 | [RD_OUTREQ_N_4] Supports 4 outstanding read request |  |
|  | Read 0x3 | [RD_OUTREQ_N_8] Supports 8 outstanding read request |  |
|  | Read 0x4 | [RD_OUTREQ_N_16] Supports 16 outstanding read request |  |
15:12 | DATA_PATH | Provides the AXI interface Data Path Width | RO | 0x3
|  | Read 0x3 | [DATA_PATH_64] Supported AXI interface Data Path Width is 64 bits |  |
|  | Read 0x4 | [DATA_PATH_128] Supported AXI interface Data Path Width is 128 bits |  |
|  | Read 0x5 | [DATA_PATH_256] Supported AXI interface Data Path Width is 256 bits |  |
11:8 | CLK_DOM | Sets the Clock Domain of the AXI interface | RO | 0x4
|  | Read 0x0 | [CLK_DOM_0] CDC is bypassed |  |
|  | Read 0x1 | [CLK_DOM_1] CDC is implemented with fifo depth equal to 2 |  |
|  | Read 0x2 | [CLK_DOM_2] CDC is implemented with fifo depth equal to 4 |  |
|  | Read 0x3 | [CLK_DOM_3] CDC is implemented with fifo depth equal to 8 |  |
|  | Read 0x4 | [CLK_DOM_4] CDC is implemented with fifo depth equal to 16 |  |
7:4 | IF_ID | Provides the ID used to target this interface. This ID is used to specify the SRC/DEST_ID, SG/SG2_ID and the TRSL_ID fields of the DMA Engines and Address Translation registers | RO | 0x4
|  | Read 0x4 | [IF_ID_4] ID number 4 is used to target this interface. |  |
3:0 | IF_TYPE | Specifies the AXI Interface type | RO | 0x3
|  | Read 0x3 | [IF_TYPE_AXI4S] AXI4 Slave |  |
|  | Read 0x7 | [IF_TYPE_AXI3S] AXI3 Slave |  |

### PF_PCIE_BRIDGE : GEN_SETTINGS

Address offset | 0x000 0080
Physical address | 0x0300 4080 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8080 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Bridge general settings. When these register?s bits are not hardwired by Core Constants, they are read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:21 | reserved21 | Reserved | RW | 0x000
20 | SRIS_MODE | Indicates that the device is operating in SRIS mode. | RW | 0
19 | ERROR | Nullify TLP when TX ECC/parity error is detected. | RW | 0
18 | reserved18 | reserved | RW | 0
17 | PIE_8_MODE | Datapath PIE-8 compatibility mode. When set, the Core's PHY data interface conforms to the PIE-8 1.00 specification, which means that: the Core does not perform data scrambling/descrambling at 8.0 Gbps speed. RxDataK/TxDataK are used instead of RxDataValid/TxDataValid at 8.0 Gbps speed. RxStatus encoding differs from the PIPE specification | RW | 0
16 | RXELECIDLE | Use RXELECIDLE to detect electrical idle entry | RW | 1
15 | LANE_REVERSAL | Lane reversal supported | RW | 1
14 | EQUPHASE_23 | For downstream ports: setting this bit makes the Core execute phases 2/3; otherwise these phases are skipped. ? For upstream ports: setting this bit makes the Core perform remote transmitter adjustment during phase 2; otherwise the Core does not perform adjustment during this phase. | RW | 0
13 | SPEED_8G | 8.0 Gbps supported | RW | 0
12 | SPEED_5G | 5.0 Gbps supported | RW | 1
11 | LINK_WIDTH_x16 | Link width x16 is supported | RW | 0
10 | LINK_WIDTH_x8 | Link width x8 is supported | RW | 0
9 | LINK_WIDTH_x4 | Link width x4 is supported | RW | 1
8 | LINK_WIDTH_x2 | Link width x2 is supported | RW | 1
7:1 | reserved1 | reserved | RW | 0x00
0 | PORT_TYPE | PCIe port type. 0 => Native Endpoint, 1=>Rootport | RW | 0

### PF_PCIE_BRIDGE : PCIE_CFGCTRL

Address offset | 0x000 0084
Physical address | 0x0300 4084 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8084 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe IP Configuration Control: When the PCIe controller is in Endpoint mode and certain of the PCIe configuration setting?s registers (0x008C - 0x013F) are read/write , the local processor (on the AXI domain) must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:27 | reserved27 | Reserved | RW | 0x00
26:24 | VIRTUAL_CH_NUM | When several virtual channels are implemented, it enables initializing the selected virtual channel?s PCIe configuration setting registers (0x0090 - 0x0097). Otherwise this sub-field is reserved. | RW | 0x0
23:19 | reserved19 | Reserved | RW | 0x00
18:16 | FUNCTION_NUM | When several physical functions are implemented, it enables initializing the selected function?s PCIe configuration setting registers (0x0098 - 0x00BF, 0x00E0 - 0x00FF,0x0120 - 0x013F). Otherwise this sub-field is reserved. | RW | 0x0
15:1 | reserved1 | Reserved | RW | 0x0000
0 | CONF_NOTREADY | If the local processor need more time to load PCIe configuration settings, it can assert this bit until all physical function configuration settings are properly set. The PCIe Core will reply to all physical function configuration requests with Configuration Retry Status completions while this bit is asserted | RW | 0

### PF_PCIE_BRIDGE : PCIE_PIPE_DW0

Address offset | 0x000 0088
Physical address | 0x0300 4088 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8088 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe optional pipeline settings bits [31:0]
Type | RO

Bits | Field Name | Description | Type | Reset
31:29 | reserved29 | Reserved | RO | 0x1
28 | DLLP_INS_TLP_ALEN_DISBALE | DLLP Insertion with TLP of atypical length is disabled | RO | 0
27:21 | reserved21 | Reserved | RO | 0x00
20 | OS_DET_PIPE | De-Scrambled Data and 128b/130b OS Detection signals are pipelined | RO | 0
19 | DC_OFFSET_PIPE | DC offset calculation is pipelined | RO | 0
18 | Tx_ALIGN_DATA_PIPE | Tx aligned data is pipelined.Note: When this bit is set, the TS1/TS2 DC symbol replacement logic is slightly modified to enable the logic to run at a much higher frequency. In this case, however, it no longer conforms exactly to the PCI Express specifications. | RO | 0
17 | PIPE_INPUT | PIPE input signals are registered | RO | 0
16:0 | reserved0 | Reserved | RO | 0x0 0000

### PF_PCIE_BRIDGE : PCIE_PIPE_DW1

Address offset | 0x000 008C
Physical address | 0x0300 408C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 808C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe optional pipeline settings bits [63:32]
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | reserved62 | Reserved | RO | 0x0
29 | TLP_PIPE | TLP Decoding signals are pipelined | RO | 0
28 | RxLCRC_CHECK_PIPE | RxLCRC Checking Result is pipelined | RO | 0
27 | RXLCRC_DWORD2CHECK_PIPE | RxLCRC DWord to check is pipelined | RO | 1
26 | RxLCRC_RESULT_PIPE | RxLCRC Results are pipelined | RO | 0
25 | SEQ_RXL_DATA_PIPE | SeqNumber and RxLCRC Data XOR Computation are pipelined | RO | 0
24 | TLP_DEC_IN_DATA_PIPE | TLP decoder input data are pipelined | RO | 0
23:11 | reserved43 | Reserved | RO | 0x0000
10 | RxLCRC_FC_PIPE | RxLCRC Field Computation is pipelined (for ECRC only) | RO | 0
9 | TxLCRC_FG_PIPE | TxLCRC Field Generation is pipelined | RO | 0
8 | TxLCRC_DATA_XOR_PIPE | TxLCRC Data Xor Computation is pipelined | RO | 0
7:1 | reserved33 | Reserved?? Need to confirm | RO | 0x00
0 | DLLP_STATUS_STBUS_PIPE | DLLP Status StreamBus signals are pipelined | RO | 1

### PF_PCIE_BRIDGE : PCIE_VC_CRED_DW0

Address offset | 0x000 0090
Physical address | 0x0300 4090 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8090 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe available Credit Settings (per virtual channel) bits [31:0]. When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | NP_DATA_CREDITS | Non-Posted data credits(lower 4 bits) | RW | 0x1
27:20 | NP_HDR_CREDITS | Non-Posted header credits | RW | 0x00
19:8 | P_DATA_CREDITS | Posted data credits | RW | 0x0B8
7:0 | P_HDR_CREDITS | Posted header credits | RW | 0x18

### PF_PCIE_BRIDGE : PCIE_VC_CRED_DW1

Address offset | 0x000 0094
Physical address | 0x0300 4094 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8094 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe available Credit Settings (per virtual channel) bits [63:32]. When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | reserved56 | reserved | RW | 0x00
23:12 | CPL_DATA_CREDITS | Completion data credits | RW | 0x000
11:4 | CPL_HDR_CREDITS | Completion header credits | RW | 0x00
3:0 | NP_DATA_CREDITS | Non-Posted data credits (upper 4 bits) | RW | 0x1

### PF_PCIE_BRIDGE : PCIE_PCI_IDS_DW0

Address offset | 0x000 0098
Physical address | 0x0300 4098 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8098 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe PCI Standard Configuration Identification Settings (bits [31:0]): (per function number).When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | DEVICE_ID | Device ID | RW | 0x1100
15:0 | VENDOR_ID | Vendor ID | RW | 0x1556

### PF_PCIE_BRIDGE : PCIE_PCI_IDS_DW1

Address offset | 0x000 009C
Physical address | 0x0300 409C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 809C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe PCI Standard Configuration Identification Settings(bits [63:32]): (per function number).When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | CLASS_CODE | Class code | RW | 0xFF00
7:0 | REVISION_ID | Revision ID | RW | 0x0001

### PF_PCIE_BRIDGE : PCIE_PCI_IDS_DW2

Address offset | 0x000 00A0
Physical address | 0x0300 40A0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80A0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe PCI Standard Configuration Identification Settings(bits[95:64]): (per function number).When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | SS_DEVICE_ID | Sub-system device ID | RW | 0x1100
15:0 | SS_VENDOR_ID | Sub-system vendor ID | RW | 0x1556

### PF_PCIE_BRIDGE : PCIE_PCI_LPM

Address offset | 0x000 00A4
Physical address | 0x0300 40A4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80A4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe PCI Legacy Power Management Settings: (per function number). When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:27 | PME_SUPPORT | PME support | RW | 0x1F
26 | D2_SUPPORT | D2 support | RW | 1
25 | D1_SUPPORT | D1 support | RW | 1
24:22 | AUX_CURRENT | Auxiliary current | RW | 0x0
21 | DSI | DSI | RW | 0
20:18 | reserved18 | Reserved | RW | 0x0
17 | PRI_SUPPORT | Page Request Interface support | RO | 0
16 | ATS_SUPPORT | Address Translation Service support | RO | 0
15:0 | reserved0 | Reserved | RW | 0x0000

### PF_PCIE_BRIDGE : PCIE_PCI_IRQ_DW0

Address offset | 0x000 00A8
Physical address | 0x0300 40A8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80A8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe PCI Interrupt, MSI and MSI-X Settings: bits[31:0](per function number) When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | MSIX_CAP | Implement MSI-X capability | RW | 1
30:27 | reserved27 | Reserved | RW | 0x0
26:16 | TABLE_SIZE | Table size | RW | 0x000
15:8 | reserved8 | Reserved | RW | 0x00
7 | MSI_MASK_SUPPORT | MSI per-vector masking support | RW | 0
6:4 | NUM_MSI_MSGS | Number of MSI messages (000:1,...,101:32) | RW | 0x5
3 | reserved3 | Reserved | RW | 0
2:0 | INT_PIN | Interrupt Pin | RW | 0x4
|  | 0x0 | [NONE] None |  |
|  | 0x1 | [INT_A] INTA |  |
|  | 0x2 | [INT_B] INTB |  |
|  | 0x3 | [INT_C] INTC |  |
|  | 0x4 | [INT_D] INTD |  |

### PF_PCIE_BRIDGE : PCIE_PCI_IRQ_DW1

Address offset | 0x000 00AC
Physical address | 0x0300 40AC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80AC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe PCI Interrupt, MSI and MSI-X Settings: bits [63:32] (per function number) When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | TABLE_OFFSET | Table offset | RW | 0x0000 0000
2:0 | TABLE_BIR | Table BIR | RW | 0x0

### PF_PCIE_BRIDGE : PCIE_PCI_IRQ_DW2

Address offset | 0x000 00B0
Physical address | 0x0300 40B0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80B0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe PCI Interrupt, MSI and MSI-X Settings:bits [95:64] (per function number) When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | PBA_OFFSET | PBA offset | RW | 0x0000 0000
2:0 | PBA_BIR | PBA BIR | RW | 0x0

### PF_PCIE_BRIDGE : PCIE_PCI_IOV_DW0

Address offset | 0x000 00B4
Physical address | 0x0300 40B4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80B4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Address Translation Service and PRI Settings: bits[31:0] When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved6 | Reserved | RW | 0x000 0000
5 | ATS_PAGE_ALGN_REQ | ATS page aligned request —Not applicable for root port | RW | 0
4:0 | ATS_INVLD_QUEUE_DEPTH | ATS invalidate queue depth—Not applicable for root port | RW | 0x0A

### PF_PCIE_BRIDGE : PCIE_PCI_IOV_DW1

Address offset | 0x000 00B8
Physical address | 0x0300 40B8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80B8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Address Translation Service and PRI Settings: bits[63:32]When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | PRI_PAGE_REQ_CAP | PRI outstanding page request capacity—Not applicable for root port | RW | 0x0000 0000

### PF_PCIE_BRIDGE : PCIE_PEX_DEV

Address offset | 0x000 00C0
Physical address | 0x0300 40C0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80C0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Device Capabilities Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:29 | reserved29 | Reserved | RW | 0x0
28 | FLR_CAP | Function-level reset capability | RO | 0
27:12 | reserved12 | Reserved | RW | 0x0000
11:9 | EP_L1_LATENCY | Endpoint L1 acceptable latency | RW | 0x0
8:6 | EP_L0_LATENCY | Endpoint L0s acceptable latency | RW | 0x0
5 | reserved5 | Reserved | RW | 0
4:3 | reserved3 | reserved for phantom functions support | RW | 0x0
2:0 | MAXPAYLOAD | Maximum payload size. Note: Do not set the PCIe Maximum payload size to a value greater than the Bridge Maximum Payload size. | RW | 0x1

### PF_PCIE_BRIDGE : PCIE_PEX_DEV2

Address offset | 0x000 00C4
Physical address | 0x0300 40C4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80C4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Device 2 Capabilities Settings:When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved12 | reserved | RW | 0x0 0000
11 | LTR_support | Latency Tolerance Reporting mechanism support | RW | 1
10:5 | reserved5 | reserved | RW | 0x00
4 | CPL_TIMEOUT_DISABLE | Completion Timeout Disable Supported | RW | 1
3:0 | CPL_TIMEOUT_RANGE | Completion Timeout Ranges. XpressRICH3-AXI chosen Completion Timeout Values are: ? In Default Range: fixed to 50 ms in hardware and 128 誑 in simulation ? In Range A: 64 us or 4ms ? In Range B: 32 ms or 128 ms ? In Range C: 512 ms or 2 sec ? In Range D: 8 sec or 32 sec | RW | 0xF
|  | 0x0 | [NO_TIMEOUT] Completion Timeout programming not supported |  |
|  | 0x1 | [RANGE_A] Range A |  |
|  | 0x2 | [RANGE_B] Range B |  |
|  | 0x3 | [RANGE_A_B] Ranges A and B |  |
|  | 0x6 | [RANGE_B_C] Ranges B and C |  |
|  | 0x7 | [RANGE_A_B_C] Ranges A, B, and C |  |
|  | 0xE | [RANGE_B_C_D] Ranges B, C, and D |  |
|  | 0xF | [RANGE_A_B_C_D] Ranges A, B, C, and D |  |

### PF_PCIE_BRIDGE : PCIE_PEX_LINK

Address offset | 0x000 00C8
Physical address | 0x0300 40C8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80C8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Link Capabilities Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | PORT_NUM | Port Number | RW | 0x01
23:21 | reserved21 | Reserved | RW | 0x0
20 | reserved_DLL | Reserved for DLL active reporting capable support | RW | 0
19 | reserved_ERR_REPORT | Reserved for Surprise down error reporting capable support | RW | 0
18 | reserved_clk_pwr_mgt | Reserved for Clock power management support | RW | 0
17:15 | L1_EXIT_LATENCY | L1 exit latency | RW | 0x0
14:12 | L0s_EXIT_LATENCY | L0s exit latency | RW | 0x1
11 | ASPM_L1 | ASPM L1 support | RW | 1
10 | ASPM_L0s | ASPM L0s support | RW | 1
9:8 | reserved8 | Reserved | RW | 0x0
7:4 | SRIS_LWR_SKIP_RECP | SRIS Lower SKP OS Reception Supported Speeds Vector bits 3:0 | RO | 0x0
3:0 | SRIS_LWR_SKIP_GEN | SRIS Lower SKP OS Generation Supported Speeds Vector bits 3:0. | RO | 0x0

### PF_PCIE_BRIDGE : PCIE_PEX_SLOT

Address offset | 0x000 00CC
Physical address | 0x0300 40CC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80CC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Slot Capabilities Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RO

Bits | Field Name | Description | Type | Reset
31:19 | SLOT_NUM | Physical slot number | RO | 0x0000
18 | NO_CMD_CPL | No command complete support | RO | 0
17 | EM_INTERLOCK | Electromechanical interlock present | RO | 0
16:15 | SLOT_PWR_LIMIT_SCALE | Slot power limit scale | RO | 0x0
14:7 | SLOT_PWR_LIMIT_VAL | Slot power limit value | RO | 0x00
6 | HOT_PLUG_CAP | Hot-plug capable | RO | 1
5 | HOT_PLUG_SURPRISE | Hot-plug surprise | RO | 1
4 | PWR_IND_PRESENT | Power indicator present | RO | 1
3 | ATTN_IND_PRESENT | Attention indicator present | RO | 1
2 | MRL_SENSOR_PRESENT | MRL sensor present | RO | 1
1 | PWR_CNTRL_PRESENT | Power controller present | RO | 1
0 | ATTN_BUTTN_PRESENT | Attention button present | RO | 1

### PF_PCIE_BRIDGE : PCIE_PEX_ROOT_VC

Address offset | 0x000 00D0
Physical address | 0x0300 40D0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80D0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Root and VC Capabilities Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved_VC_CAP | Reserved for Virtual Channel Capabilities support | RW | 0x0000
15:1 | reserved_ROOT_CAP | Reserved for Root Capabilities support | RW | 0x0000
0 | CRS_SW_VISIBILITY | CRS Software Visibility support | RO | 1

### PF_PCIE_BRIDGE : PCIE_PEX_SPC

Address offset | 0x000 00D4
Physical address | 0x0300 40D4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80D4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Specific Capabilities Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | AER_IMPL | AER implemented | RW | 1
30:21 | reserved21 | Reserved | RW | 0x000
20:16 | DEV_NUM_RP | Device Number for Rootport | RW | 0x00
15 | RP_RCB | Rootport RCB | RW | 0
14 | LINK_SEL_DEEMPHASIS | Link selectable de-emphasis | RW | 1
13 | SLOT_CLK_CFG | Slot clock configuration (0:independent, 1:refclk) | RW | 0
12 | SLOT_REG_IMPL | Slot register implemented | RW | 1
11:0 | reserved0 | reserved | RW | 0x000

### PF_PCIE_BRIDGE : PCIE_PEX_SPC2

Address offset | 0x000 00D8
Physical address | 0x0300 40D8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80D8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Specific 2 Capabilities Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:23 | reserved23 | reserved | RW | 0x000
22:18 | ASPM_L1_DELAY | ASPM L1 entry delay (in steps of 256ns) | RO | 0x03
17:13 | ASPM_L0s_DELAY | ASPM L0s entry delay (in steps of 256ns) | RW | 0x03
12:8 | PCIE_MSI_MSG_NUM | PCI Express MSI message number | RW | 0x00
7:3 | AER_MSI_MSG_NUM | AER MSI message number | RW | 0x00
2 | ECRC_CHK | ECRC checking support | RW | 1
1 | ECRC_GEN | ECRC generation support | RW | 1
0 | reserved0 | reserved | RW | 0

### PF_PCIE_BRIDGE : PCIE_PEX_NFTS

Address offset | 0x000 00DC
Physical address | 0x0300 40DC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80DC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Number of Fast Training Sequences Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | reserved24 | reserved | RW | 0x00
23:16 | NUM_FTS_8G | Number of fast training sequences at 8.0 Gbps | RW | 0x20
15:8 | NUM_FTS_5G | Number of fast training sequences at 5.0 Gbps | RW | 0x20
7:0 | NUM_FTS_2p5G | Number of fast training sequences at 2.5 Gbps | RW | 0x20

### PF_PCIE_BRIDGE : PCIE_PEX_L1SS

Address offset | 0x000 00E0
Physical address | 0x0300 40E0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80E0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | L1 Substates Capabilities Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved24 | reserved | RO | 0x00
23:19 | T_POWER_ON_VAL | Port T_POWER_ON value | RO | 0x05
18 | reserved18 | reserved | RO | 0
17:16 | T_POWER_ON_SCALE | Port T_POWER_ON scale | RO | 0x0
15:8 | PORT_CM_RESTORE_TIME | Port common mode restore time | RO | 0x0A
7:5 | T_POWROFF_VAL | T_POWEROFF value in units of 256ns (000 = 256ns, 110 = 7*256ns) | RO | 0x0
4 | L1_PM_SUBSTATE_SUPPORT | L1 PM substates supported (the L1 PM substates capability is only implemented if this bit is set) ? Bit [7:5]: T_POWEROFF value in units of 256ns (000 = 256ns, 110 = 7*256ns) | RO | 1
3 | ASPM_L1p1_SUPPORT | ASPM L1.1 supported | RO | 1
2 | ASPM_L1p2_SUPPORT | ASPM L1.2 supported | RO | 1
1 | PCI_PM_L1p1_SUPPORT | PCI-PM L1.1 supported | RO | 0
0 | PCI_PM_L1p2_SUPPORT | PCI-PM L1.2 supported | RO | 1

### PF_PCIE_BRIDGE : PCIE_BAR_01_DW0

Address offset | 0x000 00E4
Physical address | 0x0300 40E4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80E4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe BAR 0 and 1 Settings (per function number): bits [31:0].When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | BAR_SIZE_MASK | Bar size mask | RW | 0xFFF FF00
3 | PREFETCH_OR_BAR_SIZE | IF BAR_TYPE=1 BAR size mask. If BAR_TYPE=0 prefetchable. | RW | 1
2 | ADDR_OR_BAR_SIZE | IF BAR_TYPE=1 BAR size mask. If BAR_TYPE=0 64-bit address space. | RW | 1
1 | reserved | Reserved | RW | 0
0 | BAR_TYPE | BAR type (0=memory, 1=IO) | RW | 0

### PF_PCIE_BRIDGE : PCIE_BAR_01_DW1

Address offset | 0x000 00E8
Physical address | 0x0300 40E8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80E8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe BAR 0 and 1 Settings (per function number): bits[63:32] .When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED_OR_BAR_SIZE_MASK | If BAR_TYPE=1 reserved. If BAR_TYPE=0 reserved if 32 bit, BAR size mask otherwise | RW | 0xFFFF FFFF

### PF_PCIE_BRIDGE : PCIE_BAR_23_DW0

Address offset | 0x000 00EC
Physical address | 0x0300 40EC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80EC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe BAR 2 and 3 Settings (per function number) bits [31:0]
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | BAR_SIZE_MASK | Bar size mask | RW | 0xFFF FE00
3 | PREFETCH_OR_BAR_SIZE | IF BAR_TYPE=1 BAR size mask. If BAR_TYPE=0 prefetchable. | RW | 1
2 | ADDR_OR_BAR_SIZE | IF BAR_TYPE=1 BAR size mask. If BAR_TYPE=0 64-bit address space. | RW | 1
1 | reserved | Reserved | RW | 0
0 | BAR_TYPE | BAR type (0=memory, 1=IO) | RW | 0

### PF_PCIE_BRIDGE : PCIE_BAR_23_DW1

Address offset | 0x000 00F0
Physical address | 0x0300 40F0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80F0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe BAR 2 and 3 Settings (per function number) bits[63:32]
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED_OR_BAR_SIZE_MASK | If BAR_TYPE=1 reserved. If BAR_TYPE=0 reserved if 32 bit, BAR size mask otherwise | RW | 0xFFFF FFFF

### PF_PCIE_BRIDGE : PCIE_BAR_45_DW0

Address offset | 0x000 00F4
Physical address | 0x0300 40F4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80F4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe BAR 4 and 5 Settings (per function number) bits [31:0]
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | BAR_SIZE_MASK | Bar size mask | RW | 0x000 0000
3 | PREFETCH_OR_BAR_SIZE | IF BAR_TYPE=1 BAR size mask. If BAR_TYPE=0 prefetchable. | RW | 0
2 | ADDR_OR_BAR_SIZE | IF BAR_TYPE=1 BAR size mask. If BAR_TYPE=0 64-bit address space. | RW | 0
1 | reserved | Reserved | RW | 0
0 | BAR_TYPE | BAR type (0=memory, 1=IO) | RW | 0

### PF_PCIE_BRIDGE : PCIE_BAR_45_DW1

Address offset | 0x000 00F8
Physical address | 0x0300 40F8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80F8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe BAR 4 and 5 Settings (per function number) bits [63:32]
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED_OR_BAR_SIZE_MASK | If BAR_TYPE=1 reserved. If BAR_TYPE=0 reserved if 32 bit, BAR size mask otherwise | RW | 0x0000 0000

### PF_PCIE_BRIDGE : PCIE_BAR_WIN

Address offset | 0x000 00FC
Physical address | 0x0300 40FC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 80FC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Windows Settings: (per function number). When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up. Note: This register is reserved when core is in endpoint.
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved | reserved | RW | 0x000 0000
3 | PFETCH_MEMWIN_64bADDR | Prefetchable memory window 64-bit addressing support | RW | 0
2 | PFETCH_MEMWIN | Prefetchable memory window implemented | RW | 0
1 | IOWIN_32bADDR | IO window 32-bit addressing support | RW | 0
0 | IOWIN | IO window implemented | RW | 0

### PF_PCIE_BRIDGE : PCIE_EQ_PRESET_DW0

Address offset | 0x000 0100
Physical address | 0x0300 4100 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8100 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Equalization Preset Values Settings(bits[31:0]): When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up. These values are applicable for Rootport only and are reported in the Lane Equalization Control Register of the Secondary PCI Express Extended Capability.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved140 | reserved | RW | 0
30:28 | UP_RCVR_PRST_LN1 | Lane1 Upstream port receiver preset hint | RW | 0x0
27:24 | UP_XSMR_PRST_LN1 | Lane1 Upstream port transmitter preset | RW | 0x0
23 | reserved141 | reserved | RW | 0
22:20 | DP_RCVR_PRST_LN1 | Lane1 Downstream port receiver preset hint | RW | 0x0
19:16 | DP_XSMR_PRST_LN1 | Lane1 Downstream port transmitter preset | RW | 0x0
15 | reserved150 | reserved | RW | 0
14:12 | UP_RCVR_PRST_LN0 | Lane0 Upstream port receiver preset hint | RW | 0x0
11:8 | UP_XSMR_PRST_LN0 | Lane0 Upstream port transmitter preset | RW | 0x0
7 | reserved151 | reserved | RW | 0
6:4 | DP_RCVR_PRST_LN0 | Lane0 Downstream port receiver preset hint | RW | 0x0
3:0 | DP_XSMR_PRST_LN0 | Lane0 Downstream port transmitter preset | RW | 0x0

### PF_PCIE_BRIDGE : PCIE_EQ_PRESET_DW1

Address offset | 0x000 0104
Physical address | 0x0300 4104 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8104 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Equalization Preset Values Settings(bits[63:32]): When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up. These values are applicable for Rootport only and are reported in the Lane Equalization Control Register of the Secondary PCI Express Extended Capability.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved120 | reserved | RW | 0
30:28 | UP_RCVR_PRST_LN3 | Lane3 Upstream port receiver preset hint | RW | 0x0
27:24 | UP_XSMR_PRST_LN3 | Lane3 Upstream port transmitter preset | RW | 0x0
23 | reserved121 | reserved | RW | 0
22:20 | DP_RCVR_PRST_LN3 | Lane3 Downstream port receiver preset hint | RW | 0x0
19:16 | DP_XSMR_PRST_LN3 | Lane3 Downstream port transmitter preset | RW | 0x0
15 | reserved130 | reserved | RW | 0
14:12 | UP_RCVR_PRST_LN2 | Lane2 Upstream port receiver preset hint | RW | 0x0
11:8 | UP_XSMR_PRST_LN2 | Lane2 Upstream port transmitter preset | RW | 0x0
7 | reserved131 | reserved | RW | 0
6:4 | DP_RCVR_PRST_LN2 | Lane2 Downstream port receiver preset hint | RW | 0x0
3:0 | DP_XSMR_PRST_LN2 | Lane2 Downstream port transmitter preset | RW | 0x0

### PF_PCIE_BRIDGE : PCIE_EQ_PRESET_DW2

Address offset | 0x000 0108
Physical address | 0x0300 4108 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8108 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Equalization Preset Values Settings(bits[95:64]): When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up. These values are applicable for Rootport only and are reported in the Lane Equalization Control Register of the Secondary PCI Express Extended Capability.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved100 | reserved | RW | 0
30:28 | UP_RCVR_PRST_LN5 | Lane5 Upstream port receiver preset hint | RW | 0x0
27:24 | UP_XSMR_PRST_LN5 | Lane5 Upstream port transmitter preset | RW | 0x0
23 | reserved101 | reserved | RW | 0
22:20 | DP_RCVR_PRST_LN5 | Lane5 Downstream port receiver preset hint | RW | 0x0
19:16 | DP_XSMR_PRST_LN5 | Lane5 Downstream port transmitter preset | RW | 0x0
15 | reserved110 | reserved | RW | 0
14:12 | UP_RCVR_PRST_LN4 | Lane4 Upstream port receiver preset hint | RW | 0x0
11:8 | UP_XSMR_PRST_LN4 | Lane4 Upstream port transmitter preset | RW | 0x0
7 | reserved111 | reserved | RW | 0
6:4 | DP_RCVR_PRST_LN4 | Lane4 Downstream port receiver preset hint | RW | 0x0
3:0 | DP_XSMR_PRST_LN4 | Lane4 Downstream port transmitter preset | RW | 0x0

### PF_PCIE_BRIDGE : PCIE_EQ_PRESET_DW3

Address offset | 0x000 010C
Physical address | 0x0300 410C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 810C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Equalization Preset Values Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up. These values are applicable for Rootport only and are reported in the Lane Equalization Control Register of the Secondary PCI Express Extended Capability.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved80 | reserved | RW | 0
30:28 | UP_RCVR_PRST_LN7 | Lane7 Upstream port receiver preset hint | RW | 0x0
27:24 | UP_XSMR_PRST_LN7 | Lane7 Upstream port transmitter preset | RW | 0x0
23 | reserved81 | reserved | RW | 0
22:20 | DP_RCVR_PRST_LN7 | Lane7 Downstream port receiver preset hint | RW | 0x0
19:16 | DP_XSMR_PRST_LN7 | Lane7 Downstream port transmitter preset | RW | 0x0
15 | reserved90 | reserved | RW | 0
14:12 | UP_RCVR_PRST_LN6 | Lane6 Upstream port receiver preset hint | RW | 0x0
11:8 | UP_XSMR_PRST_LN6 | Lane6 Upstream port transmitter preset | RW | 0x0
7 | reserved91 | reserved | RW | 0
6:4 | DP_RCVR_PRST_LN6 | Lane6 Downstream port receiver preset hint | RW | 0x0
3:0 | DP_XSMR_PRST_LN6 | Lane6 Downstream port transmitter preset | RW | 0x0

### PF_PCIE_BRIDGE : PCIE_EQ_PRESET_DW4

Address offset | 0x000 0110
Physical address | 0x0300 4110 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8110 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Equalization Preset Values Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up. These values are applicable for Rootport only and are reported in the Lane Equalization Control Register of the Secondary PCI Express Extended Capability.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved60 | reserved | RW | 0
30:28 | UP_RCVR_PRST_LN9 | Lane9 Upstream port receiver preset hint | RW | 0x0
27:24 | UP_XSMR_PRST_LN9 | Lane9 Upstream port transmitter preset | RW | 0x0
23 | reserved61 | reserved | RW | 0
22:20 | DP_RCVR_PRST_LN9 | Lane9 Downstream port receiver preset hint | RW | 0x0
19:16 | DP_XSMR_PRST_LN9 | Lane9 Downstream port transmitter preset | RW | 0x0
15 | reserved70 | reserved | RW | 0
14:12 | UP_RCVR_PRST_LN8 | Lane8 Upstream port receiver preset hint | RW | 0x0
11:8 | UP_XSMR_PRST_LN8 | Lane8 Upstream port transmitter preset | RW | 0x0
7 | reserved71 | reserved | RW | 0
6:4 | DP_RCVR_PRST_LN8 | Lane8 Downstream port receiver preset hint | RW | 0x0
3:0 | DP_XSMR_PRST_LN8 | Lane8 Downstream port transmitter preset | RW | 0x0

### PF_PCIE_BRIDGE : PCIE_EQ_PRESET_DW5

Address offset | 0x000 0114
Physical address | 0x0300 4114 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8114 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Equalization Preset Values Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up. These values are applicable for Rootport only and are reported in the Lane Equalization Control Register of the Secondary PCI Express Extended Capability.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved40 | reserved | RW | 0
30:28 | UP_RCVR_PRST_LN11 | Lane11 Upstream port receiver preset hint | RW | 0x0
27:24 | UP_XSMR_PRST_LN11 | Lane11 Upstream port transmitter preset | RW | 0x0
23 | reserved41 | reserved | RW | 0
22:20 | DP_RCVR_PRST_LN11 | Lane11 Downstream port receiver preset hint | RW | 0x0
19:16 | DP_XSMR_PRST_LN11 | Lane11 Downstream port transmitter preset | RW | 0x0
15 | reserved50 | reserved | RW | 0
14:12 | UP_RCVR_PRST_LN10 | Lane10 Upstream port receiver preset hint | RW | 0x0
11:8 | UP_XSMR_PRST_LN10 | Lane10 Upstream port transmitter preset | RW | 0x0
7 | reserved51 | reserved | RW | 0
6:4 | DP_RCVR_PRST_LN10 | Lane10 Downstream port receiver preset hint | RW | 0x0
3:0 | DP_XSMR_PRST_LN10 | Lane10 Downstream port transmitter preset | RW | 0x0

### PF_PCIE_BRIDGE : PCIE_EQ_PRESET_DW6

Address offset | 0x000 0118
Physical address | 0x0300 4118 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8118 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Equalization Preset Values Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up. These values are applicable for Rootport only and are reported in the Lane Equalization Control Register of the Secondary PCI Express Extended Capability.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved20 | reserved | RW | 0
30:28 | UP_RCVR_PRST_LN13 | Lane13 Upstream port receiver preset hint | RW | 0x0
27:24 | UP_XSMR_PRST_LN13 | Lane13 Upstream port transmitter preset | RW | 0x0
23 | reserved21 | reserved | RW | 0
22:20 | DP_RCVR_PRST_LN13 | Lane13 Downstream port receiver preset hint | RW | 0x0
19:16 | DP_XSMR_PRST_LN13 | Lane13 Downstream port transmitter preset | RW | 0x0
15 | reserved30 | reserved | RW | 0
14:12 | UP_RCVR_PRST_LN12 | Lane12 Upstream port receiver preset hint | RW | 0x0
11:8 | UP_XSMR_PRST_LN12 | Lane12 Upstream port transmitter preset | RW | 0x0
7 | reserved31 | reserved | RW | 0
6:4 | DP_RCVR_PRST_LN12 | Lane12 Downstream port receiver preset hint | RW | 0x0
3:0 | DP_XSMR_PRST_LN12 | Lane12 Downstream port transmitter preset | RW | 0x0

### PF_PCIE_BRIDGE : PCIE_EQ_PRESET_DW7

Address offset | 0x000 011C
Physical address | 0x0300 411C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 811C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe Equalization Preset Values Settings: When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up. These values are applicable for Rootport only and are reported in the Lane Equalization Control Register of the Secondary PCI Express Extended Capability.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | reserved00 | reserved | RW | 0
30:28 | UP_RCVR_PRST_LN15 | Lane15 Upstream port receiver preset hint | RW | 0x0
27:24 | UP_XSMR_PRST_LN15 | Lane15 Upstream port transmitter preset | RW | 0x0
23 | reserved01 | reserved | RW | 0
22:20 | DP_RCVR_PRST_LN15 | Lane15 Downstream port receiver preset hint | RW | 0x0
19:16 | DP_XSMR_PRST_LN15 | Lane15 Downstream port transmitter preset | RW | 0x0
15 | reserved10 | reserved | RW | 0
14:12 | UP_RCVR_PRST_LN14 | Lane14 Upstream port receiver preset hint | RW | 0x0
11:8 | UP_XSMR_PRST_LN14 | Lane14 Upstream port transmitter preset | RW | 0x0
7 | reserved11 | reserved | RW | 0
6:4 | DP_RCVR_PRST_LN14 | Lane14 Downstream port receiver preset hint | RW | 0x0
3:0 | DP_XSMR_PRST_LN14 | Lane14 Downstream port transmitter preset | RW | 0x0

### PF_PCIE_BRIDGE : PCIE_SRIOV_DW0

Address offset | 0x000 0120
Physical address | 0x0300 4120 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8120 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe SR-IOV Virtual Functions Settings (bits[31:0]) Note: Virtual Functions BARs are set equal to the Physical Function BARs settings.
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | VF_SS_DEVICE_ID | VF subsystem device ID | RO | 0x0000
15:0 | VF_DEVICE_ID | VF device ID | RO | 0x0000

### PF_PCIE_BRIDGE : PCIE_SRIOV_DW1

Address offset | 0x000 0124
Physical address | 0x0300 4124 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8124 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe SR-IOV Virtual Functions Settings(bits[63:32]). Note: Virtual Functions BARs are set equal to the Physical Function BARs settings.
Type | RO

Bits | Field Name | Description | Type | Reset
31:12 | reserved44 | reserved | RO | 0x0 0000
11:0 | PAGE_SIZE | Supported page sizes (Mandatory page sizes are always supported regardless of the values specified here.) | RO | 0x000

### PF_PCIE_BRIDGE : PCIE_SRIOV_DW2

Address offset | 0x000 0128
Physical address | 0x0300 4128 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8128 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe SR-IOV Virtual Functions Settings(bits[95:64]). Note: Virtual Functions BARs are set equal to the Physical Function BARs settings.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | reserved0 | reserved | RO | 0x0000 0000

### PF_PCIE_BRIDGE : PCIE_SRIOV_DW3

Address offset | 0x000 012C
Physical address | 0x0300 412C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 812C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe SR-IOV Virtual Functions Settings(bits[127:96]). Note: Virtual Functions BARs are set equal to the Physical Function BARs settings.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | reserved0 | reserved | RO | 0x0000 0000

### PF_PCIE_BRIDGE : PCIE_SRIOV_DW4

Address offset | 0x000 0130
Physical address | 0x0300 4130 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8130 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe SR-IOV Virtual Functions Settings(bits[159:128]). Note: Virtual Functions BARs are set equal to the Physical Function BARs settings.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | reserved0 | reserved | RO | 0x0000 0000

### PF_PCIE_BRIDGE : PCIE_SRIOV_DW5

Address offset | 0x000 0134
Physical address | 0x0300 4134 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8134 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe SR-IOV Virtual Functions Settings(bits[191:160]). Note: Virtual Functions BARs are set equal to the Physical Function BARs settings.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | reserved0 | reserved | RO | 0x0000 0000

### PF_PCIE_BRIDGE : PCIE_SRIOV_DW6

Address offset | 0x000 0138
Physical address | 0x0300 4138 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8138 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe SR-IOV Virtual Functions Settings(bits[223:192]). Note: Virtual Functions BARs are set equal to the Physical Function BARs settings.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | reserved0 | reserved | RO | 0x0000 0000

### PF_PCIE_BRIDGE : PCIE_SRIOV_DW7

Address offset | 0x000 013C
Physical address | 0x0300 413C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 813C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCIe SR-IOV Virtual Functions Settings(bits[255:224]). Note: Virtual Functions BARs are set equal to the Physical Function BARs settings.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | reserved0 | reserved | RO | 0x0000 0000

### PF_PCIE_BRIDGE : PCIE_CFGNUM

Address offset | 0x000 0140
Physical address | 0x0300 4140 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8140 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When the PCIe controller is in Rootport mode, the local processor (on the AXI domain) can use the PCI Express Configuration Space of the Bridge Configuration Space to send CFG read and write requests on the PCIe interface. To do this, it configures the PCIE_CFGNUM register and accesses the desired register. This register is reserved when the Core is in Endpoint mode and only one function is implemented.
Type | RO

Bits | Field Name | Description | Type | Reset
31:21 | reserved21 | reserved | RO | 0x000
20 | FORCE_BE | When asserted, the byte enable of the CFG read or write request is forced to the BYTE_EN field value, regardless of AXI strobes. This may be required, for example, when targeting the R1C register, as there is no read strobe in the AXI protocol. | RO | 0
19:16 | BYTE_EN | CFG byte enable | RO | 0x0
15:8 | BUS_NUMBER | Bus Number | RO | 0x00
7:3 | DEVICE_NUMBER | Device Number | RO | 0x00
2:0 | FUNC_NUMBER | Function Number. When the PCIe controller is in Endpoint Mode and supports multi-functions, the local processor (on the AXI domain) sets FUNC_NUMBER to the desired value. | RO | 0x0

### PF_PCIE_BRIDGE : PM_CONF_DW0

Address offset | 0x000 0174
Physical address | 0x0300 4174 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8174 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCI Power Management Data Register (bits [31:0]): When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up. PCI Power Management Data Register provides the scaling factor and state dependent data related to the power state selected by the Data_Select field of Power Management Control and Status register:
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | DATA_SCALE_7 | The scale used to find the power consumed by a particular component when Data_Select=7. Data scale includes the following values: 00: unknown ; 01: 0.1 x ; 10: 0.01 x ; 11: 0.001 x | RW | 0x0
29:28 | DATA_SCALE_6 | The scale used to find the power consumed by a particular component when Data_Select=6. Data scale includes the following values: 00: unknown ; 01: 0.1 x ; 10: 0.01 x ; 11: 0.001 x | RW | 0x0
27:26 | DATA_SCALE_5 | The scale used to find the power consumed by a particular component when Data_Select=5. Data scale includes the following values: 00: unknown ; 01: 0.1 x ; 10: 0.01 x ; 11: 0.001 x | RW | 0x0
25:24 | DATA_SCALE_4 | The scale used to find the power consumed by a particular component when Data_Select=4. Data scale includes the following values: 00: unknown ; 01: 0.1 x ; 10: 0.01 x ; 11: 0.001 x | RW | 0x0
23:22 | DATA_SCALE_3 | The scale used to find the power consumed by a particular component when Data_Select=3. Data scale includes the following values: 00: unknown ; 01: 0.1 x ; 10: 0.01 x ; 11: 0.001 x | RW | 0x0
21:20 | DATA_SCALE_2 | The scale used to find the power consumed by a particular component when Data_Select=2. Data scale includes the following values: 00: unknown ; 01: 0.1 x ; 10: 0.01 x ; 11: 0.001 x | RW | 0x0
19:18 | DATA_SCALE_1 | The scale used to find the power consumed by a particular component when Data_Select=1. Data scale includes the following values: 00: unknown ; 01: 0.1 x ; 10: 0.01 x ; 11: 0.001 x | RW | 0x0
17:16 | DATA_SCALE_0 | The scale used to find the power consumed by a particular component when Data_Select=0. Data scale includes the following values: 00: unknown ; 01: 0.1 x ; 10: 0.01 x ; 11: 0.001 x | RW | 0x0
15:0 | reserved | Reserved | RW | 0x0000

### PF_PCIE_BRIDGE : PM_CONF_DW1

Address offset | 0x000 0178
Physical address | 0x0300 4178 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8178 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCI Power Management Data Register(bits[63:32]): When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up. PCI Power Management Data Register provides the scaling factor and state dependent data related to the power state selected by the Data_Select field of Power Management Control and Status register:
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | DATA_REGSITER_3 | Value associated with the power consumed by the component when Data_Select=3. | RW | 0x00
23:16 | DATA_REGSITER_2 | Value associated with the power consumed by the component when Data_Select=2. | RW | 0x00
15:8 | DATA_REGSITER_1 | Value associated with the power consumed by the component when Data_Select=1. | RW | 0x00
7:0 | DATA_REGSITER_0 | Value associated with the power consumed by the component when Data_Select=0. | RW | 0x00

### PF_PCIE_BRIDGE : PM_CONF_DW2

Address offset | 0x000 017C
Physical address | 0x0300 417C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 817C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCI Power Management Data Register(bits[95:64]): When this register is not hardwired by Core Constants, it is read/write and the local processor must initialize it at power-up. PCI Power Management Data Register provides the scaling factor and state dependent data related to the power state selected by the Data_Select field of Power Management Control and Status register:
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | DATA_REGSITER_7 | Value associated with the power consumed by the component when Data_Select=7. | RW | 0x00
23:16 | DATA_REGSITER_6 | Value associated with the power consumed by the component when Data_Select=6. | RW | 0x00
15:8 | DATA_REGSITER_5 | Value associated with the power consumed by the component when Data_Select=5. | RW | 0x00
7:0 | DATA_REGSITER_4 | Value associated with the power consumed by the component when Data_Select=4. | RW | 0x00

### PF_PCIE_BRIDGE : IMASK_LOCAL

Address offset | 0x000 0180
Physical address | 0x0300 4180 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8180 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When this register is not hardwired by Core Constants, it is read/write and its default value after reset is 32'h0. Setting a bit enables the associated interrupt source and clearing a bit masks the interrupt source.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | IMASK_SYS_ERR | Mask or enable the system error interrupt source (only available in root port) | RW | 0
30 | IMASK_PM_EVENTS | Mask or enable the interrupt source of PM/LTR/Hotplug event for Rootport, Legacy power management state change for Endpoint | RW | 0
29 | IMASK_AER_EVT | Mask or enable the interrupt source of AER Event (RP only, reserved for EP) | RW | 0
28 | IMASK_INT_MSI | Mask or enable the interrupt source of MSI received (RP only, reserved for EP) | RW | 0
27 | IMASK_INT_INTD | Mask or enable the interrupt source of PCI interrupt line D(RP only, reserved for EP) | RW | 0
26 | IMASK_INT_INTC | Mask or enable the interrupt source of PCI interrupt line C(RP only, reserved for EP) | RW | 0
25 | IMASK_INT_INTB | Mask or enable the interrupt source of PCI interrupt line B(RP only, reserved for EP) | RW | 0
24 | IMASK_INT_INTA | Mask or enable the interrupt source of PCI interrupt line A(RP only, reserved for EP) | RW | 0
23 | IMASK_P_ATR_EVT_DOORBELL | Mask or enable the interrupt source for PCIe Doorbell Event described in ISTATUS_LOCAL register bit 23. | RW | 0
22 | IMASK_P_ATR_EVT_DISCARD_ERR | Mask or enable the interrupt source for PCIe Discard Error Event described in ISTATUS_LOCAL register bit 22. | RW | 0
21 | IMASK_P_ATR_EVT_FETCH_ERR | Mask or enable the interrupt source for PCIe Fetch Error event described in ISTATUS_LOCAL register bit 21. | RW | 0
20 | IMASK_P_ATR_EVT_POST_ERR | Mask or enable the interrupt source for PCIe Post Error event described in ISTATUS_LOCAL register bit 20. | RW | 0
19 | IMASK_A_ATR_EVT_DOORBELL | Mask or enable the interrupt source for AXI Doorbell Event described in ISTATUS_LOCAL register bit 19. | RW | 0
18 | IMASK_A_ATR_EVT_DISCARD_ERR | Mask or enable the interrupt source for AXI Discard Error Event described in ISTATUS_LOCAL register bit 18. | RW | 0
17 | IMASK_A_ATR_EVT_FETCH_ERR | Mask or enable the interrupt source for AXI Fetch Error event described in ISTATUS_LOCAL register bit 17. | RW | 0
16 | IMASK_A_ATR_EVT_POST_ERR | Mask or enable the interrupt source for AXI Post Error event described in ISTATUS_LOCAL register bit 16. | RW | 0
15 | IMASK_DMA_ERR_ENGINE_7 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 15. | RW | 0
14 | IMASK_DMA_ERR_ENGINE_6 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 14. | RW | 0
13 | IMASK_DMA_ERR_ENGINE_5 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 13. | RW | 0
12 | IMASK_DMA_ERR_ENGINE_4 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 12. | RW | 0
11 | IMASK_DMA_ERR_ENGINE_3 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 11. | RW | 0
10 | IMASK_DMA_ERR_ENGIN_2 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 10. | RW | 0
9 | IMASK_DMA_ERR_ENGINE_1 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 9. | RW | 0
8 | IMASK_DMA_ERR_ENGINE_0 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 8. | RW | 0
7 | IMASK_DMA_END_ENGINE_7 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 7. | RW | 0
6 | IMASK_DMA_END_ENGINE_6 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 6. | RW | 0
5 | IMASK_DMA_END_ENGINE_5 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 5. | RW | 0
4 | IMASK_DMA_END_ENGINE_4 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 4. | RW | 0
3 | IMASK_DMA_END_ENGINE_3 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 3. | RW | 0
2 | IMASK_DMA_END_ENGINE_2 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 2. | RW | 0
1 | IMASK_DMA_END_ENGINE_1 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 1. | RW | 0
0 | IMASK_DMA_END_ENGINE_0 | Mask or enable the interrupt source described in ISTATUS_LOCAL register bit 0. | RW | 0

### PF_PCIE_BRIDGE : ISTATUS_LOCAL

Address offset | 0x000 0184
Physical address | 0x0300 4184 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8184 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Local Processor Interrupt Status. This is a read/write/clear register; the register?s bits are set when the corresponding interrupt source is activated. Each source is independent and thus multiple sources may be active simultaneously. The local processor can monitor and clear status bits: writing 1 clears a bit, writing 0 has no effect.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | PM_MSI_INT_SYS_ERR | System error signaled (Rootport only, reserved for Endpoint) | RW | 0
30 | PM_MSI_INT_EVENTS | PM/LTR/Hotplug event for Rootport, Legacy power management state change for Endpoint | RW | 0
29 | PM_MSI_INT_AER_EVT | AER Event (RP only, reserved for EP) | RW | 0
28 | PM_MSI_INT_MSI | MSI received (RP only, reserved for EP) | RW | 0
27 | PM_MSI_INT_INTD | Asserted when PCI interrupt line D is asserted (RP only, reserved for EP) | RW | 0
26 | PM_MSI_INT_INTC | Asserted when PCI interrupt line C is asserted (RP only, reserved for EP) | RW | 0
25 | PM_MSI_INT_INTB | Asserted when PCI interrupt line B is asserted (RP only, reserved for EP) | RW | 0
24 | PM_MSI_INT_INTA | Asserted when PCI interrupt line A is asserted (RP only, reserved for EP) | RW | 0
23 | P_ATR_EVT_DOORBELL | Asserted when a PCIe request has successfully targeted an Address Translation Table | RW | 0
22 | P_ATR_EVT_DISCARD_ERR | Asserted to signal a completion timeout on a PCIe read request | RW | 0
21 | P_ATR_EVT_FETCH_ERR | Asserted to indicate that an error occurred on a PCIe read request | RW | 0
20 | P_ATR_EVT_POST_ERR | Asserted to indicate that an error occurred on a PCIe write request | RW | 0
19 | A_ATR_EVT_DOORBELL | Asserted when an AXI request has successfully targeted an Address Translation Table | RW | 0
18 | A_ATR_EVT_DISCARD_ERR | Asserted to signal a completion timeout on an AXI read request | RW | 0
17 | A_ATR_EVT_FETCH_ERR | Asserted to indicate that an error occurred on an AXI read request | RW | 0
16 | A_ATR_EVT_POST_ERR | Asserted to indicate that an error occurred on an AXI write request | RW | 0
15 | DMA_ERROR_ENGINE_7 | Reports that an error occurred during a DMA transfer correspoding to DMA Engine 7 | RW | 0
14 | DMA_ERROR_ENGINE_6 | Reports that an error occurred during a DMA transfer correspoding to DMA Engine 6 | RW | 0
13 | DMA_ERROR_ENGINE_5 | Reports that an error occurred during a DMA transfer correspoding to DMA Engine 5 | RW | 0
12 | DMA_ERROR_ENGINE_4 | Reports that an error occurred during a DMA transfer correspoding to DMA Engine 4 | RW | 0
11 | DMA_ERROR_ENGINE_3 | Reports that an error occurred during a DMA transfer correspoding to DMA Engine 3 | RW | 0
10 | DMA_ERROR_ENGIN_2 | Reports that an error occurred during a DMA transfer correspoding to DMA Engine 2 | RW | 0
9 | DMA_ERROR_ENGINE_1 | Reports that an error occurred during a DMA transfer correspoding to DMA Engine 1 | RW | 0
8 | DMA_ERROR_ENGINE_0 | Reports that an error occurred during a DMA transfer correspoding to DMA Engine 0 | RW | 0
7 | DMA_END_ENGINE_7 | Reports that a DMA transfer is ended which corresponds to DMA engine 7 | RW | 0
6 | DMA_END_ENGINE_6 | Reports that a DMA transfer is ended which corresponds to DMA engine 6 | RW | 0
5 | DMA_END_ENGINE_5 | Reports that a DMA transfer is ended which corresponds to DMA engine 5 | RW | 0
4 | DMA_END_ENGINE_4 | Reports that a DMA transfer is ended which corresponds to DMA engine 4 | RW | 0
3 | DMA_END_ENGINE_3 | Reports that a DMA transfer is ended which corresponds to DMA engine 3 | RW | 0
2 | DMA_END_ENGINE_2 | Reports that a DMA transfer is ended which corresponds to DMA engine 2 | RW | 0
1 | DMA_END_ENGINE_1 | Reports that a DMA transfer is ended which corresponds to DMA engine 1 | RW | 0
0 | DMA_END_ENGINE_0 | Reports that a DMA transfer is ended which corresponds to DMA engine 0 | RW | 0

### PF_PCIE_BRIDGE : IMASK_HOST

Address offset | 0x000 0188
Physical address | 0x0300 4188 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8188 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | (Reserved for Rootport) When this register is not hardwired by Core Constants, it is read/write
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | INT_MASK_HOST | Setting a bit enables the associated interrupt source and clearing a bit masks the interrupt source. See ISTATUS_HOST for details of this register?s bits | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ISTATUS_HOST

Address offset | 0x000 018C
Physical address | 0x0300 418C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 818C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Host Processor Interrupt Status: (reserved for Rootport) This is a read/write/clear register; the register?s bits are automatically set when the corresponding interrupt source is activated. Each source is independent and thus multiple sources may be active simultaneously. The host processor can monitor and clear status bits: writing 1 clears a bit, writing 0 has no effect. If one or more ISTATUS_HOST interrupt sources are active and not masked by IMASK_HOST, the Bridge IP Core issues an interrupt towards the Host Processor (on the PCIe domain). The interrupt is sent using Message Signaled Interrupt if the PCI host processor has enabled MSI, otherwise INT messages are used.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | INT_REQUEST | Reports interrupt requests from the local processor to the Host Processor. | RW | 0x00
23:20 | P_ATR_EVT | Interrupt Sources as described in the corresponding bits of ISTATUS_LOCAL register | RW | 0x0
19:16 | A_ATR_EVT | Interrupt Sources as described in the corresponding bits of ISTATUS_LOCAL register | RW | 0x0
15:8 | DMA_ERROR | Interrupt Sources as described in the corresponding bits of ISTATUS_LOCAL register | RW | 0x00
7:0 | DMA_END | Interrupt Sources as described in the corresponding bits of ISTATUS_LOCAL register | RW | 0x00

### PF_PCIE_BRIDGE : IMSI_ADDR

Address offset | 0x000 0190
Physical address | 0x0300 4190 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8190 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | MSI Capture Address (reserved for Endpoint). Note that this address is 64-bit aligned (bits 2:0 are ?000?).
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | MSI_CAPTURE_ADDR | Specifies the address on which incoming MSI messages are received when the PCIe is Rootport. The Rootport captures all memory write operations at this address and treats them as MSI. | RO | 0x0000 0190

### PF_PCIE_BRIDGE : ISTATUS_MSI

Address offset | 0x000 0194
Physical address | 0x0300 4194 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8194 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | MSI Message (reserved for Endpoint). This is a read/write/clear register.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | MSI_STATUS | Bits 31-0 are asserted when an MSI with message number 31-0 is received by the Rootport. The local processor must monitor and clear these bits: writing 1 clears a bit, 0 has no effect. Note that MSI messages with numbers greater than 31 are ignored and discarded. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ICMD_PM

Address offset | 0x000 0198
Physical address | 0x0300 4198 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8198 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Event Command: Enables the local processor to activate and send events to the PCIe bus.
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | reserved9 | reserved | RW | 0x00 0000
8 | CLKREQ_CLK_CTRL | This field is used by the application to indicate when the PCI Express reference clock can be safely removed (when applicable). 0: the application does not allow the reference clock to be removed. ? 1: the application allows the reference clock to be removed. This field is not used and must be set to 0 when Clock Power Management and L1 PM substates with CLKREQ# are not implemented. | RW | 0
7:5 | reserved5 | reserved | RW | 0x0
4 | TURN_OFF_LINK | (RP only, reserved for EP) The local processor can send a Turn Off Link command in order to start L2 state entry negotiation. If the Endpoint device is also ready to enter this state, then both devices will enter L2 state and this link will be turned off. Deasserting this signal forces the Core to exit L2 state and wakes the link. | RW | 0
3:1 | reserved1 | reserved | RW | 0x0
0 | SEND_PME | Send PME (EP only, reserved for RP): Local processor can write 1 to send PME bit command in order to generate a PME# event on the PCI Express link. This is used to ask PCI host processor to restore bridge to a fully functional legacy power state. Note that this bit is immediately cleared by the XpressRICH3-AXI Core: the local processor does not need to clear it.Note that the PME_En bit in the Power Management Control/Status register should be set to 1b to enable PME# to be asserted (see Section A.1.4). | RW | 0

### PF_PCIE_BRIDGE : ISTATUS_PM

Address offset | 0x000 019C
Physical address | 0x0300 419C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 819C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | PCI Legacy Power Management State
Type | RO

Bits | Field Name | Description | Type | Reset
31:11 | reserved11 | reserved | RO | 0x00 0000
10:8 | CLKREQ_CLK_STATUS | When L1 PM Substates with CLKREQ are implemented, this field reports the L1 PM substate. | RO | 0x0
|  | Read 0x0 | [ST_NONE] None |  |
|  | Read 0x1 | [ST_L1p1] L1 PM substate L1.1 |  |
|  | Read 0x2 | [ST_L1p2_ENTRY] L1 PM substate L1.2 Entry |  |
|  | Read 0x3 | [ST_L1p2_IDLE] L1 PM substate L1.2 Idle |  |
|  | Read 0x4 | [ST_L1p2_EXIT] L1 PM substate L1.2 Exit |  |
7:2 | reserved2 | reserved | RO | 0x00
1:0 | PCI_PM_STATE | This register specifies the PCI Legacy Power Management state (00=D0, 01=D1, 10=D2 or 11=D3hot or D3cold). It is used when the PCIe is Endpoint. Note that change in the power management state is reported by an interrupt in the ISTATUS_LOCAL register (bit 6 of PM_MSI_INT Field) | RO | 0x0

### PF_PCIE_BRIDGE : ATS_PRI_REPORT

Address offset | 0x000 01A0
Physical address | 0x0300 41A0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 81A0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Address Translation Service and Page Request Interface Reporting
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved3 | Reserved | RW | 0x0000 0000
2 | PAGE_REQ_INTF_RUN | The application sets this bit when issuing page requests or waiting for page request completions, and must clear it when serviced. | RW | 0
1 | PAGE_REQ_INTF_UPGRI | The application sets this bit to report an unexpected page request group index error. It is automatically cleared by the Bridge. | RW | 0
0 | PAGE_REQ_INTF_RESP_FAIL | Page Request Interface response failure: This bit is asserted for one clock cycle to report a response failure. It is automatically cleared by the Bridge. | RW | 0

### PF_PCIE_BRIDGE : LTR_VALUES

Address offset | 0x000 01A4
Physical address | 0x0300 41A4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 81A4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Latency Tolerance Reporting values: This register is RW for Endpoints; the Core uses these values to send Latency Tolerance Reporting messages and to manage internal L1 PM sub-states. This field is RO for Rootports; it reports the Latency Tolerance Reporting values of the last received LTR Message.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | NO_SNOOP_LAT_REQ | No-Snoop latency requirement | RW | 0
30:29 | reserved29 | Reserved | RW | 0x0
28:26 | NO_SNOOP_LAT_SCALE | No-Snoop latency scale | RW | 0x0
25:16 | NO_SNOOP_LAT_VAL | No-Snoop latency value | RW | 0x000
15 | SNOOP_LAT_REQ | Snoop latency requirement | RW | 0
14:13 | reserved13 | Reserved | RW | 0x0
12:10 | SNOOP_LAT_SCALE | Snoop latency scale | RW | 0x0
9:0 | SNOOP_LAT_VAL | Snoop latency value | RW | 0x000

### PF_PCIE_BRIDGE : ISTATUS_DMA0

Address offset | 0x000 01B0
Physical address | 0x0300 41B0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 81B0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | DMA status for DMA engine0. Register is automatically cleared when DMA_CONTROL[0] is set to 1b.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved24 | Reserved | RO | 0x00
23:20 | reserved20 | Reserved | RO | 0x0
19 | DEST_ERR_UR_OR_DECERR | DEST_ERR:UR received PCIe if on PCIe domain, DECERR response received if on AXI domain | RO | 0
18 | DEST_ERR_EP_ECRC_OR_SLVERR | DEST_ERR:EP or ECRC received if on PCIe domain, SLVERR response received if on AXI domain | RO | 0
17 | DEST_ERR_CA_OR_EXOKAY | DEST_ERR:CA received if on PCIe domain, EXOKAY received if on AXI domain | RO | 0
16 | DEST_ERR_CMPL_TIMEOUT | DEST_ERR:Completion Timeout | RO | 0
15:12 | reserved15 | Reserved | RO | 0x0
11 | SRC_ERR_UR_OR_DECERR | SRC_ERR:UR received PCIe if on PCIe domain, DECERR response received if on AXI domain | RO | 0
10 | SRC_ERR_EP_ECRC_OR_SLVERR | SRC_ERR:EP or ECRC received if on PCIe domain, SLVERR response received if on AXI domain | RO | 0
9 | SRC_ERR_CA_OR_EXOKAY | SRC_ERR:CA received if on PCIe domain, EXOKAY received if on AXI domain | RO | 0
8 | SCR_ERR_CMPL_TIMEOUT | SRC_ERR:Completion Timeout | RO | 0
7 | DMA_END | DMA incorrectly ended (buffer or descriptor not released). Note that if DMA ends because of an error, the Error Status field will be something other than 8?b0. This field is automatically cleared when DMA_CONTROL[0] is set to 1b. | RO | 0
6 | DMA_STOP | DMA successfully stopped by user | RO | 0
5 | reserved5 | Reserved | RO | 0
4 | DMA_CMPL | DMA Complete with more than 4GBytes of data transferred | RO | 0
3 | DMA_CMPL_ERR | DMA Complete with Error | RO | 0
2 | DMA_CMPL_EOC | DMA Complete with EOC received on last descriptor (if relevant) | RO | 0
1 | DMA_CMPL_EOP | DMA Complete with an EOP condition reported by the source of the transfer | RO | 0
0 | DMA_COMPL_LENGTH | DMA Complete with DMA_LENGTH reached | RO | 0

### PF_PCIE_BRIDGE : ISTATUS_DMA1

Address offset | 0x000 01B4
Physical address | 0x0300 41B4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 81B4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | DMA status for DMA engine1. Register is automatically cleared when DMA_CONTROL[0] is set to 1b.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved24 | Reserved | RO | 0x00
23:20 | reserved20 | Reserved | RO | 0x0
19 | DEST_ERR_UR_OR_DECERR | DEST_ERR:UR received PCIe if on PCIe domain, DECERR response received if on AXI domain | RO | 0
18 | DEST_ERR_EP_ECRC_OR_SLVERR | DEST_ERR:EP or ECRC received if on PCIe domain, SLVERR response received if on AXI domain | RO | 0
17 | DEST_ERR_CA_OR_EXOKAY | DEST_ERR:CA received if on PCIe domain, EXOKAY received if on AXI domain | RO | 0
16 | DEST_ERR_CMPL_TIMEOUT | DEST_ERR:Completion Timeout | RO | 0
15:12 | reserved15 | Reserved | RO | 0x0
11 | SRC_ERR_UR_OR_DECERR | SRC_ERR:UR received PCIe if on PCIe domain, DECERR response received if on AXI domain | RO | 0
10 | SRC_ERR_EP_ECRC_OR_SLVERR | SRC_ERR:EP or ECRC received if on PCIe domain, SLVERR response received if on AXI domain | RO | 0
9 | SRC_ERR_CA_OR_EXOKAY | SRC_ERR:CA received if on PCIe domain, EXOKAY received if on AXI domain | RO | 0
8 | SCR_ERR_CMPL_TIMEOUT | SRC_ERR:Completion Timeout | RO | 0
7 | DMA_END | DMA incorrectly ended (buffer or descriptor not released). Note that if DMA ends because of an error, the Error Status field will be something other than 8?b0. This field is automatically cleared when DMA_CONTROL[0] is set to 1b. | RO | 0
6 | DMA_STOP | DMA successfully stopped by user | RO | 0
5 | reserved5 | Reserved | RO | 0
4 | DMA_CMPL | DMA Complete with more than 4GBytes of data transferred | RO | 0
3 | DMA_CMPL_ERR | DMA Complete with Error | RO | 0
2 | DMA_CMPL_EOC | DMA Complete with EOC received on last descriptor (if relevant) | RO | 0
1 | DMA_CMPL_EOP | DMA Complete with an EOP condition reported by the source of the transfer | RO | 0
0 | DMA_COMPL_LENGTH | DMA Complete with DMA_LENGTH reached | RO | 0

### PF_PCIE_BRIDGE : ISTATUS_P_ADT_WIN0

Address offset | 0x000 01D8
Physical address | 0x0300 41D8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 81D8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | The status register's bits are automatically set when a corresponding event occurs. These registers are automatically cleared when the corresponding bits of P_ATR_EVT and A_ATR_EVT Field are written to 1b.
Type | RO

Bits | Field Name | Description | Type | Reset
31 | ISTATUS_ADT7_W0_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 0 Address Translation Table 7. | RO | 0
30 | ISTATUS_ADT7_W0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 7. | RO | 0
29 | ISTATUS_ADT7_W0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 7. | RO | 0
28 | ISTATUS_ADT7_W0_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 0 Address Translation Table 7. | RO | 0
27 | ISTATUS_ADT6_W0_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 0 Address Translation Table 7. | RO | 0
26 | ISTATUS_ADT6_W0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 6. | RO | 0
25 | ISTATUS_ADT6_W0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 6. | RO | 0
24 | ISTATUS_ADT6_W0_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 0 Address Translation Table 6. | RO | 0
23 | ISTATUS_ADT5_W0_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 0 Address Translation Table 5. | RO | 0
22 | ISTATUS_ADT5_W0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 5. | RO | 0
21 | ISTATUS_ADT5_W0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 5. | RO | 0
20 | ISTATUS_ADT5_W0_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 0 Address Translation Table 5. | RO | 0
19 | ISTATUS_ADT4_W0_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 0 Address Translation Table 4. | RO | 0
18 | ISTATUS_ADT4_W0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 4. | RO | 0
17 | ISTATUS_ADT4_W0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 4. | RO | 0
16 | ISTATUS_ADT4_W0_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 0 Address Translation Table 4. | RO | 0
15 | ISTATUS_ADT3_W0_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 0 Address Translation Table 3. | RO | 0
14 | ISTATUS_ADT3_W0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 3. | RO | 0
13 | ISTATUS_ADT3_W0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 3. | RO | 0
12 | ISTATUS_ADT3_W0_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 0 Address Translation Table 3. | RO | 0
11 | ISTATUS_ADT2_W0_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 0 Address Translation Table 2. | RO | 0
10 | ISTATUS_ADT2_W0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 2. | RO | 0
9 | ISTATUS_ADT2_W0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 2. | RO | 0
8 | ISTATUS_ADT2_W0_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 0 Address Translation Table 2. | RO | 0
7 | ISTATUS_ADT1_W0_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 0 Address Translation Table 1. | RO | 0
6 | ISTATUS_ADT1_W0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 1. | RO | 0
5 | ISTATUS_ADT1_W0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 1. | RO | 0
4 | ISTATUS_ADT1_W0_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 0 Address Translation Table 1. | RO | 0
3 | ISTATUS_ADT0_W0_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 0 Address Translation Table 0. | RO | 0
2 | ISTATUS_ADT0_W0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 0. | RO | 0
1 | ISTATUS_ADT0_W0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 0 Address Translation Table 0. | RO | 0
0 | ISTATUS_ADT0_W0_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 0 Address Translation Table 0. | RO | 0

### PF_PCIE_BRIDGE : ISTATUS_P_ADT_WIN1

Address offset | 0x000 01DC
Physical address | 0x0300 41DC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 81DC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | The status register's bits are automatically set when a corresponding event occurs. These registers are automatically cleared when the corresponding bits of P_ATR_EVT and A_ATR_EVT Field are written to 1b.
Type | RO

Bits | Field Name | Description | Type | Reset
31 | ISTATUS_ADT7_W1_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 1 Address Translation Table 7. | RO | 0
30 | ISTATUS_ADT7_W1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 7. | RO | 0
29 | ISTATUS_ADT7_W1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 7. | RO | 0
28 | ISTATUS_ADT7_W1_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 1 Address Translation Table 7. | RO | 0
27 | ISTATUS_ADT6_W1_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 1 Address Translation Table 7. | RO | 0
26 | ISTATUS_ADT6_W1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 6. | RO | 0
25 | ISTATUS_ADT6_W1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 6. | RO | 0
24 | ISTATUS_ADT6_W1_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 1 Address Translation Table 6. | RO | 0
23 | ISTATUS_ADT5_W1_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 1 Address Translation Table 5. | RO | 0
22 | ISTATUS_ADT5_W1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 5. | RO | 0
21 | ISTATUS_ADT5_W1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 5. | RO | 0
20 | ISTATUS_ADT5_W1_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 1 Address Translation Table 5. | RO | 0
19 | ISTATUS_ADT4_W1_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 1 Address Translation Table 4. | RO | 0
18 | ISTATUS_ADT4_W1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 4. | RO | 0
17 | ISTATUS_ADT4_W1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 4. | RO | 0
16 | ISTATUS_ADT4_W1_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 1 Address Translation Table 4. | RO | 0
15 | ISTATUS_ADT3_W1_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 1 Address Translation Table 3. | RO | 0
14 | ISTATUS_ADT3_W1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 3. | RO | 0
13 | ISTATUS_ADT3_W1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 3. | RO | 0
12 | ISTATUS_ADT3_W1_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 1 Address Translation Table 3. | RO | 0
11 | ISTATUS_ADT2_W1_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 1 Address Translation Table 2. | RO | 0
10 | ISTATUS_ADT2_W1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 2. | RO | 0
9 | ISTATUS_ADT2_W1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 2. | RO | 0
8 | ISTATUS_ADT2_W1_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 1 Address Translation Table 2. | RO | 0
7 | ISTATUS_ADT1_W1_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 1 Address Translation Table 1. | RO | 0
6 | ISTATUS_ADT1_W1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 1. | RO | 0
5 | ISTATUS_ADT1_W1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 1. | RO | 0
4 | ISTATUS_ADT1_W1_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 1 Address Translation Table 1. | RO | 0
3 | ISTATUS_ADT0_W1_DOORBELL | Status set when a PCIe request has successfully targeted PCIe Window 1 Address Translation Table 0. | RO | 0
2 | ISTATUS_ADT0_W1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 0. | RO | 0
1 | ISTATUS_ADT0_W1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a PCIe read request corresponding to PCIe Window 1 Address Translation Table 0. | RO | 0
0 | ISTATUS_ADT0_W1_POST_ERR | Status set when an event occurs to signal an error occurred on a PCIe write request corresponding to PCIe Window 1 Address Translation Table 0. | RO | 0

### PF_PCIE_BRIDGE : ISTATUS_A_ADT_SLV0

Address offset | 0x000 01E0
Physical address | 0x0300 41E0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 81E0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | The status register's bits are automatically set when a corresponding event occurs. These registers are automatically cleared when the corresponding bits of P_ATR_EVT and A_ATR_EVT Field are written to 1b.
Type | RO

Bits | Field Name | Description | Type | Reset
31 | ISTATUS_ADT7_S0_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 0 Address Translation Table 7. | RO | 0
30 | ISTATUS_ADT7_S0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 7. | RO | 0
29 | ISTATUS_ADT7_S0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 7. | RO | 0
28 | ISTATUS_ADT7_S0_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 0 Address Translation Table 7. | RO | 0
27 | ISTATUS_ADT6_S0_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 0 Address Translation Table 7. | RO | 0
26 | ISTATUS_ADT6_S0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 6. | RO | 0
25 | ISTATUS_ADT6_S0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 6. | RO | 0
24 | ISTATUS_ADT6_S0_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 0 Address Translation Table 6. | RO | 0
23 | ISTATUS_ADT5_S0_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 0 Address Translation Table 5. | RO | 0
22 | ISTATUS_ADT5_S0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 5. | RO | 0
21 | ISTATUS_ADT5_S0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 5. | RO | 0
20 | ISTATUS_ADT5_S0_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 0 Address Translation Table 5. | RO | 0
19 | ISTATUS_ADT4_S0_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 0 Address Translation Table 4. | RO | 0
18 | ISTATUS_ADT4_S0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 4. | RO | 0
17 | ISTATUS_ADT4_S0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 4. | RO | 0
16 | ISTATUS_ADT4_S0_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 0 Address Translation Table 4. | RO | 0
15 | ISTATUS_ADT3_S0_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 0 Address Translation Table 3. | RO | 0
14 | ISTATUS_ADT3_S0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 3. | RO | 0
13 | ISTATUS_ADT3_S0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 3. | RO | 0
12 | ISTATUS_ADT3_S0_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 0 Address Translation Table 3. | RO | 0
11 | ISTATUS_ADT2_S0_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 0 Address Translation Table 2. | RO | 0
10 | ISTATUS_ADT2_S0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 2. | RO | 0
9 | ISTATUS_ADT2_S0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 2. | RO | 0
8 | ISTATUS_ADT2_S0_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 0 Address Translation Table 2. | RO | 0
7 | ISTATUS_ADT1_S0_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 0 Address Translation Table 1. | RO | 0
6 | ISTATUS_ADT1_S0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 1. | RO | 0
5 | ISTATUS_ADT1_S0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 1. | RO | 0
4 | ISTATUS_ADT1_S0_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 0 Address Translation Table 1. | RO | 0
3 | ISTATUS_ADT0_S0_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 0 Address Translation Table 0. | RO | 0
2 | ISTATUS_ADT0_S0_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 0. | RO | 0
1 | ISTATUS_ADT0_S0_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 0 Address Translation Table 0. | RO | 0
0 | ISTATUS_ADT0_S0_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 0 Address Translation Table 0. | RO | 0

### PF_PCIE_BRIDGE : ISTATUS_A_ADT_SLV1

Address offset | 0x000 01E4
Physical address | 0x0300 41E4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 81E4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | The status register's bits are automatically set when a corresponding event occurs. These registers are automatically cleared when the corresponding bits of P_ATR_EVT and A_ATR_EVT Field are written to 1b.
Type | RO

Bits | Field Name | Description | Type | Reset
31 | ISTATUS_ADT7_S1_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 1 Address Translation Table 7. | RO | 0
30 | ISTATUS_ADT7_S1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 7. | RO | 0
29 | ISTATUS_ADT7_S1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 7. | RO | 0
28 | ISTATUS_ADT7_S1_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 1 Address Translation Table 7. | RO | 0
27 | ISTATUS_ADT6_S1_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 1 Address Translation Table 7. | RO | 0
26 | ISTATUS_ADT6_S1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 6. | RO | 0
25 | ISTATUS_ADT6_S1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 6. | RO | 0
24 | ISTATUS_ADT6_S1_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 1 Address Translation Table 6. | RO | 0
23 | ISTATUS_ADT5_S1_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 1 Address Translation Table 5. | RO | 0
22 | ISTATUS_ADT5_S1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 5. | RO | 0
21 | ISTATUS_ADT5_S1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 5. | RO | 0
20 | ISTATUS_ADT5_S1_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 1 Address Translation Table 5. | RO | 0
19 | ISTATUS_ADT4_S1_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 1 Address Translation Table 4. | RO | 0
18 | ISTATUS_ADT4_S1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 4. | RO | 0
17 | ISTATUS_ADT4_S1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 4. | RO | 0
16 | ISTATUS_ADT4_S1_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 1 Address Translation Table 4. | RO | 0
15 | ISTATUS_ADT3_S1_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 1 Address Translation Table 3. | RO | 0
14 | ISTATUS_ADT3_S1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 3. | RO | 0
13 | ISTATUS_ADT3_S1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 3. | RO | 0
12 | ISTATUS_ADT3_S1_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 1 Address Translation Table 3. | RO | 0
11 | ISTATUS_ADT2_S1_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 1 Address Translation Table 2. | RO | 0
10 | ISTATUS_ADT2_S1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 2. | RO | 0
9 | ISTATUS_ADT2_S1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 2. | RO | 0
8 | ISTATUS_ADT2_S1_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 1 Address Translation Table 2. | RO | 0
7 | ISTATUS_ADT1_S1_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 1 Address Translation Table 1. | RO | 0
6 | ISTATUS_ADT1_S1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 1. | RO | 0
5 | ISTATUS_ADT1_S1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 1. | RO | 0
4 | ISTATUS_ADT1_S1_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 1 Address Translation Table 1. | RO | 0
3 | ISTATUS_ADT0_S1_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 1 Address Translation Table 0. | RO | 0
2 | ISTATUS_ADT0_S1_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 0. | RO | 0
1 | ISTATUS_ADT0_S1_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 1 Address Translation Table 0. | RO | 0
0 | ISTATUS_ADT0_S1_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 1 Address Translation Table 0. | RO | 0

### PF_PCIE_BRIDGE : ISTATUS_A_ADT_SLV2

Address offset | 0x000 01E8
Physical address | 0x0300 41E8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 81E8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | The status register's bits are automatically set when a corresponding event occurs. These registers are automatically cleared when the corresponding bits of P_ATR_EVT and A_ATR_EVT Field are written to 1b.
Type | RO

Bits | Field Name | Description | Type | Reset
31 | ISTATUS_ADT7_S2_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 2 Address Translation Table 7. | RO | 0
30 | ISTATUS_ADT7_S2_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 7. | RO | 0
29 | ISTATUS_ADT7_S2_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 7. | RO | 0
28 | ISTATUS_ADT7_S2_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 2 Address Translation Table 7. | RO | 0
27 | ISTATUS_ADT6_S2_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 2 Address Translation Table 7. | RO | 0
26 | ISTATUS_ADT6_S2_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 6. | RO | 0
25 | ISTATUS_ADT6_S2_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 6. | RO | 0
24 | ISTATUS_ADT6_S2_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 2 Address Translation Table 6. | RO | 0
23 | ISTATUS_ADT5_S2_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 2 Address Translation Table 5. | RO | 0
22 | ISTATUS_ADT5_S2_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 5. | RO | 0
21 | ISTATUS_ADT5_S2_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 5. | RO | 0
20 | ISTATUS_ADT5_S2_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 2 Address Translation Table 5. | RO | 0
19 | ISTATUS_ADT4_S2_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 2 Address Translation Table 4. | RO | 0
18 | ISTATUS_ADT4_S2_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 4. | RO | 0
17 | ISTATUS_ADT4_S2_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 4. | RO | 0
16 | ISTATUS_ADT4_S2_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 2 Address Translation Table 4. | RO | 0
15 | ISTATUS_ADT3_S2_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 2 Address Translation Table 3. | RO | 0
14 | ISTATUS_ADT3_S2_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 3. | RO | 0
13 | ISTATUS_ADT3_S2_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 3. | RO | 0
12 | ISTATUS_ADT3_S2_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 2 Address Translation Table 3. | RO | 0
11 | ISTATUS_ADT2_S2_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 2 Address Translation Table 2. | RO | 0
10 | ISTATUS_ADT2_S2_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 2. | RO | 0
9 | ISTATUS_ADT2_S2_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 2. | RO | 0
8 | ISTATUS_ADT2_S2_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 2 Address Translation Table 2. | RO | 0
7 | ISTATUS_ADT1_S2_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 2 Address Translation Table 1. | RO | 0
6 | ISTATUS_ADT1_S2_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 1. | RO | 0
5 | ISTATUS_ADT1_S2_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 1. | RO | 0
4 | ISTATUS_ADT1_S2_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 2 Address Translation Table 1. | RO | 0
3 | ISTATUS_ADT0_S2_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 2 Address Translation Table 0. | RO | 0
2 | ISTATUS_ADT0_S2_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 0. | RO | 0
1 | ISTATUS_ADT0_S2_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 2 Address Translation Table 0. | RO | 0
0 | ISTATUS_ADT0_S2_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 2 Address Translation Table 0. | RO | 0

### PF_PCIE_BRIDGE : ISTATUS_A_ADT_SLV3

Address offset | 0x000 01EC
Physical address | 0x0300 41EC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 81EC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | The status register's bits are automatically set when a corresponding event occurs. These registers are automatically cleared when the corresponding bits of P_ATR_EVT and A_ATR_EVT Field are written to 1b.
Type | RO

Bits | Field Name | Description | Type | Reset
31 | ISTATUS_ADT7_S3_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 3 Address Translation Table 7. | RO | 0
30 | ISTATUS_ADT7_S3_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 7. | RO | 0
29 | ISTATUS_ADT7_S3_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 7. | RO | 0
28 | ISTATUS_ADT7_S3_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 3 Address Translation Table 7. | RO | 0
27 | ISTATUS_ADT6_S3_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 3 Address Translation Table 7. | RO | 0
26 | ISTATUS_ADT6_S3_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 6. | RO | 0
25 | ISTATUS_ADT6_S3_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 6. | RO | 0
24 | ISTATUS_ADT6_S3_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 3 Address Translation Table 6. | RO | 0
23 | ISTATUS_ADT5_S3_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 3 Address Translation Table 5. | RO | 0
22 | ISTATUS_ADT5_S3_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 5. | RO | 0
21 | ISTATUS_ADT5_S3_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 5. | RO | 0
20 | ISTATUS_ADT5_S3_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 3 Address Translation Table 5. | RO | 0
19 | ISTATUS_ADT4_S3_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 3 Address Translation Table 4. | RO | 0
18 | ISTATUS_ADT4_S3_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 4. | RO | 0
17 | ISTATUS_ADT4_S3_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 4. | RO | 0
16 | ISTATUS_ADT4_S3_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 3 Address Translation Table 4. | RO | 0
15 | ISTATUS_ADT3_S3_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 3 Address Translation Table 3. | RO | 0
14 | ISTATUS_ADT3_S3_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 3. | RO | 0
13 | ISTATUS_ADT3_S3_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 3. | RO | 0
12 | ISTATUS_ADT3_S3_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 3 Address Translation Table 3. | RO | 0
11 | ISTATUS_ADT2_S3_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 3 Address Translation Table 2. | RO | 0
10 | ISTATUS_ADT2_S3_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 2. | RO | 0
9 | ISTATUS_ADT2_S3_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 2. | RO | 0
8 | ISTATUS_ADT2_S3_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 3 Address Translation Table 2. | RO | 0
7 | ISTATUS_ADT1_S3_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 3 Address Translation Table 1. | RO | 0
6 | ISTATUS_ADT1_S3_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 1. | RO | 0
5 | ISTATUS_ADT1_S3_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 1. | RO | 0
4 | ISTATUS_ADT1_S3_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 3 Address Translation Table 1. | RO | 0
3 | ISTATUS_ADT0_S3_DOORBELL | Status set when a AXI request has successfully targeted AXI4 Slave 3 Address Translation Table 0. | RO | 0
2 | ISTATUS_ADT0_S3_DISCARD_ERR | Status set when an event occurs to signal a completion timeout on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 0. | RO | 0
1 | ISTATUS_ADT0_S3_FETCH_ERR | Status set when an event occurs to signal an error occurred on a AXI read request corresponding to AXI4 Slave 3 Address Translation Table 0. | RO | 0
0 | ISTATUS_ADT0_S3_POST_ERR | Status set when an event occurs to signal an error occurred on a AXI write request corresponding to AXI4 Slave 3 Address Translation Table 0. | RO | 0

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW0

Address offset | 0x000 0200
Physical address | 0x0300 4200 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8200 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_0 | When bit j[0..31] of vector is asserted, it means that Completer 0 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 0. | RO | 0x000B 0011

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW1

Address offset | 0x000 0204
Physical address | 0x0300 4204 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8204 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_1 | When bit j[0..31] of vector is asserted, it means that Completer 1 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 1. | RO | 0x0000 0015

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW2

Address offset | 0x000 0208
Physical address | 0x0300 4208 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8208 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_2 | When bit j[0..31] of vector is asserted, it means that Completer 2 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 2. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW3

Address offset | 0x000 020C
Physical address | 0x0300 420C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 820C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_3 | When bit j[0..31] of vector is asserted, it means that Completer 3 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 3. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW4

Address offset | 0x000 0210
Physical address | 0x0300 4210 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8210 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_4 | When bit j[0..31] of vector is asserted, it means that Completer 4 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 4. | RO | 0x000E 0011

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW5

Address offset | 0x000 0214
Physical address | 0x0300 4214 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8214 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_5 | When bit j[0..31] of vector is asserted, it means that Completer 5 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 5. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW6

Address offset | 0x000 0218
Physical address | 0x0300 4218 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8218 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_6 | When bit j[0..31] of vector is asserted, it means that Completer 6 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 6. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW7

Address offset | 0x000 021C
Physical address | 0x0300 421C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 821C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_7 | When bit j[0..31] of vector is asserted, it means that Completer 7 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 7. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW8

Address offset | 0x000 0220
Physical address | 0x0300 4220 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8220 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_8 | When bit j[0..31] of vector is asserted, it means that Completer 8 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 8. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW9

Address offset | 0x000 0224
Physical address | 0x0300 4224 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8224 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_9 | When bit j[0..31] of vector is asserted, it means that Completer 9 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 9. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW10

Address offset | 0x000 0228
Physical address | 0x0300 4228 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8228 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_10 | When bit j[0..31] of vector is asserted, it means that Completer 10 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 10. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW11

Address offset | 0x000 022C
Physical address | 0x0300 422C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 822C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_11 | When bit j[0..31] of vector is asserted, it means that Completer 11 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 11. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW12

Address offset | 0x000 0230
Physical address | 0x0300 4230 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8230 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_12 | When bit j[0..31] of vector is asserted, it means that Completer 12 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 12. | RO | 0x0000 0015

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW13

Address offset | 0x000 0234
Physical address | 0x0300 4234 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8234 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_13 | When bit j[0..31] of vector is asserted, it means that Completer 13 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 13. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW14

Address offset | 0x000 0238
Physical address | 0x0300 4238 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8238 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_14 | When bit j[0..31] of vector is asserted, it means that Completer 14 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 14. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_R_DW15

Address offset | 0x000 023C
Physical address | 0x0300 423C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 823C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Read Requester and Read Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_RREQ_M[31:0] , ..,XR3AXI_KARB00_RREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_R_CMPL_15 | When bit j[0..31] of vector is asserted, it means that Completer 15 is allowed to receive a read request from Requester j, and that Requester j is allowed to receive a read completion from Completer 15. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW0

Address offset | 0x000 0240
Physical address | 0x0300 4240 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8240 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_0 | When bit j[0..31] of vector is asserted, it means that Completer 0 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 0. | RO | 0x000F 0011

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW1

Address offset | 0x000 0244
Physical address | 0x0300 4244 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8244 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_1 | When bit j[0..31] of vector is asserted, it means that Completer 1 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 1. | RO | 0x0000 0014

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW2

Address offset | 0x000 0248
Physical address | 0x0300 4248 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8248 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_2 | When bit j[0..31] of vector is asserted, it means that Completer 2 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 2. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW3

Address offset | 0x000 024C
Physical address | 0x0300 424C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 824C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_3 | When bit j[0..31] of vector is asserted, it means that Completer 3 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 3. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW4

Address offset | 0x000 0250
Physical address | 0x0300 4250 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8250 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_4 | When bit j[0..31] of vector is asserted, it means that Completer 4 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 4. | RO | 0x000B 0011

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW5

Address offset | 0x000 0254
Physical address | 0x0300 4254 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8254 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_5 | When bit j[0..31] of vector is asserted, it means that Completer 5 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 5. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW6

Address offset | 0x000 0258
Physical address | 0x0300 4258 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8258 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_6 | When bit j[0..31] of vector is asserted, it means that Completer 6 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 6. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW7

Address offset | 0x000 025C
Physical address | 0x0300 425C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 825C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_7 | When bit j[0..31] of vector is asserted, it means that Completer 7 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 7. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW8

Address offset | 0x000 0260
Physical address | 0x0300 4260 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8260 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_8 | When bit j[0..31] of vector is asserted, it means that Completer 8 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 8. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW9

Address offset | 0x000 0264
Physical address | 0x0300 4264 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8264 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_9 | When bit j[0..31] of vector is asserted, it means that Completer 9 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 9. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW10

Address offset | 0x000 0268
Physical address | 0x0300 4268 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8268 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_10 | When bit j[0..31] of vector is asserted, it means that Completer 10 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 10. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW11

Address offset | 0x000 026C
Physical address | 0x0300 426C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 826C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_11 | When bit j[0..31] of vector is asserted, it means that Completer 11 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 11. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW12

Address offset | 0x000 0270
Physical address | 0x0300 4270 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8270 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_12 | When bit j[0..31] of vector is asserted, it means that Completer 12 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 12. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW13

Address offset | 0x000 0274
Physical address | 0x0300 4274 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8274 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_13 | When bit j[0..31] of vector is asserted, it means that Completer 13 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 13. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW14

Address offset | 0x000 0278
Physical address | 0x0300 4278 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8278 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_14 | When bit j[0..31] of vector is asserted, it means that Completer 14 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 14. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ROUTING_RULES_W_DW15

Address offset | 0x000 027C
Physical address | 0x0300 427C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 827C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Routing Rules register defines the allowed connections between Write Requester and Write Completer modules. It consists of 16 vectors of 32 bits. Its value is equal to {XR3AXI_KARB15_WREQ_M[31:0] , ..,XR3AXI_KARB00_WREQ_M[31:0]}
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ROUTING_W_CMPL_15 | When bit j[0..31] of vector is asserted, it means that Completer 15 is allowed to receive a write request from Requester j, and that Requester j is allowed to receive a write completion from Completer 15. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW0

Address offset | 0x000 0280
Physical address | 0x0300 4280 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8280 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields. These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC1 | Defines the Arbitration type for write completions for Requester/Completer 1 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC1 | Defines the Arbitration type for write requests for Requester/Completer 1 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC1 | Defines the Arbitration type for read completions for Requester/Completer 1 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC1 | Defines the Arbitration type for read requests for Requester/Completer 1 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC0 | Defines the Arbitration type for write completions for Requester/Completer 0 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC0 | Defines the Arbitration type for write requests for Requester/Completer 0 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC0 | Defines the Arbitration type for read completions for Requester/Completer 0 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC0 | Defines the Arbitration type for read requests for Requester/Completer 0 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW1

Address offset | 0x000 0284
Physical address | 0x0300 4284 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8284 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC3 | Defines the Arbitration type for write completions for Requester/Completer 3 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC3 | Defines the Arbitration type for write requests for Requester/Completer 3 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC3 | Defines the Arbitration type for read completions for Requester/Completer 3 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC3 | Defines the Arbitration type for read requests for Requester/Completer 3 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC2 | Defines the Arbitration type for write completions for Requester/Completer 2 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC2 | Defines the Arbitration type for write requests for Requester/Completer 2 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC2 | Defines the Arbitration type for read completions for Requester/Completer 2 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC2 | Defines the Arbitration type for read requests for Requester/Completer 2 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW2

Address offset | 0x000 0288
Physical address | 0x0300 4288 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8288 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC5 | Defines the Arbitration type for write completions for Requester/Completer 5 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC5 | Defines the Arbitration type for write requests for Requester/Completer 5 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC5 | Defines the Arbitration type for read completions for Requester/Completer 5 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC5 | Defines the Arbitration type for read requests for Requester/Completer 5 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC4 | Defines the Arbitration type for write completions for Requester/Completer 4 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC4 | Defines the Arbitration type for write requests for Requester/Completer 4 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC4 | Defines the Arbitration type for read completions for Requester/Completer 4 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC4 | Defines the Arbitration type for read requests for Requester/Completer 4 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW3

Address offset | 0x000 028C
Physical address | 0x0300 428C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 828C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC7 | Defines the Arbitration type for write completions for Requester/Completer 7 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC7 | Defines the Arbitration type for write requests for Requester/Completer 7 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC7 | Defines the Arbitration type for read completions for Requester/Completer 7 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC7 | Defines the Arbitration type for read requests for Requester/Completer 7 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC6 | Defines the Arbitration type for write completions for Requester/Completer 6 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC6 | Defines the Arbitration type for write requests for Requester/Completer 6 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC6 | Defines the Arbitration type for read completions for Requester/Completer 6 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC6 | Defines the Arbitration type for read requests for Requester/Completer 6 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW4

Address offset | 0x000 0290
Physical address | 0x0300 4290 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8290 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC9 | Defines the Arbitration type for write completions for Requester/Completer 9 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC9 | Defines the Arbitration type for write requests for Requester/Completer 9 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC9 | Defines the Arbitration type for read completions for Requester/Completer 9 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC9 | Defines the Arbitration type for read requests for Requester/Completer 9 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC8 | Defines the Arbitration type for write completions for Requester/Completer 8 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC8 | Defines the Arbitration type for write requests for Requester/Completer 8 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC8 | Defines the Arbitration type for read completions for Requester/Completer 8 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC8 | Defines the Arbitration type for read requests for Requester/Completer 8 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW5

Address offset | 0x000 0294
Physical address | 0x0300 4294 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8294 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC11 | Defines the Arbitration type for write completions for Requester/Completer 11 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC11 | Defines the Arbitration type for write requests for Requester/Completer 11 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC11 | Defines the Arbitration type for read completions for Requester/Completer 11 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC11 | Defines the Arbitration type for read requests for Requester/Completer 11 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC10 | Defines the Arbitration type for write completions for Requester/Completer 10 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC10 | Defines the Arbitration type for write requests for Requester/Completer 10 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC10 | Defines the Arbitration type for read completions for Requester/Completer 10 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC10 | Defines the Arbitration type for read requests for Requester/Completer 10 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW6

Address offset | 0x000 0298
Physical address | 0x0300 4298 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8298 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC13 | Defines the Arbitration type for write completions for Requester/Completer 13 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC13 | Defines the Arbitration type for write requests for Requester/Completer 13 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC13 | Defines the Arbitration type for read completions for Requester/Completer 13 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC13 | Defines the Arbitration type for read requests for Requester/Completer 13 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC12 | Defines the Arbitration type for write completions for Requester/Completer 12 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC12 | Defines the Arbitration type for write requests for Requester/Completer 12 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC12 | Defines the Arbitration type for read completions for Requester/Completer 12 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC12 | Defines the Arbitration type for read requests for Requester/Completer 12 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW7

Address offset | 0x000 029C
Physical address | 0x0300 429C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 829C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC15 | Defines the Arbitration type for write completions for Requester/Completer 15 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC15 | Defines the Arbitration type for write requests for Requester/Completer 15 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC15 | Defines the Arbitration type for read completions for Requester/Completer 15 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC15 | Defines the Arbitration type for read requests for Requester/Completer 15 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC14 | Defines the Arbitration type for write completions for Requester/Completer 14 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC14 | Defines the Arbitration type for write requests for Requester/Completer 14 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC14 | Defines the Arbitration type for read completions for Requester/Completer 14 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC14 | Defines the Arbitration type for read requests for Requester/Completer 14 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW8

Address offset | 0x000 02A0
Physical address | 0x0300 42A0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82A0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC17 | Defines the Arbitration type for write completions for Requester/Completer 17 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC17 | Defines the Arbitration type for write requests for Requester/Completer 17 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC17 | Defines the Arbitration type for read completions for Requester/Completer 17 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC17 | Defines the Arbitration type for read requests for Requester/Completer 17 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC16 | Defines the Arbitration type for write completions for Requester/Completer 16 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC16 | Defines the Arbitration type for write requests for Requester/Completer 16 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC16 | Defines the Arbitration type for read completions for Requester/Completer 16 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC16 | Defines the Arbitration type for read requests for Requester/Completer 16 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW9

Address offset | 0x000 02A4
Physical address | 0x0300 42A4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82A4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC19 | Defines the Arbitration type for write completions for Requester/Completer 19 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC19 | Defines the Arbitration type for write requests for Requester/Completer 19 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC19 | Defines the Arbitration type for read completions for Requester/Completer 19 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC19 | Defines the Arbitration type for read requests for Requester/Completer 19 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC18 | Defines the Arbitration type for write completions for Requester/Completer 18 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC18 | Defines the Arbitration type for write requests for Requester/Completer 18 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC18 | Defines the Arbitration type for read completions for Requester/Completer 18 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC18 | Defines the Arbitration type for read requests for Requester/Completer 18 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW10

Address offset | 0x000 02A8
Physical address | 0x0300 42A8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82A8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC21 | Defines the Arbitration type for write completions for Requester/Completer 21 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC21 | Defines the Arbitration type for write requests for Requester/Completer 21 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC21 | Defines the Arbitration type for read completions for Requester/Completer 21 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC21 | Defines the Arbitration type for read requests for Requester/Completer 21 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC20 | Defines the Arbitration type for write completions for Requester/Completer 20 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC20 | Defines the Arbitration type for write requests for Requester/Completer 20 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC20 | Defines the Arbitration type for read completions for Requester/Completer 20 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC20 | Defines the Arbitration type for read requests for Requester/Completer 20 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW11

Address offset | 0x000 02AC
Physical address | 0x0300 42AC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82AC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC23 | Defines the Arbitration type for write completions for Requester/Completer 23 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC23 | Defines the Arbitration type for write requests for Requester/Completer 23 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC23 | Defines the Arbitration type for read completions for Requester/Completer 23 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC23 | Defines the Arbitration type for read requests for Requester/Completer 23 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC22 | Defines the Arbitration type for write completions for Requester/Completer 22 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC22 | Defines the Arbitration type for write requests for Requester/Completer 22 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC22 | Defines the Arbitration type for read completions for Requester/Completer 22 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC22 | Defines the Arbitration type for read requests for Requester/Completer 22 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW12

Address offset | 0x000 02B0
Physical address | 0x0300 42B0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82B0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC25 | Defines the Arbitration type for write completions for Requester/Completer 25 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC25 | Defines the Arbitration type for write requests for Requester/Completer 25 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC25 | Defines the Arbitration type for read completions for Requester/Completer 25 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC25 | Defines the Arbitration type for read requests for Requester/Completer 25 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC24 | Defines the Arbitration type for write completions for Requester/Completer 24 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC24 | Defines the Arbitration type for write requests for Requester/Completer 24 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC24 | Defines the Arbitration type for read completions for Requester/Completer 24 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC24 | Defines the Arbitration type for read requests for Requester/Completer 24 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW13

Address offset | 0x000 02B4
Physical address | 0x0300 42B4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82B4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC27 | Defines the Arbitration type for write completions for Requester/Completer 27 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC27 | Defines the Arbitration type for write requests for Requester/Completer 27 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC27 | Defines the Arbitration type for read completions for Requester/Completer 27 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC27 | Defines the Arbitration type for read requests for Requester/Completer 27 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC26 | Defines the Arbitration type for write completions for Requester/Completer 26 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC26 | Defines the Arbitration type for write requests for Requester/Completer 26 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC26 | Defines the Arbitration type for read completions for Requester/Completer 26 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC26 | Defines the Arbitration type for read requests for Requester/Completer 26 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW14

Address offset | 0x000 02B8
Physical address | 0x0300 42B8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82B8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC29 | Defines the Arbitration type for write completions for Requester/Completer 29 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC29 | Defines the Arbitration type for write requests for Requester/Completer 29 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC29 | Defines the Arbitration type for read completions for Requester/Completer 29 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC29 | Defines the Arbitration type for read requests for Requester/Completer 29 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC28 | Defines the Arbitration type for write completions for Requester/Completer 28 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC28 | Defines the Arbitration type for write requests for Requester/Completer 28 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC28 | Defines the Arbitration type for read completions for Requester/Completer 28 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC28 | Defines the Arbitration type for read requests for Requester/Completer 28 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : ARBITRATION_RULES_DW15

Address offset | 0x000 02BC
Physical address | 0x0300 42BC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82BC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Arbitration rules register defines the implemented arbitration type for each Requester/Completer. It consists of 32 vectors of 16 bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_ARB_TYPE_RC31 | Defines the Arbitration type for write completions for Requester/Completer 31 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
27:24 | WR_REQ_ARB_TYPE_RC31 | Defines the Arbitration type for write requests for Requester/Completer 31 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
23:20 | RD_CPL_ARB_TYPE_RC31 | Defines the Arbitration type for read completions for Requester/Completer 31 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
19:16 | RD_REQ_ARB_TYPE_RC31 | Defines the Arbitration type for read requests for Requester/Completer 31 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
15:12 | WR_CPL_ARB_TYPE_RC30 | Defines the Arbitration type for write completions for Requester/Completer 30 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
11:8 | WR_REQ_ARB_TYPE_RC30 | Defines the Arbitration type for write requests for Requester/Completer 30 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
7:4 | RD_CPL_ARB_TYPE_RC30 | Defines the Arbitration type for read completions for Requester/Completer 30 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |
3:0 | RD_REQ_ARB_TYPE_RC30 | Defines the Arbitration type for read requests for Requester/Completer 30 | RW | 0x1
|  | 0x0 | [FIXED_ARB] Fixed Arbitration |  |
|  | 0x1 | [RR_ARB] RoundRobin Arbitration |  |
|  | 0x2 | [WRR_ARB] Weighted Round Robin Arbitration |  |

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW0

Address offset | 0x000 02C0
Physical address | 0x0300 42C0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82C0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC1 | Defines the priority of the write completion for Requester/Completer 1 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC1 | Defines the priority of the write request for Requester/Completer 1 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC1 | Defines the priority of the read completion for Requester/Completer 1 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC1 | Defines the priority of the read request for Requester/Completer1 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC0 | Defines the priority of the write completion for Requester/Completer 0 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC0 | Defines the priority of the write request for Requester/Completer 0 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC0 | Defines the priority of the read completion for Requester/Completer 0 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC0 | Defines the priority of the read request for Requester/Completer0 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW1

Address offset | 0x000 02C4
Physical address | 0x0300 42C4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82C4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC3 | Defines the priority of the write completion for Requester/Completer 3 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC3 | Defines the priority of the write request for Requester/Completer 3 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC3 | Defines the priority of the read completion for Requester/Completer 3 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC3 | Defines the priority of the read request for Requester/Completer3 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC2 | Defines the priority of the write completion for Requester/Completer 2 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC2 | Defines the priority of the write request for Requester/Completer 2 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC2 | Defines the priority of the read completion for Requester/Completer 2 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC2 | Defines the priority of the read request for Requester/Completer2 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW2

Address offset | 0x000 02C8
Physical address | 0x0300 42C8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82C8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC5 | Defines the priority of the write completion for Requester/Completer 5 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC5 | Defines the priority of the write request for Requester/Completer 5 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC5 | Defines the priority of the read completion for Requester/Completer 5 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC5 | Defines the priority of the read request for Requester/Completer5 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC4 | Defines the priority of the write completion for Requester/Completer 4 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC4 | Defines the priority of the write request for Requester/Completer 4 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC4 | Defines the priority of the read completion for Requester/Completer 4 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC4 | Defines the priority of the read request for Requester/Completer4 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW3

Address offset | 0x000 02CC
Physical address | 0x0300 42CC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82CC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC7 | Defines the priority of the write completion for Requester/Completer 7 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC7 | Defines the priority of the write request for Requester/Completer 7 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC7 | Defines the priority of the read completion for Requester/Completer 7 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC7 | Defines the priority of the read request for Requester/Completer7 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC6 | Defines the priority of the write completion for Requester/Completer 6 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC6 | Defines the priority of the write request for Requester/Completer 6 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC6 | Defines the priority of the read completion for Requester/Completer 6 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC6 | Defines the priority of the read request for Requester/Completer6 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW4

Address offset | 0x000 02D0
Physical address | 0x0300 42D0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82D0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC9 | Defines the priority of the write completion for Requester/Completer 9 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC9 | Defines the priority of the write request for Requester/Completer 9 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC9 | Defines the priority of the read completion for Requester/Completer 9 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC9 | Defines the priority of the read request for Requester/Completer9 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC8 | Defines the priority of the write completion for Requester/Completer 8 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC8 | Defines the priority of the write request for Requester/Completer 8 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC8 | Defines the priority of the read completion for Requester/Completer 8 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC8 | Defines the priority of the read request for Requester/Completer8 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW5

Address offset | 0x000 02D4
Physical address | 0x0300 42D4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82D4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC11 | Defines the priority of the write completion for Requester/Completer 11 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC11 | Defines the priority of the write request for Requester/Completer 11 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC11 | Defines the priority of the read completion for Requester/Completer 11 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC11 | Defines the priority of the read request for Requester/Completer11 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC10 | Defines the priority of the write completion for Requester/Completer 10 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC10 | Defines the priority of the write request for Requester/Completer 10 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC10 | Defines the priority of the read completion for Requester/Completer 10 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC10 | Defines the priority of the read request for Requester/Completer10 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW6

Address offset | 0x000 02D8
Physical address | 0x0300 42D8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82D8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC13 | Defines the priority of the write completion for Requester/Completer 13 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC13 | Defines the priority of the write request for Requester/Completer 13 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC13 | Defines the priority of the read completion for Requester/Completer 13 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC13 | Defines the priority of the read request for Requester/Completer13 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC12 | Defines the priority of the write completion for Requester/Completer 12 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC12 | Defines the priority of the write request for Requester/Completer 12 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC12 | Defines the priority of the read completion for Requester/Completer 12 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC12 | Defines the priority of the read request for Requester/Completer12 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW7

Address offset | 0x000 02DC
Physical address | 0x0300 42DC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82DC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC15 | Defines the priority of the write completion for Requester/Completer 15 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC15 | Defines the priority of the write request for Requester/Completer 15 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC15 | Defines the priority of the read completion for Requester/Completer 15 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC15 | Defines the priority of the read request for Requester/Completer15 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC14 | Defines the priority of the write completion for Requester/Completer 14 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC14 | Defines the priority of the write request for Requester/Completer 14 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC14 | Defines the priority of the read completion for Requester/Completer 14 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC14 | Defines the priority of the read request for Requester/Completer14 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW8

Address offset | 0x000 02E0
Physical address | 0x0300 42E0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82E0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC17 | Defines the priority of the write completion for Requester/Completer 17 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC17 | Defines the priority of the write request for Requester/Completer 17 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC17 | Defines the priority of the read completion for Requester/Completer 17 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC17 | Defines the priority of the read request for Requester/Completer17 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC16 | Defines the priority of the write completion for Requester/Completer 16 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC16 | Defines the priority of the write request for Requester/Completer 16 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC16 | Defines the priority of the read completion for Requester/Completer 16 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC16 | Defines the priority of the read request for Requester/Completer16 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW9

Address offset | 0x000 02E4
Physical address | 0x0300 42E4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82E4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC19 | Defines the priority of the write completion for Requester/Completer 19 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC19 | Defines the priority of the write request for Requester/Completer 19 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC19 | Defines the priority of the read completion for Requester/Completer 19 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC19 | Defines the priority of the read request for Requester/Completer19 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC18 | Defines the priority of the write completion for Requester/Completer 18 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC18 | Defines the priority of the write request for Requester/Completer 18 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC18 | Defines the priority of the read completion for Requester/Completer 18 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC18 | Defines the priority of the read request for Requester/Completer18 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW10

Address offset | 0x000 02E8
Physical address | 0x0300 42E8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82E8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC21 | Defines the priority of the write completion for Requester/Completer 21 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC21 | Defines the priority of the write request for Requester/Completer 21 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC21 | Defines the priority of the read completion for Requester/Completer 21 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC21 | Defines the priority of the read request for Requester/Completer21 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC20 | Defines the priority of the write completion for Requester/Completer 20 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC20 | Defines the priority of the write request for Requester/Completer 20 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC20 | Defines the priority of the read completion for Requester/Completer 20 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC20 | Defines the priority of the read request for Requester/Completer20 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW11

Address offset | 0x000 02EC
Physical address | 0x0300 42EC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82EC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC23 | Defines the priority of the write completion for Requester/Completer 23 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC23 | Defines the priority of the write request for Requester/Completer 23 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC23 | Defines the priority of the read completion for Requester/Completer 23 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC23 | Defines the priority of the read request for Requester/Completer23 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC22 | Defines the priority of the write completion for Requester/Completer 22 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC22 | Defines the priority of the write request for Requester/Completer 22 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC22 | Defines the priority of the read completion for Requester/Completer 22 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC22 | Defines the priority of the read request for Requester/Completer22 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW12

Address offset | 0x000 02F0
Physical address | 0x0300 42F0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82F0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC25 | Defines the priority of the write completion for Requester/Completer 25 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC25 | Defines the priority of the write request for Requester/Completer 25 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC25 | Defines the priority of the read completion for Requester/Completer 25 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC25 | Defines the priority of the read request for Requester/Completer25 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC24 | Defines the priority of the write completion for Requester/Completer 24 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC24 | Defines the priority of the write request for Requester/Completer 24 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC24 | Defines the priority of the read completion for Requester/Completer 24 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC24 | Defines the priority of the read request for Requester/Completer24 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW13

Address offset | 0x000 02F4
Physical address | 0x0300 42F4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82F4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC27 | Defines the priority of the write completion for Requester/Completer 27 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC27 | Defines the priority of the write request for Requester/Completer 27 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC27 | Defines the priority of the read completion for Requester/Completer 27 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC27 | Defines the priority of the read request for Requester/Completer 27 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC26 | Defines the priority of the write completion for Requester/Completer 26 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC26 | Defines the priority of the write request for Requester/Completer 26 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC26 | Defines the priority of the read completion for Requester/Completer 26 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC26 | Defines the priority of the read request for Requester/Completer26 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW14

Address offset | 0x000 02F8
Physical address | 0x0300 42F8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82F8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC29 | Defines the priority of the write completion for Requester/Completer 29 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC29 | Defines the priority of the write request for Requester/Completer 29 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC29 | Defines the priority of the read completion for Requester/Completer 29 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC29 | Defines the priority of the read request for Requester/Completer 29 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC28 | Defines the priority of the write completion for Requester/Completer 28 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC28 | Defines the priority of the write request for Requester/Completer 28 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC28 | Defines the priority of the read completion for Requester/Completer 28 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC28 | Defines the priority of the read request for Requester/Completer 28 | RW | 0x0

### PF_PCIE_BRIDGE : PRIORITY_RULES_DW15

Address offset | 0x000 02FC
Physical address | 0x0300 42FC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 82FC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | When Weighted Round Robin arbitration is implemented, the Priority Rules define which Requester/Completer should be given the highest priority. This register consists of 32 vectors of 16-bits each, with each vector composed of 4 sub-fields These fields are set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | WR_CPL_PRIORITY_RC31 | Defines the priority of the write completion for Requester/Completer 31 | RW | 0x0
27:24 | WR_REQ_PRIORITY_RC31 | Defines the priority of the write request for Requester/Completer 31 | RW | 0x0
23:20 | RD_CPL_PRIRORITY_RC31 | Defines the priority of the read completion for Requester/Completer 31 | RW | 0x0
19:16 | RD_REQ_PRIORITY_RC31 | Defines the priority of the read request for Requester/Completer 31 | RW | 0x0
15:12 | WR_CPL_PRIORITY_RC30 | Defines the priority of the write completion for Requester/Completer 30 | RW | 0x0
11:8 | WR_REQ_PRIORITY_RC30 | Defines the priority of the write request for Requester/Completer 30 | RW | 0x0
7:4 | RD_CPL_PRIRORITY_RC30 | Defines the priority of the read completion for Requester/Completer 30 | RW | 0x0
3:0 | RD_REQ_PRIORITY_RC30 | Defines the priority of the read request for Requester/Completer 30 | RW | 0x0

### PF_PCIE_BRIDGE : P2A_TC_QOS_CONV

Address offset | 0x000 03C0
Physical address | 0x0300 43C0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 83C0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Automatic conversion between PCIe Traffic Class and AXI Quality of Service: When automatic conversion is enabled, the Traffic Class or AxQoS values issued by the Bridge are computed based on the Traffic Class or AxQoS values received by the Address Translation modules. When automatic conversion is disabled, the Traffic Class or AxQoS values issued by the Bridge depends on the Transfer Parameters programmed in Address Translation Tables.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | AxQoS_TC_7 | AxQoS[3:0] value corresponding to TC[2:0] = 7 (recommended value is 1) | RW | 0x0
27:24 | AxQoS_TC_6 | AxQoS[3:0] value corresponding to TC[2:0] = 6 (recommended value is 1) | RW | 0x0
23:20 | AxQoS_TC_5 | AxQoS[3:0] value corresponding to TC[2:0] = 5 (recommended value is 1) | RW | 0x0
19:16 | AxQoS_TC_4 | AxQoS[3:0] value corresponding to TC[2:0] = 4(recommended value is 1) | RW | 0x0
15:12 | AxQoS_TC_3 | AxQoS[3:0] value corresponding to TC[2:0] = 3 (recommended value is 1) | RW | 0x0
11:8 | AxQoS_TC_2 | AxQoS[3:0] value corresponding to TC[2:0] = 2 (recommended value is 1) | RW | 0x0
7:4 | AxQoS_TC_1 | AxQoS[3:0] value corresponding to TC[2:0] = 1 (recommended value is 1). Note: The AxQoS[3:0] value corresponding to TC[2:0] = 0 is always 0 | RW | 0x0
3:1 | reserved1 | reserved | RW | 0x0
0 | AUTO_CONV | When this bit is asserted, automatic conversion between PCIe Traffic Class and AXI Quality of Service is enabled. Otherwise it is disabled. | RW | 0

### PF_PCIE_BRIDGE : P2A_ATTR_CACHE_CONV

Address offset | 0x000 03C4
Physical address | 0x0300 43C4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 83C4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Automatic conversion between PCIe No Snoop Attribute and AXI Memory types: When automatic conversion is enabled, the No Snoop Attribute or AxCACHE values issued by the Bridge are computed based on the No Snoop Attribute or AxCACHE values received by the Address Translation modules. Note: 1. The Bridge issues PCIe memory accesses with No Snoop Attribute set to 1 when the following requirements are set: ? AxCACHE[1] of an AXI received transaction is set to 0 (transaction is non-cacheable). ? Bit [0] and Bit [5] are asserted (automatic conversion is enabled between Memory cache and No Snoop). ? Enable No Snoop Bit is asserted in the Device ControlRegister of PCIe controller configuration space.2. All PCIe IO requests will be converted into AXI transaction with AxCACHE values equal to 4'b0000. 3. In Rootport mode, the Bridge can translate PCIe MSI requests into AXI transactions. However, these requests should be forwarded to an interrupt controller, and thus should not be cacheable. This means that you can define a PCIe Non-Cacheable Space in which all incoming transactions are translated into non-cacheable AXI transactions. ? When automatic conversion is disabled, the No Snoop Attribute or AxCACHE values issued by the Bridge depends on the Transfer Parameters programmed in Address Translation Tables.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | NON_CACHE_SPACE_BUF | When asserted, all PCIe accesses whose address falls between Non-Cacheable Space Base Address and Non-Cacheable Space Base Address + 2^Non-Cacheable Space Size are set to AxCACHE = 4'b0001. Otherwise it is set to 4'b0000. | RW | 0
30:24 | NON_CACHE_SPACE_SIZE | When set to 0, this address space is disabled. Otherwise its size is equal to 2^Non-Cacheable Space Size in Bytes. | RW | 0x00
23:8 | reserved8 | Reserved | RW | 0x0000
7 | MEM_OTHER_ALLOC | When asserted, and PCIe No Snoop = 0 and Bit [5:4] = 2'b11, all PCIe memory accesses are marked as other allocate (AxCACHE[3] is set to 1) (recommended value = 0). | RW | 0
6 | MEM_ALLOC | When asserted, and PCIe No Snoop = 0 and Bit [5:4] = 2'b11, all PCIe memory accesses are marked as allocate (AxCACHE[2] is set to 1) (recommended value = 0). | RW | 0
5 | MEM_CACHEABLE | When asserted, and PCIe No Snoop = 0, all PCIe memory accesses are marked as cacheable (AxCACHE[1] is set to 1) (recommended value = 1). | RW | 0
4 | MEM_BUFFERABLE | When asserted, all PCIe memory accesses are marked as bufferable (AxCACHE[0] is set to 1) (recommended value = 1). | RW | 0
3:1 | reserved1 | Reserved | RW | 0x0
0 | AUTO_CONV_EN | When this bit is asserted, automatic conversion between PCIe No Snoop Attribute and AXI Memory types is enabled. | RW | 0

### PF_PCIE_BRIDGE : P2A_NC_BASE_ADDR_DW0

Address offset | 0x000 03C8
Physical address | 0x0300 43C8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 83C8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Non-Cacheable Space Base Address (bits [31:0]): this 64-bit address should be aligned on Non-Cacheable Space Size
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | BASE_ADDR_LDW | P2A_NC_BASE_ADDR[31:0][integer (Non-Cacheable Space Size -1):0] should be reserved and is ignored. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : P2A_NC_BASE_ADDR_DW1

Address offset | 0x000 03CC
Physical address | 0x0300 43CC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 83CC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Non-Cacheable Space Base Address(bits[63:32]): this 64-bit address should be aligned on Non-Cacheable Space Size
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | BASE_ADDR_UDW | P2A_NC_BASE_ADDR[63:32][integer (Non-Cacheable Space Size -1):0] should be reserved and is ignored. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : DMA0_SRC_PARAM

Address offset | 0x000 0400
Physical address | 0x0300 4400 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8400 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Source Parameters:DMA0_SRCPARAM is used to configure the source of the DMA Transfer(DMA engine 0), the transfer priority inside the Bridge IP Core, and the transfer parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved28 | RW | 0x0
27:16 | TRSF_PARAM | Provides the Transfer Parameters. Its content depends on the value of DEST_ID. | RW | 0x000
15:12 | reserved12 | Reserved12 | RW | 0x0
11:8 | TRSF_PRIOR | Defines the Transfer Priority inside the XpressRICH3-AXI. It is only relevant when Weighted Round Robin arbitration is implemented. The higher the priority value attributed, the lower the actual priority given. | RW | 0x0
7:4 | reserved4 | Reserved4 | RW | 0x0
3:0 | SRC_ID | Defines the Source interface ID of the DMA Transfer. When these register fields are not hardwired by Core Constants, they are read/write and their default value after reset is 4?h0 | RW | 0x0
|  | 0x0 | [SRC_ID_PCIE] PCIe Interface |  |
|  | 0x4 | [SRC_ID_AXIM0] AXI4-Master Interface Number 0 |  |
|  | 0x5 | [SRC_ID_AXIM1] AXI4-Master Interface Number 1 |  |
|  | 0x6 | [SRC_ID_AXIM2] AXI4-Master Interface Number 2 |  |
|  | 0x7 | [SRC_ID_AXIM3] AXI4-Master Interface Number 3 |  |
|  | 0x8 | [SRC_ID_AXIS0] AXI4-Stream Interface Number 0 |  |
|  | 0x9 | [SRC_ID_AXIS1] AXI4-Stream Interface Number 1 |  |
|  | 0xA | [SRC_ID_AXIS2] AXI4-Stream Interface Number 2 |  |
|  | 0xB | [SRC_ID_AXIS3] AXI4-Stream Interface Number 3 |  |

### PF_PCIE_BRIDGE : DMA0_DESTPARAM

Address offset | 0x000 0404
Physical address | 0x0300 4404 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8404 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | DMA0_DESTPARAM is used to configure the destination of the DMA Transfer(DMA engine 0), the transfer priority inside the Bridge IP Core, and the transfer parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved28 | RW | 0x0
27:16 | TRSF_PARAM | Provides the Transfer Parameters. Its content depends on the value of DEST_ID. | RW | 0x000
15:12 | reserved12 | Reserved12 | RW | 0x0
11:8 | TRSF_PRIOR | Defines the Transfer Priority inside the XpressRICH3-AXI. It is only relevant when Weighted Round Robin arbitration is implemented. The higher the priority value attributed, the lower the actual priority given. | RW | 0x0
7:4 | reserved4 | Reserved4 | RW | 0x0
3:0 | DEST_ID | Defines the Source interface ID of the DMA Transfer. When these register fields are not hardwired by Core Constants, they are read/write and their default value after reset is 4?h0 | RW | 0x0
|  | 0x0 | [DEST_ID_PCIE] PCIe Interface |  |
|  | 0x4 | [DEST_ID_AXIM0] AXI4-Master Interface Number 0 |  |
|  | 0x5 | [DEST_ID_AXIM1] AXI4-Master Interface Number 1 |  |
|  | 0x6 | [DEST_ID_AXIM2] AXI4-Master Interface Number 2 |  |
|  | 0x7 | [DEST_ID_AXIM3] AXI4-Master Interface Number 3 |  |
|  | 0x8 | [DEST_ID_AXIS0] AXI4-Stream Interface Number 0 |  |
|  | 0x9 | [DEST_ID_AXIS1] AXI4-Stream Interface Number 1 |  |
|  | 0xA | [DEST_ID_AXIS2] AXI4-Stream Interface Number 2 |  |
|  | 0xB | [DEST_ID_AXIS3] AXI4-Stream Interface Number 3 |  |

### PF_PCIE_BRIDGE : DMA0_SRCADDR_LDW

Address offset | 0x000 0408
Physical address | 0x0300 4408 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8408 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | This register provide the starting source address of the DMA Transfer(DMA engine 0)(bits[31:0]).
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRCADDR_LDW | LSB 32 bits of the starting source address of DMA transfer. Note:When SG mode is enabled for the source (see DMA_CONTROL and DMA_LENGTH registers), DMA_SRCADDR provides the address of the first Source descriptor. Note: the least significant bits must be 0. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : DMA0_SRCADDR_UDW

Address offset | 0x000 040C
Physical address | 0x0300 440C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 840C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | This register provide the starting source address of the DMA Transfer(DMA engine0)(bits[31:0]).
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRCADDR_UDW | MSB 32 bits of the starting source address of DMA transfer.If the actual source and destination address are less than 64-bits, MSB bits are ignored. Note:When SG mode is enabled for the source (see DMA_CONTROL and DMA_LENGTH registers), DMA_SRCADDR provides the address of the first Source descriptor. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : DMA0_DESTADDR_LDW

Address offset | 0x000 0410
Physical address | 0x0300 4410 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8410 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | This register provide the starting destination address of the DMA Transfer(DMA engine 0).Note that when SG Type Field is equal to 2?b11, DMA_DESTADDR is irrelevant as it is identical to DMA_SRCADDR.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | DESTADDR_LDW | LSB 32 bits of the starting destination address of DMA transfer. Note:When SG mode is enabled for the destination, DMA_DESTADDR provides the address of the first Destination descriptor. Note: the least significant bits must be 0. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : DMA0_DESTADDR_UDW

Address offset | 0x000 0414
Physical address | 0x0300 4414 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8414 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | This register provide the starting destination address of the DMA Transfer(DMA engine 0).Note that when SG Type Field is equal to 2?b11, DMA_DESTADDR is irrelevant as it is identical to DMA_SRCADDR.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | DESTADDR_UDW | MSB 32 bits of the starting destination address of DMA transfer.If the actual destination address is less than 64-bits, MSB bits are ignored. Note:When SG mode is enabled for the destination, DMA_DESTADDR provides the address of the first Destination descriptor. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : DMA0_LENGTH

Address offset | 0x000 0418
Physical address | 0x0300 4418 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8418 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | DMA_LENGTH Register provides the amount of data in bytes (up to 4GB) that should be transferred from the Source to the Destination (DMA engine 0)
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TRANSFER_LENGTH | Number of Bytesin DMA transfer. Note: If Bit 1 of the SE_COND Field is cleared, this value is only indicative and will be used to compute Bit 0 of the STATUS Field of the DMA_STATUS register. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : DMA0_CONTROL

Address offset | 0x000 041C
Physical address | 0x0300 441C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 841C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | DMA control (DMA engine 0) This configuration is set by Libero.
Type | RW

Bits | Field Name | Description | Type | Reset
31:29 | SG2_ID | If SG_TYPE is set to 2?b00, SG_ID is connected to the Source and SG2_ID is connected to the Destination. Otherwise, SG_ID is connected to the Source and/or Destination, and SG2_ID is irrelevant.Constants, they are read/write and their default value after reset is 'b0. | RW | 0x0
|  | 0x0 | [SG2_ID_PCIE] PCIe Interface |  |
|  | 0x3 | [SG2_ID_AXI_MD] AXI4-Master Descriptor Interface |  |
|  | 0x4 | [SG2_ID_AXI_M0] AXI4-Master Interface Number 0 |  |
|  | 0x5 | [SG2_ID_AXI_M1] AXI4-Master Interface Number 1 |  |
|  | 0x6 | [SG2_ID_AXI_M2] AXI4-Master Interface Number 2 |  |
|  | 0x7 | [SG2_ID_AXI_M3] AXI4-Master Interface Number 3 |  |
28:26 | SG_ID | Defines on which interface the descriptors should be read | RW | 0x0
|  | 0x0 | [SG_ID_PCIE] PCIe Interface |  |
|  | 0x3 | [SG_ID_AXI_MD] AXI4-Master Descriptor Interface |  |
|  | 0x4 | [SG_ID_AXI_M0] AXI4-Master Interface Number 0 |  |
|  | 0x5 | [SG_ID_AXI_M1] AXI4-Master Interface Number 1 |  |
|  | 0x6 | [SG_ID_AXI_M2] AXI4-Master Interface Number 2 |  |
|  | 0x7 | [SG_ID_AXI_M3] AXI4-Master Interface Number 3 |  |
25:24 | SG_TYPE | Defines the Scatter-Gather type for the DMA (only relevant if bit 3 of CTRL Field is set). 2?b00: independent SG for both Source and Destination. 2?b01: Source address is set according to Descriptor, Destination address is incremented. 2?b10: Destination address is set according to Descriptor, Source address is incremented. 2?b11: Source and Destination addresses are set according to Descriptor. When this register field is not hardwired by Core Constants, it is read/write and its default value after reset is 2?b0. | RW | 0x3
23 | DESC_UPDT | Set to 1 by the application to indicate to the DMA Engine that a Descriptor has been updated. It is only relevant when SG mode is enabled and the DESC_NEXT_RDY field was set to 0 (see DESC_NEXT_RDY). This bit is automatically cleared by the DMA Engine. | RW | 0
22:14 | reserved14 | Reserved | RW | 0x000
13 | IRD_ID_PCIE | Interrupt is issued to the Host Processor (on PCIe domain). Note: Both these bits[bit 13 and bit 12] cannot be set to ?1? at the same time; to generate an interruption on both sides, you must enable interrupts on the AXI side, and use LOCAL_INTERRUPT_IN to generate interrupts on the PCIe side. If a DMA transfer event occurs, it is reported to ISTATUS_HOST and/or ISTATUS_LOCAL registers (see the ISTATUS register), depending on the IRQ_ID content. | RW | 0
12 | IRQ_ID_AXI | Interrupt is issued to the Local Processor (on AXI domain). | RW | 0
11 | reserved11 | Reserved | RW | 0
10 | IRQ_EOP | An IRQ is issued if the source of the transfer reports an EOP condition. | RW | 0
9 | IRQ_ERR | An IRQ is issued if an error occurs. | RW | 0
8 | IRQ_DMA_END | An IRQ is issued on a DMA end. | RW | 0
7 | SE_COND_ERR | Abort on error condition (otherwise erroneous packet or descriptor is considered as processed, but the error is logged in source and/or destination error fields).[7:4]SE_COND Defines the Start and End conditions of the DMA. | RW | 0
6 | SE_COND_AXI | If the DMA destination is an AXI-Stream Interface, generate an EOP at the end of the DMA. If the source of the DMA is an AXI-Stream Interface, stop the DMA if the source of the transfer reports an EOP condition. | RW | 0
5 | SE_COND_LEN | Stop if DMA_LENGTH is reached. | RW | 0
4 | SE_COND_START | Start on SOP reception (only relevant when the source is an AXI4 Stream Interface that is on data following a TLAST assertion). | RW | 0
3 | CTRL_SG_MODE | Enables SG mode. When this register field is not hardwired by Core Constants, it is read/write and its default value after reset is 0b. | RW | 0
2 | reserved2 | Reserved | RW | 0
1 | CTRL_PAUSE_RESUME | When set to 1b DMA transfer is paused (to temporarily give more bandwidth to a transfer with higher priority). | RW | 0
0 | CTRL_START_ABORT | When set to 1b, it launches the DMA transfer; appropriate registers should have previously been set. This bit is automatically cleared by the DMA Engine at the end of the DMA transfer. | RW | 0

### PF_PCIE_BRIDGE : DMA0_STATUS

Address offset | 0x000 0420
Physical address | 0x0300 4420 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8420 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | DMA status (DMA engine 0).
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved24 | Reserved | RO | 0x00
23:20 | reserved20 | Reserved | RO | 0x0
19 | DEST_ERR_UR_OR_DECERR | DEST_ERR:UR received PCIe if on PCIe domain, DECERR response received if on AXI domain | RO | 0
18 | DEST_ERR_EP_ECRC_OR_SLVERR | DEST_ERR:EP or ECRC received if on PCIe domain, SLVERR response received if on AXI domain | RO | 0
17 | DEST_ERR_CA_OR_EXOKAY | DEST_ERR:CA received if on PCIe domain, EXOKAY received if on AXI domain | RO | 0
16 | DEST_ERR_CMPL_TIMEOUT | DEST_ERR:Completion Timeout | RO | 0
15:12 | reserved12 | Reserved | RO | 0x0
11 | SRC_ERR_UR_OR_DECERR | SRC_ERR:UR received PCIe if on PCIe domain, DECERR response received if on AXI domain | RO | 0
10 | SRC_ERR_EP_ECRC_OR_SLVERR | SRC_ERR:EP or ECRC received if on PCIe domain, SLVERR response received if on AXI domain | RO | 0
9 | SRC_ERR_CA_OR_EXOKAY | SRC_ERR:CA received if on PCIe domain, EXOKAY received if on AXI domain | RO | 0
8 | SCR_ERR_CMPL_TIMEOUT | SRC_ERR:Completion Timeout | RO | 0
7 | DMA_END | DMA incorrectly ended (buffer or descriptor not released). Note that if DMA ends because of an error, the Error Status field will be something other than 8?b0. This field is automatically cleared when DMA_CONTROL[0] is set to 1b. | RO | 0
6 | DMA_STOP | DMA successfully stopped by user | RO | 0
5 | reserved5 | Reserved | RO | 0
4 | DMA_CMPL | DMA Complete with more than 4GBytes of data transferred | RO | 0
3 | DMA_CMPL_ERR | DMA Complete with Error | RO | 0
2 | DMA_CMPL_EOC | DMA Complete with EOC received on last descriptor (if relevant) | RO | 0
1 | DMA_CMPL_EOP | DMA Complete with an EOP condition reported by the source of the transfer | RO | 0
0 | DMA_COMPL_LENGTH | DMA Complete with DMA_LENGTH reached | RO | 0

### PF_PCIE_BRIDGE : DMA0_PRC_LENGTH

Address offset | 0x000 0424
Physical address | 0x0300 4424 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8424 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | This 32-bit register provides the amount of data in bytes actually transferred from the Source to the Destination (DMA engine 0). It is only relevant if Bit 4 of the STATUS Field is cleared.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | DMA_PRC_LENGTH | Number of bytes trasnferred. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : DMA0_SHARE_ACCESS

Address offset | 0x000 0428
Physical address | 0x0300 4428 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8428 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | DMA Share access (DMA engine 0)
Type | RO

Bits | Field Name | Description | Type | Reset
31:11 | reserved11 | Reserved | RO | 0x00 0000
10:4 | VIR_FN_NUM | Virtual Function Number(1-64).If 0, then a physical function is targeted. These bits are only available if virtual functions are implemented. | RO | 0x00
3:2 | reserved2 | Reserved | RO | 0x0
1 | DMA_ACC_GNT | DMA Access Granted: Returns 1 when read by the Physical or Virtual Functions identified by Bits [10:4] or when DMA Access Locked is set to 0. Otherwise, it returns 0 | RO | 0
0 | DMA_ACC_LOCK | DMA Access Locked: When set to 1, write access to the DMA Engine registers is restricted to the Physical or Virtual Function identified by Bits [10:4]. Otherwise all functions are allowed write access. | RO | 0

### PF_PCIE_BRIDGE : DMA1_SRC_PARAM

Address offset | 0x000 0440
Physical address | 0x0300 4440 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8440 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | Source Parameters:DMA1_SRCPARAM is used to configure the source of the DMA Transfer(DMA engine 1), the transfer priority inside the Bridge IP Core, and the transfer parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved28 | RW | 0x0
27:16 | TRSF_PARAM | Provides the Transfer Parameters. Its content depends on the value of DEST_ID. | RW | 0x000
15:12 | reserved12 | Reserved12 | RW | 0x0
11:8 | TRSF_PRIOR | Defines the Transfer Priority inside the XpressRICH3-AXI. It is only relevant when Weighted Round Robin arbitration is implemented. The higher the priority value attributed, the lower the actual priority given. | RW | 0x0
7:4 | reserved4 | Reserved4 | RW | 0x0
3:0 | SRC_ID | Defines the Source interface ID of the DMA Transfer. When these register fields are not hardwired by Core Constants, they are read/write and their default value after reset is 4?h0 | RW | 0x4
|  | 0x0 | [SRC_ID_PCIE] PCIe Interface |  |
|  | 0x4 | [SRC_ID_AXIM0] AXI4-Master Interface Number 0 |  |
|  | 0x5 | [SRC_ID_AXIM1] AXI4-Master Interface Number 1 |  |
|  | 0x6 | [SRC_ID_AXIM2] AXI4-Master Interface Number 2 |  |
|  | 0x7 | [SRC_ID_AXIM3] AXI4-Master Interface Number 3 |  |
|  | 0x8 | [SRC_ID_AXIS0] AXI4-Stream Interface Number 0 |  |
|  | 0x9 | [SRC_ID_AXIS1] AXI4-Stream Interface Number 1 |  |
|  | 0xA | [SRC_ID_AXIS2] AXI4-Stream Interface Number 2 |  |
|  | 0xB | [SRC_ID_AXIS3] AXI4-Stream Interface Number 3 |  |

### PF_PCIE_BRIDGE : DMA1_DESTPARAM

Address offset | 0x000 0444
Physical address | 0x0300 4444 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8444 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | DMA1_DESTPARAM is used to configure the destination of the DMA Transfer(DMA engine 1), the transfer priority inside the Bridge IP Core, and the transfer parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved28 | RW | 0x0
27:16 | TRSF_PARAM | Provides the Transfer Parameters. Its content depends on the value of DEST_ID. | RW | 0x000
15:12 | reserved12 | Reserved12 | RW | 0x0
11:8 | TRSF_PRIOR | Defines the Transfer Priority inside the XpressRICH3-AXI. It is only relevant when Weighted Round Robin arbitration is implemented. The higher the priority value attributed, the lower the actual priority given. | RW | 0x0
7:4 | reserved4 | Reserved4 | RW | 0x0
3:0 | DEST_ID | Defines the Source interface ID of the DMA Transfer. When these register fields are not hardwired by Core Constants, they are read/write and their default value after reset is 4?h0 | RW | 0x0
|  | 0x0 | [DEST_ID_PCIE] PCIe Interface |  |
|  | 0x4 | [DEST_ID_AXIM0] AXI4-Master Interface Number 0 |  |
|  | 0x5 | [DEST_ID_AXIM1] AXI4-Master Interface Number 1 |  |
|  | 0x6 | [DEST_ID_AXIM2] AXI4-Master Interface Number 2 |  |
|  | 0x7 | [DEST_ID_AXIM3] AXI4-Master Interface Number 3 |  |
|  | 0x8 | [DEST_ID_AXIS0] AXI4-Stream Interface Number 0 |  |
|  | 0x9 | [DEST_ID_AXIS1] AXI4-Stream Interface Number 1 |  |
|  | 0xA | [DEST_ID_AXIS2] AXI4-Stream Interface Number 2 |  |
|  | 0xB | [DEST_ID_AXIS3] AXI4-Stream Interface Number 3 |  |

### PF_PCIE_BRIDGE : DMA1_SRCADDR_LDW

Address offset | 0x000 0448
Physical address | 0x0300 4448 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8448 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | This register provide the starting source address of the DMA Transfer(DMA engine 1).
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRCADDR_LDW | LSB 32 bits of the starting source address of DMA transfer. Note:When SG mode is enabled for the source (see DMA_CONTROL and DMA_LENGTH registers), DMA_SRCADDR provides the address of the first Source descriptor. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : DMA1_SRCADDR_UDW

Address offset | 0x000 044C
Physical address | 0x0300 444C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 844C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | This register provide the starting source address of the DMA Transfer(DMA engine0).
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRCADDR_UDW | MSB 32 bits of the starting source address of DMA transfer.If the actual source and destination address are less than 64-bits, MSB bits are ignored. Note:When SG mode is enabled for the source (see DMA_CONTROL and DMA_LENGTH registers), DMA_SRCADDR provides the address of the first Source descriptor. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : DMA1_DESTADDR_LDW

Address offset | 0x000 0450
Physical address | 0x0300 4450 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8450 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | This register provide the starting destination address of the DMA Transfer(DMA engine 1).Note that when SG Type Field is equal to 2?b11, DMA_DESTADDR is irrelevant as it is identical to DMA_SRCADDR.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | DESTADDR_LDW | LSB 32 bits of the starting destination address of DMA transfer. Note:When SG mode is enabled for the destination, DMA_DESTADDR provides the address of the first Destination descriptor. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : DMA1_DESTADDR_UDW

Address offset | 0x000 0454
Physical address | 0x0300 4454 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8454 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | This register provide the starting destination address of the DMA Transfer(DMA engine 1).Note that when SG Type Field is equal to 2?b11, DMA_DESTADDR is irrelevant as it is identical to DMA_SRCADDR.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | DESTADDR_UDW | MSB 32 bits of the starting destination address of DMA transfer.If the actual destination address is less than 64-bits, MSB bits are ignored. Note:When SG mode is enabled for the destination, DMA_DESTADDR provides the address of the first Destination descriptor. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : DMA1_LENGTH

Address offset | 0x000 0458
Physical address | 0x0300 4458 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8458 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | DMA_LENGTH Register provides the amount of data in bytes (up to 4GB) that should be transferred from the Source to the Destination (DMA engine 1)
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TRANSFER_LENGTH | Number of Bytesin DMA transfer. Note: If Bit 1 of the SE_COND Field is cleared, this value is only indicative and will be used to compute Bit 0 of the STATUS Field of the DMA_STATUS register. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : DMA1_CONTROL

Address offset | 0x000 045C
Physical address | 0x0300 445C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 845C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | DMA control (DMA engine 1)
Type | RW

Bits | Field Name | Description | Type | Reset
31:29 | SG2_ID | If SG_TYPE is set to 2?b00, SG_ID is connected to the Source and SG2_ID is connected to the Destination. Otherwise, SG_ID is connected to the Source and/or Destination, and SG2_ID is irrelevant.Constants, they are read/write and their default value after reset is 'b0. | RW | 0x0
|  | 0x0 | [SG2_ID_PCIE] PCIe Interface |  |
|  | 0x3 | [SG2_ID_AXI_MD] AXI4-Master Descriptor Interface |  |
|  | 0x4 | [SG2_ID_AXI_M0] AXI4-Master Interface Number 0 |  |
|  | 0x5 | [SG2_ID_AXI_M1] AXI4-Master Interface Number 1 |  |
|  | 0x6 | [SG2_ID_AXI_M2] AXI4-Master Interface Number 2 |  |
|  | 0x7 | [SG2_ID_AXI_M3] AXI4-Master Interface Number 3 |  |
28:26 | SG_ID | Defines on which interface the descriptors should be read | RW | 0x0
|  | 0x0 | [SG_ID_PCIE] PCIe Interface |  |
|  | 0x3 | [SG_ID_AXI_MD] AXI4-Master Descriptor Interface |  |
|  | 0x4 | [SG_ID_AXI_M0] AXI4-Master Interface Number 0 |  |
|  | 0x5 | [SG_ID_AXI_M1] AXI4-Master Interface Number 1 |  |
|  | 0x6 | [SG_ID_AXI_M2] AXI4-Master Interface Number 2 |  |
|  | 0x7 | [SG_ID_AXI_M3] AXI4-Master Interface Number 3 |  |
25:24 | SG_TYPE | Defines the Scatter-Gather type for the DMA (only relevant if bit 3 of CTRL Field is set). 2?b00: independent SG for both Source and Destination. 2?b01: Source address is set according to Descriptor, Destination address is incremented. 2?b10: Destination address is set according to Descriptor, Source address is incremented. 2?b11: Source and Destination addresses are set according to Descriptor. When this register field is not hardwired by Core Constants, it is read/write and its default value after reset is 2?b0. | RW | 0x0
23 | DESC_UPDT | Set to 1 by the application to indicate to the DMA Engine that a Descriptor has been updated. It is only relevant when SG mode is enabled and the DESC_NEXT_RDY field was set to 0 (see DESC_NEXT_RDY). This bit is automatically cleared by the DMA Engine. | RO | 0
22:14 | reserved14 | Reserved | RW | 0x000
13 | IRD_ID_PCIE | Interrupt is issued to the Host Processor (on PCIe domain). Note: Both these bits[bit 13 and bit 12] cannot be set to ?1? at the same time; to generate an interruption on both sides, you must enable interrupts on the AXI side, and use LOCAL_INTERRUPT_IN to generate interrupts on the PCIe side. If a DMA transfer event occurs, it is reported to ISTATUS_HOST and/or ISTATUS_LOCAL registers (see the ISTATUS register), depending on the IRQ_ID content. | RW | 0
12 | IRQ_ID_AXI | Interrupt is issued to the Local Processor (on AXI domain). | RW | 0
11 | reserved11 | Reserved | RW | 0
10 | IRQ_EOP | An IRQ is issued if the source of the transfer reports an EOP condition. | RW | 0
9 | IRQ_ERR | An IRQ is issued if an error occurs. | RW | 0
8 | IRQ_DMA_END | An IRQ is issued on a DMA end. | RW | 0
7 | SE_COND_ERR | Abort on error condition (otherwise erroneous packet or descriptor is considered as processed, but the error is logged in source and/or destination error fields).[7:4]SE_COND Defines the Start and End conditions of the DMA. | RW | 0
6 | SE_COND_AXI | If the DMA destination is an AXI-Stream Interface, generate an EOP at the end of the DMA. If the source of the DMA is an AXI-Stream Interface, stop the DMA if the source of the transfer reports an EOP condition. | RW | 0
5 | SE_COND_LEN | Stop if DMA_LENGTH is reached. | RW | 0
4 | SE_COND_START | Start on SOP reception (only relevant when the source is an AXI4 Stream Interface that is on data following a TLAST assertion). | RW | 0
3 | CTRL_SG_MODE | Enables SG mode. When this register field is not hardwired by Core Constants, it is read/write and its default value after reset is 0b. | RW | 0
2 | reserved2 | Reserved | RW | 0
1 | CTRL_PAUSE_RESUME | When set to 1b DMA transfer is paused (to temporarily give more bandwidth to a transfer with higher priority). | RW | 0
0 | CTRL_START_ABORT | When set to 1b, it launches the DMA transfer; appropriate registers should have previously been set. This bit is automatically cleared by the DMA Engine at the end of the DMA transfer. | RW | 0

### PF_PCIE_BRIDGE : DMA1_STATUS

Address offset | 0x000 0460
Physical address | 0x0300 4460 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8460 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | DMA status (DMA engine 1).
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | reserved24 | Reserved | RO | 0x00
23:20 | reserved20 | Reserved | RO | 0x0
19 | DEST_ERR_UR_OR_DECERR | DEST_ERR:UR received PCIe if on PCIe domain, DECERR response received if on AXI domain | RO | 0
18 | DEST_ERR_EP_ECRC_OR_SLVERR | DEST_ERR:EP or ECRC received if on PCIe domain, SLVERR response received if on AXI domain | RO | 0
17 | DEST_ERR_CA_OR_EXOKAY | DEST_ERR:CA received if on PCIe domain, EXOKAY received if on AXI domain | RO | 0
16 | DEST_ERR_CMPL_TIMEOUT | DEST_ERR:Completion Timeout | RO | 0
15:12 | reserved12 | Reserved | RO | 0x0
11 | SRC_ERR_UR_OR_DECERR | SRC_ERR:UR received PCIe if on PCIe domain, DECERR response received if on AXI domain | RO | 0
10 | SRC_ERR_EP_ECRC_OR_SLVERR | SRC_ERR:EP or ECRC received if on PCIe domain, SLVERR response received if on AXI domain | RO | 0
9 | SRC_ERR_CA_OR_EXOKAY | SRC_ERR:CA received if on PCIe domain, EXOKAY received if on AXI domain | RO | 0
8 | SCR_ERR_CMPL_TIMEOUT | SRC_ERR:Completion Timeout | RO | 0
7 | DMA_END | DMA incorrectly ended (buffer or descriptor not released). Note that if DMA ends because of an error, the Error Status field will be something other than 8?b0. This field is automatically cleared when DMA_CONTROL[0] is set to 1b. | RO | 0
6 | DMA_STOP | DMA successfully stopped by user | RO | 0
5 | reserved5 | Reserved | RO | 0
4 | DMA_CMPL | DMA Complete with more than 4GBytes of data transferred | RO | 0
3 | DMA_CMPL_ERR | DMA Complete with Error | RO | 0
2 | DMA_CMPL_EOC | DMA Complete with EOC received on last descriptor (if relevant) | RO | 0
1 | DMA_CMPL_EOP | DMA Complete with an EOP condition reported by the source of the transfer | RO | 0
0 | DMA_COMPL_LENGTH | DMA Complete with DMA_LENGTH reached | RO | 0

### PF_PCIE_BRIDGE : DMA1_PRC_LENGTH

Address offset | 0x000 0464
Physical address | 0x0300 4464 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8464 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | This 32-bit register provides the amount of data in bytes actually transferred from the Source to the Destination (DMA engine 1). It is only relevant if Bit 4 of the STATUS Field is cleared.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | DMA_PRC_LENGTH | Number of bytes trasnferred. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : DMA1_SHARE_ACCESS

Address offset | 0x000 0468
Physical address | 0x0300 4468 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8468 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | DMA Share access (DMA engine 1)
Type | RO

Bits | Field Name | Description | Type | Reset
31:11 | reserved11 | Reserved | RO | 0x00 0000
10:4 | VIR_FN_NUM | Virtual Function Number(1-64).If 0, then a physical function is targeted. These bits are only available if virtual functions are implemented. | RO | 0x00
3:2 | reserved2 | Reserved | RO | 0x0
1 | DMA_ACC_GNT | DMA Access Granted: Returns 1 when read by the Physical or Virtual Functions identified by Bits [10:4] or when DMA Access Locked is set to 0. Otherwise, it returns 0 | RO | 0
0 | DMA_ACC_LOCK | DMA Access Locked: When set to 1, write access to the DMA Engine registers is restricted to the Physical or Virtual Function identified by Bits [10:4]. Otherwise all functions are allowed write access. | RO | 0

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN0_SRCADDR_PARAM

Address offset | 0x000 0600
Physical address | 0x0300 4600 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8600 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN0_SRCADDR_PARAM: PCIe Window 0 Address Translation Table 0 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LDW | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x0B
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 1

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN0_SRC_ADDR

Address offset | 0x000 0604
Physical address | 0x0300 4604 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8604 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN0_SRC_ADDR: PCIe Window 0 Address Translation Table 0 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN0_TRSL_ADDR_LSB

Address offset | 0x000 0608
Physical address | 0x0300 4608 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8608 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN0_TRSL_ADDR_LSB: PCIe Window 0 Address Translation Table 0 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR_LDW | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN0_TRSL_ADDR_UDW

Address offset | 0x000 060C
Physical address | 0x0300 460C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 860C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN0: PCIe Window 0 Address Translation Table 0 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR_UDW | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN0_TRSL_PARAM

Address offset | 0x000 0610
Physical address | 0x0300 4610 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8610 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN0_TRSL_PARAM: PCIe Window 0 Address Translation Table 0 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0xC
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN0_TRSL_MASK_DW0

Address offset | 0x000 0618
Physical address | 0x0300 4618 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8618 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 0 TRSL_MASK defines the translation table mask address (bits [31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF F000

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN0_TRSL_MASK_DW1

Address offset | 0x000 061C
Physical address | 0x0300 461C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 861C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 0 TRSL_MASK defines the translation table mask address (bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF FFFF

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN0_SRCADDR_PARAM

Address offset | 0x000 0620
Physical address | 0x0300 4620 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8620 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN0_SRCADDR_PARAM: PCIe Window 0 Address Translation Table 1 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LDW | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x0B
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN0_SRC_ADDR

Address offset | 0x000 0624
Physical address | 0x0300 4624 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8624 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN0_SRC_ADDR: PCIe Window 0 Address Translation Table 1 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN0_TRSL_ADDR_LSB

Address offset | 0x000 0628
Physical address | 0x0300 4628 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8628 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN0_TRSL_ADDR_LSB: PCIe Window 0 Address Translation Table 1 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR_LDW | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN0_TRSL_ADDR_UDW

Address offset | 0x000 062C
Physical address | 0x0300 462C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 862C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN0: PCIe Window 0 Address Translation Table 1 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR_UDW | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN0_TRSL_PARAM

Address offset | 0x000 0630
Physical address | 0x0300 4630 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8630 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN0_TRSL_PARAM: PCIe Window 0 Address Translation Table 1 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x1
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN0_TRSL_MASK_DW0

Address offset | 0x000 0638
Physical address | 0x0300 4638 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8638 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 1 TRSL_MASK defines the translation table mask address bits[31:0]
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF F000

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN0_TRSL_MASK_DW1

Address offset | 0x000 063C
Physical address | 0x0300 463C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 863C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 1 TRSL_MASK defines the translation table mask address bits[63:32]
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF FFFF

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN0_SRCADDR_PARAM

Address offset | 0x000 0640
Physical address | 0x0300 4640 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8640 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN0_SRCADDR_PARAM: PCIe Window 0 Address Translation Table 2 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LDW | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x0C
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 1

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN0_SRC_ADDR

Address offset | 0x000 0644
Physical address | 0x0300 4644 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8644 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN0_SRC_ADDR: PCIe Window 0 Address Translation Table 2 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN0_TRSL_ADDR_LSB

Address offset | 0x000 0648
Physical address | 0x0300 4648 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8648 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN0_TRSL_ADDR_LSB: PCIe Window 0 Address Translation Table 2 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR_LDW | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN0_TRSL_ADDR_UDW

Address offset | 0x000 064C
Physical address | 0x0300 464C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 864C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN0: PCIe Window 0 Address Translation Table 2 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR_UDW | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN0_TRSL_PARAM

Address offset | 0x000 0650
Physical address | 0x0300 4650 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8650 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN0_TRSL_PARAM: PCIe Window 0 Address Translation Table 2 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x4
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN0_TRSL_MASK_DW0

Address offset | 0x000 0658
Physical address | 0x0300 4658 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8658 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 2 TRSL_MASK defines the translation table mask address (bit[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF F000

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN0_TRSL_MASK_DW1

Address offset | 0x000 065C
Physical address | 0x0300 465C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 865C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 2 TRSL_MASK defines the translation table mask address (bits [31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF FFFF

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN0_SRCADDR_PARAM

Address offset | 0x000 0660
Physical address | 0x0300 4660 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8660 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN0_SRCADDR_PARAM: PCIe Window 0 Address Translation Table 3 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LDW | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x0B
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN0_SRC_ADDR

Address offset | 0x000 0664
Physical address | 0x0300 4664 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8664 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN0_SRC_ADDR: PCIe Window 0 Address Translation Table 3 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN0_TRSL_ADDR_LSB

Address offset | 0x000 0668
Physical address | 0x0300 4668 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8668 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN0_TRSL_ADDR_LSB: PCIe Window 0 Address Translation Table 3 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR_LDW | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN0_TRSL_ADDR_UDW

Address offset | 0x000 066C
Physical address | 0x0300 466C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 866C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN0: PCIe Window 0 Address Translation Table 3 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR_UDW | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN0_TRSL_PARAM

Address offset | 0x000 0670
Physical address | 0x0300 4670 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8670 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN0_TRSL_PARAM: PCIe Window 0 Address Translation Table 3 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x1
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN0_TRSL_MASK_DW0

Address offset | 0x000 0678
Physical address | 0x0300 4678 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8678 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 3 TRSL_MASK defines the translation table mask address (bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF F000

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN0_TRSL_MASK_DW1

Address offset | 0x000 067C
Physical address | 0x0300 467C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 867C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 3 TRSL_MASK defines the translation table mask address (bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF FFFF

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN0_SRCADDR_PARAM

Address offset | 0x000 0680
Physical address | 0x0300 4680 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8680 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN0_SRCADDR_PARAM: PCIe Window 0 Address Translation Table 4 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LDW | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN0_SRC_ADDR

Address offset | 0x000 0684
Physical address | 0x0300 4684 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8684 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN0_SRC_ADDR: PCIe Window 0 Address Translation Table 4 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN0_TRSL_ADDR_LSB

Address offset | 0x000 0688
Physical address | 0x0300 4688 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8688 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN0_TRSL_ADDR_LSB: PCIe Window 0 Address Translation Table 4 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR_LDW | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN0_TRSL_ADDR_UDW

Address offset | 0x000 068C
Physical address | 0x0300 468C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 868C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN0: PCIe Window 0 Address Translation Table 4 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR_UDW | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN0_TRSL_PARAM

Address offset | 0x000 0690
Physical address | 0x0300 4690 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8690 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN0_TRSL_PARAM: PCIe Window 0 Address Translation Table 4 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x4
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN0_TRSL_MASK_DW0

Address offset | 0x000 0698
Physical address | 0x0300 4698 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8698 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 4 TRSL_MASK defines the translation table mask address (bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF F000

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN0_TRSL_MASK_DW1

Address offset | 0x000 069C
Physical address | 0x0300 469C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 869C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 4 TRSL_MASK defines the translation table mask address (bits [63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF FFFF

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN0_SRCADDR_PARAM

Address offset | 0x000 06A0
Physical address | 0x0300 46A0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86A0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN0_SRCADDR_PARAM: PCIe Window 0 Address Translation Table 5 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x0B
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN0_SRC_ADDR

Address offset | 0x000 06A4
Physical address | 0x0300 46A4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86A4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN0_SRC_ADDR: PCIe Window 0 Address Translation Table 5 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN0_TRSL_ADDR_LSB

Address offset | 0x000 06A8
Physical address | 0x0300 46A8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86A8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN0_TRSL_ADDR_LSB: PCIe Window 0 Address Translation Table 5 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN0_TRSL_ADDR_UDW

Address offset | 0x000 06AC
Physical address | 0x0300 46AC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86AC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN0: PCIe Window 0 Address Translation Table 5 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN0_TRSL_PARAM

Address offset | 0x000 06B0
Physical address | 0x0300 46B0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86B0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN0_TRSL_PARAM: PCIe Window 0 Address Translation Table 5 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x4
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN0_TRSL_MASK_DW0

Address offset | 0x000 06B8
Physical address | 0x0300 46B8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86B8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 5 TRSL_MASK defines the translation table mask address (bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF F000

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN0_TRSL_MASK_DW1

Address offset | 0x000 06BC
Physical address | 0x0300 46BC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86BC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 5 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF FFFF

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN0_SRCADDR_PARAM

Address offset | 0x000 06C0
Physical address | 0x0300 46C0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86C0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN0_SRCADDR_PARAM: PCIe Window 0 Address Translation Table 6 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x0B
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN0_SRC_ADDR

Address offset | 0x000 06C4
Physical address | 0x0300 46C4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86C4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN0_SRC_ADDR: PCIe Window 0 Address Translation Table 6 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN0_TRSL_ADDR_LSB

Address offset | 0x000 06C8
Physical address | 0x0300 46C8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86C8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN0_TRSL_ADDR_LSB: PCIe Window 0 Address Translation Table 6 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN0_TRSL_ADDR_UDW

Address offset | 0x000 06CC
Physical address | 0x0300 46CC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86CC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN0: PCIe Window 0 Address Translation Table 6 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN0_TRSL_PARAM

Address offset | 0x000 06D0
Physical address | 0x0300 46D0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86D0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN0_TRSL_PARAM: PCIe Window 0 Address Translation Table 6 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x4
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN0_TRSL_MASK_DW0

Address offset | 0x000 06D8
Physical address | 0x0300 46D8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86D8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 6 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF F000

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN0_TRSL_MASK_DW1

Address offset | 0x000 06DC
Physical address | 0x0300 46DC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86DC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 6 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF FFFF

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN0_SRCADDR_PARAM

Address offset | 0x000 06E0
Physical address | 0x0300 46E0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86E0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN0_SRCADDR_PARAM: PCIe Window 0 Address Translation Table 7 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x0B
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN0_SRC_ADDR

Address offset | 0x000 06E4
Physical address | 0x0300 46E4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86E4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN0_SRC_ADDR: PCIe Window 0 Address Translation Table 7 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN0_TRSL_ADDR_LSB

Address offset | 0x000 06E8
Physical address | 0x0300 46E8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86E8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN0_TRSL_ADDR_LSB: PCIe Window 0 Address Translation Table 7 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN0_TRSL_ADDR_UDW

Address offset | 0x000 06EC
Physical address | 0x0300 46EC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86EC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN0: PCIe Window 0 Address Translation Table 7 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN0_TRSL_PARAM

Address offset | 0x000 06F0
Physical address | 0x0300 46F0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86F0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN0_TRSL_PARAM: PCIe Window 0 Address Translation Table 7 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x4
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN0_TRSL_MASK_DW0

Address offset | 0x000 06F8
Physical address | 0x0300 46F8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86F8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 7 TRSL_MASK defines the translation table mask address(bits [31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF F000

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN0_TRSL_MASK_DW1

Address offset | 0x000 06FC
Physical address | 0x0300 46FC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 86FC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN0_TRSL_MASK: PCIe Window 0 Address Translation Table 7 TRSL_MASK defines the translation table mask address(bits[62:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0xFFFF FFFF

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN1_SRCADDR_PARAM

Address offset | 0x000 0700
Physical address | 0x0300 4700 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8700 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN1_SRCADDR_PARAM: PCIe Window 1 Address Translation Table 0 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN1_SRC_ADDR

Address offset | 0x000 0704
Physical address | 0x0300 4704 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8704 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN1_SRC_ADDR: PCIe Window 1 Address Translation Table 0 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN1_TRSL_ADDR_LSB

Address offset | 0x000 0708
Physical address | 0x0300 4708 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8708 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN1_TRSL_ADDR_LSB: PCIe Window 1 Address Translation Table 0 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN1_TRSL_ADDR_UDW

Address offset | 0x000 070C
Physical address | 0x0300 470C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 870C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN1: PCIe Window 1 Address Translation Table 0 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN1_TRSL_PARAM

Address offset | 0x000 0710
Physical address | 0x0300 4710 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8710 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN1_TRSL_PARAM: PCIe Window 1 Address Translation Table 0 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN1_TRSL_MASK_DW0

Address offset | 0x000 0718
Physical address | 0x0300 4718 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8718 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 0 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR0_PCIE_WIN1_TRSL_MASK_DW1

Address offset | 0x000 071C
Physical address | 0x0300 471C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 871C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 0 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN1_SRCADDR_PARAM

Address offset | 0x000 0720
Physical address | 0x0300 4720 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8720 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN1_SRCADDR_PARAM: PCIe Window 1 Address Translation Table 1 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN1_SRC_ADDR

Address offset | 0x000 0724
Physical address | 0x0300 4724 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8724 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN1_SRC_ADDR: PCIe Window 1 Address Translation Table 1 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN1_TRSL_ADDR_LSB

Address offset | 0x000 0728
Physical address | 0x0300 4728 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8728 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN1_TRSL_ADDR_LSB: PCIe Window 1 Address Translation Table 1 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN1_TRSL_ADDR_UDW

Address offset | 0x000 072C
Physical address | 0x0300 472C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 872C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN1: PCIe Window 1 Address Translation Table 1 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN1_TRSL_PARAM

Address offset | 0x000 0730
Physical address | 0x0300 4730 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8730 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN1_TRSL_PARAM: PCIe Window 1 Address Translation Table 1 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN1_TRSL_MASK_DW0

Address offset | 0x000 0738
Physical address | 0x0300 4738 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8738 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 1 TRSL_MASK defines the translation table mask address (bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR1_PCIE_WIN1_TRSL_MASK_DW1

Address offset | 0x000 073C
Physical address | 0x0300 473C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 873C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 1 TRSL_MASK defines the translation table mask address(bbits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN1_SRCADDR_PARAM

Address offset | 0x000 0740
Physical address | 0x0300 4740 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8740 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN1_SRCADDR_PARAM: PCIe Window 1 Address Translation Table 2 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN1_SRC_ADDR

Address offset | 0x000 0744
Physical address | 0x0300 4744 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8744 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN1_SRC_ADDR: PCIe Window 1 Address Translation Table 2 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN1_TRSL_ADDR_LSB

Address offset | 0x000 0748
Physical address | 0x0300 4748 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8748 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN1_TRSL_ADDR_LSB: PCIe Window 1 Address Translation Table 2 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN1_TRSL_ADDR_UDW

Address offset | 0x000 074C
Physical address | 0x0300 474C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 874C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN1: PCIe Window 1 Address Translation Table 2 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN1_TRSL_PARAM

Address offset | 0x000 0750
Physical address | 0x0300 4750 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8750 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN1_TRSL_PARAM: PCIe Window 1 Address Translation Table 2 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN1_TRSL_MASK_DW0

Address offset | 0x000 0758
Physical address | 0x0300 4758 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8758 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 2 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR2_PCIE_WIN1_TRSL_MASK_DW1

Address offset | 0x000 075C
Physical address | 0x0300 475C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 875C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 2 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN1_SRCADDR_PARAM

Address offset | 0x000 0760
Physical address | 0x0300 4760 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8760 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN1_SRCADDR_PARAM: PCIe Window 1 Address Translation Table 3 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN1_SRC_ADDR

Address offset | 0x000 0764
Physical address | 0x0300 4764 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8764 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN1_SRC_ADDR: PCIe Window 1 Address Translation Table 3 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN1_TRSL_ADDR_LSB

Address offset | 0x000 0768
Physical address | 0x0300 4768 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8768 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN1_TRSL_ADDR_LSB: PCIe Window 1 Address Translation Table 3 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN1_TRSL_ADDR_UDW

Address offset | 0x000 076C
Physical address | 0x0300 476C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 876C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN1: PCIe Window 1 Address Translation Table 3 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN1_TRSL_PARAM

Address offset | 0x000 0770
Physical address | 0x0300 4770 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8770 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN1_TRSL_PARAM: PCIe Window 1 Address Translation Table 3 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN1_TRSL_MASK_DW0

Address offset | 0x000 0778
Physical address | 0x0300 4778 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8778 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 3 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR3_PCIE_WIN1_TRSL_MASK_DW1

Address offset | 0x000 077C
Physical address | 0x0300 477C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 877C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 3 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN1_SRCADDR_PARAM

Address offset | 0x000 0780
Physical address | 0x0300 4780 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8780 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN1_SRCADDR_PARAM: PCIe Window 1 Address Translation Table 4 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN1_SRC_ADDR

Address offset | 0x000 0784
Physical address | 0x0300 4784 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8784 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN1_SRC_ADDR: PCIe Window 1 Address Translation Table 4 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN1_TRSL_ADDR_LSB

Address offset | 0x000 0788
Physical address | 0x0300 4788 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8788 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN1_TRSL_ADDR_LSB: PCIe Window 1 Address Translation Table 4 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN1_TRSL_ADDR_UDW

Address offset | 0x000 078C
Physical address | 0x0300 478C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 878C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN1: PCIe Window 1 Address Translation Table 4 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN1_TRSL_PARAM

Address offset | 0x000 0790
Physical address | 0x0300 4790 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8790 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN1_TRSL_PARAM: PCIe Window 1 Address Translation Table 4 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN1_TRSL_MASK_DW0

Address offset | 0x000 0798
Physical address | 0x0300 4798 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8798 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 4 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR4_PCIE_WIN1_TRSL_MASK_DW1

Address offset | 0x000 079C
Physical address | 0x0300 479C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 879C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 4 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN1_SRCADDR_PARAM

Address offset | 0x000 07A0
Physical address | 0x0300 47A0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87A0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN1_SRCADDR_PARAM: PCIe Window 1 Address Translation Table 5 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN1_SRC_ADDR

Address offset | 0x000 07A4
Physical address | 0x0300 47A4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87A4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN1_SRC_ADDR: PCIe Window 1 Address Translation Table 5 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN1_TRSL_ADDR_LSB

Address offset | 0x000 07A8
Physical address | 0x0300 47A8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87A8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN1_TRSL_ADDR_LSB: PCIe Window 1 Address Translation Table 5 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN1_TRSL_ADDR_UDW

Address offset | 0x000 07AC
Physical address | 0x0300 47AC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87AC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN1: PCIe Window 1 Address Translation Table 5 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN1_TRSL_PARAM

Address offset | 0x000 07B0
Physical address | 0x0300 47B0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87B0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN1_TRSL_PARAM: PCIe Window 1 Address Translation Table 5 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN1_TRSL_MASK_DW0

Address offset | 0x000 07B8
Physical address | 0x0300 47B8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87B8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 5 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR5_PCIE_WIN1_TRSL_MASK_DW1

Address offset | 0x000 07BC
Physical address | 0x0300 47BC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87BC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 5 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN1_SRCADDR_PARAM

Address offset | 0x000 07C0
Physical address | 0x0300 47C0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87C0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN1_SRCADDR_PARAM: PCIe Window 1 Address Translation Table 6 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN1_SRC_ADDR

Address offset | 0x000 07C4
Physical address | 0x0300 47C4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87C4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN1_SRC_ADDR: PCIe Window 1 Address Translation Table 6 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN1_TRSL_ADDR_LSB

Address offset | 0x000 07C8
Physical address | 0x0300 47C8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87C8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN1_TRSL_ADDR_LSB: PCIe Window 1 Address Translation Table 6 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN1_TRSL_ADDR_UDW

Address offset | 0x000 07CC
Physical address | 0x0300 47CC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87CC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN1: PCIe Window 1 Address Translation Table 6 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN1_TRSL_PARAM

Address offset | 0x000 07D0
Physical address | 0x0300 47D0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87D0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN1_TRSL_PARAM: PCIe Window 1 Address Translation Table 6 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN1_TRSL_MASK_DW0

Address offset | 0x000 07D8
Physical address | 0x0300 47D8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87D8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 6 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR6_PCIE_WIN1_TRSL_MASK_DW1

Address offset | 0x000 07DC
Physical address | 0x0300 47DC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87DC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 6 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN1_SRCADDR_PARAM

Address offset | 0x000 07E0
Physical address | 0x0300 47E0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87E0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN1_SRCADDR_PARAM: PCIe Window 1 Address Translation Table 7 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN1_SRC_ADDR

Address offset | 0x000 07E4
Physical address | 0x0300 47E4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87E4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN1_SRC_ADDR: PCIe Window 1 Address Translation Table 7 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN1_TRSL_ADDR_LSB

Address offset | 0x000 07E8
Physical address | 0x0300 47E8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87E8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN1_TRSL_ADDR_LSB: PCIe Window 1 Address Translation Table 7 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN1_TRSL_ADDR_UDW

Address offset | 0x000 07EC
Physical address | 0x0300 47EC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87EC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN1: PCIe Window 1 Address Translation Table 7 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN1_TRSL_PARAM

Address offset | 0x000 07F0
Physical address | 0x0300 47F0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87F0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN1_TRSL_PARAM: PCIe Window 1 Address Translation Table 7 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN1_TRSL_MASK_DW0

Address offset | 0x000 07F8
Physical address | 0x0300 47F8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87F8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 7 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR7_PCIE_WIN1_TRSL_MASK_DW1

Address offset | 0x000 07FC
Physical address | 0x0300 47FC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 87FC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_PCIE_WIN1_TRSL_MASK: PCIe Window 1 Address Translation Table 7 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR0_AXI4_SLV0_SRCADDR_PARAM

Address offset | 0x000 0800
Physical address | 0x0300 4800 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8800 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_AXI4_SLV0_SRCADDR_PARAM: AXI4 Slave 0 Address Translation Table 0 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR0_AXI4_SLV0_SRC_ADDR

Address offset | 0x000 0804
Physical address | 0x0300 4804 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8804 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_AXI4_SLV0_SRC_ADDR: AXI4 Slave 0 Address Translation Table 0 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR0_AXI4_SLV0_TRSL_ADDR_LSB

Address offset | 0x000 0808
Physical address | 0x0300 4808 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8808 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_AXI4_SLV0_TRSL_ADDR_LSB: AXI4 Slave 0 Address Translation Table 0 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR0_AXI4_SLV0_TRSL_ADDR_UDW

Address offset | 0x000 080C
Physical address | 0x0300 480C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 880C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_AXI4_SLV0: AXI4 Slave 0 Address Translation Table 0 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR0_AXI4_SLV0_TRSL_PARAM

Address offset | 0x000 0810
Physical address | 0x0300 4810 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8810 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_AXI4_SLV0_TRSL_PARAM: AXI4 Slave 0 Address Translation Table 0 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR0_AXI4_SLV0_TRSL_MASK_DW0

Address offset | 0x000 0818
Physical address | 0x0300 4818 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8818 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 0 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR0_AXI4_SLV0_TRSL_MASK_DW1

Address offset | 0x000 081C
Physical address | 0x0300 481C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 881C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR0_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 0 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR1_AXI4_SLV0_SRCADDR_PARAM

Address offset | 0x000 0820
Physical address | 0x0300 4820 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8820 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_AXI4_SLV0_SRCADDR_PARAM: AXI4 Slave 0 Address Translation Table 1 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR1_AXI4_SLV0_SRC_ADDR

Address offset | 0x000 0824
Physical address | 0x0300 4824 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8824 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_AXI4_SLV0_SRC_ADDR: AXI4 Slave 0 Address Translation Table 1 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR1_AXI4_SLV0_TRSL_ADDR_LSB

Address offset | 0x000 0828
Physical address | 0x0300 4828 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8828 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_AXI4_SLV0_TRSL_ADDR_LSB: AXI4 Slave 0 Address Translation Table 1 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR1_AXI4_SLV0_TRSL_ADDR_UDW

Address offset | 0x000 082C
Physical address | 0x0300 482C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 882C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_AXI4_SLV0: AXI4 Slave 0 Address Translation Table 1 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR1_AXI4_SLV0_TRSL_PARAM

Address offset | 0x000 0830
Physical address | 0x0300 4830 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8830 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_AXI4_SLV0_TRSL_PARAM: AXI4 Slave 0 Address Translation Table 1 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR1_AXI4_SLV0_TRSL_MASK_DW0

Address offset | 0x000 0838
Physical address | 0x0300 4838 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8838 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 1 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR1_AXI4_SLV0_TRSL_MASK_DW1

Address offset | 0x000 083C
Physical address | 0x0300 483C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 883C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR1_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 1 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR2_AXI4_SLV0_SRCADDR_PARAM

Address offset | 0x000 0840
Physical address | 0x0300 4840 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8840 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_AXI4_SLV0_SRCADDR_PARAM: AXI4 Slave 0 Address Translation Table 2 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR2_AXI4_SLV0_SRC_ADDR

Address offset | 0x000 0844
Physical address | 0x0300 4844 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8844 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_AXI4_SLV0_SRC_ADDR: AXI4 Slave 0 Address Translation Table 2 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR2_AXI4_SLV0_TRSL_ADDR_LSB

Address offset | 0x000 0848
Physical address | 0x0300 4848 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8848 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_AXI4_SLV0_TRSL_ADDR_LSB: AXI4 Slave 0 Address Translation Table 2 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR2_AXI4_SLV0_TRSL_ADDR_UDW

Address offset | 0x000 084C
Physical address | 0x0300 484C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 884C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_AXI4_SLV0: AXI4 Slave 0 Address Translation Table 2 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR2_AXI4_SLV0_TRSL_PARAM

Address offset | 0x000 0850
Physical address | 0x0300 4850 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8850 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_AXI4_SLV0_TRSL_PARAM: AXI4 Slave 0 Address Translation Table 2 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR2_AXI4_SLV0_TRSL_MASK_DW0

Address offset | 0x000 0858
Physical address | 0x0300 4858 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8858 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 2 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR2_AXI4_SLV0_TRSL_MASK_DW1

Address offset | 0x000 085C
Physical address | 0x0300 485C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 885C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR2_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 2 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR3_AXI4_SLV0_SRCADDR_PARAM

Address offset | 0x000 0860
Physical address | 0x0300 4860 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8860 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_AXI4_SLV0_SRCADDR_PARAM: AXI4 Slave 0 Address Translation Table 3 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR3_AXI4_SLV0_SRC_ADDR

Address offset | 0x000 0864
Physical address | 0x0300 4864 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8864 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_AXI4_SLV0_SRC_ADDR: AXI4 Slave 0 Address Translation Table 3 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR3_AXI4_SLV0_TRSL_ADDR_LSB

Address offset | 0x000 0868
Physical address | 0x0300 4868 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8868 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_AXI4_SLV0_TRSL_ADDR_LSB: AXI4 Slave 0 Address Translation Table 3 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR3_AXI4_SLV0_TRSL_ADDR_UDW

Address offset | 0x000 086C
Physical address | 0x0300 486C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 886C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_AXI4_SLV0: AXI4 Slave 0 Address Translation Table 3 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR3_AXI4_SLV0_TRSL_PARAM

Address offset | 0x000 0870
Physical address | 0x0300 4870 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8870 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_AXI4_SLV0_TRSL_PARAM: AXI4 Slave 0 Address Translation Table 3 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR3_AXI4_SLV0_TRSL_MASK_DW0

Address offset | 0x000 0878
Physical address | 0x0300 4878 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8878 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 3 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR3_AXI4_SLV0_TRSL_MASK_DW1

Address offset | 0x000 087C
Physical address | 0x0300 487C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 887C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR3_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 3 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR4_AXI4_SLV0_SRCADDR_PARAM

Address offset | 0x000 0880
Physical address | 0x0300 4880 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8880 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_AXI4_SLV0_SRCADDR_PARAM: AXI4 Slave 0 Address Translation Table 4 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR4_AXI4_SLV0_SRC_ADDR

Address offset | 0x000 0884
Physical address | 0x0300 4884 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8884 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_AXI4_SLV0_SRC_ADDR: AXI4 Slave 0 Address Translation Table 4 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR4_AXI4_SLV0_TRSL_ADDR_LSB

Address offset | 0x000 0888
Physical address | 0x0300 4888 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8888 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_AXI4_SLV0_TRSL_ADDR_LSB: AXI4 Slave 0 Address Translation Table 4 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR4_AXI4_SLV0_TRSL_ADDR_UDW

Address offset | 0x000 088C
Physical address | 0x0300 488C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 888C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_AXI4_SLV0: AXI4 Slave 0 Address Translation Table 4 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR4_AXI4_SLV0_TRSL_PARAM

Address offset | 0x000 0890
Physical address | 0x0300 4890 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8890 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_AXI4_SLV0_TRSL_PARAM: AXI4 Slave 0 Address Translation Table 4 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR4_AXI4_SLV0_TRSL_MASK_DW0

Address offset | 0x000 0898
Physical address | 0x0300 4898 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 8898 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 4 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR4_AXI4_SLV0_TRSL_MASK_DW1

Address offset | 0x000 089C
Physical address | 0x0300 489C | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 889C |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR4_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 4 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR5_AXI4_SLV0_SRCADDR_PARAM

Address offset | 0x000 08A0
Physical address | 0x0300 48A0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88A0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_AXI4_SLV0_SRCADDR_PARAM: AXI4 Slave 0 Address Translation Table 5 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR5_AXI4_SLV0_SRC_ADDR

Address offset | 0x000 08A4
Physical address | 0x0300 48A4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88A4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_AXI4_SLV0_SRC_ADDR: AXI4 Slave 0 Address Translation Table 5 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR5_AXI4_SLV0_TRSL_ADDR_LSB

Address offset | 0x000 08A8
Physical address | 0x0300 48A8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88A8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_AXI4_SLV0_TRSL_ADDR_LSB: AXI4 Slave 0 Address Translation Table 5 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR5_AXI4_SLV0_TRSL_ADDR_UDW

Address offset | 0x000 08AC
Physical address | 0x0300 48AC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88AC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_AXI4_SLV0: AXI4 Slave 0 Address Translation Table 5 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR5_AXI4_SLV0_TRSL_PARAM

Address offset | 0x000 08B0
Physical address | 0x0300 48B0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88B0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_AXI4_SLV0_TRSL_PARAM: AXI4 Slave 0 Address Translation Table 5 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR5_AXI4_SLV0_TRSL_MASK_DW0

Address offset | 0x000 08B8
Physical address | 0x0300 48B8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88B8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 5 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR5_AXI4_SLV0_TRSL_MASK_DW1

Address offset | 0x000 08BC
Physical address | 0x0300 48BC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88BC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR5_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 5 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR6_AXI4_SLV0_SRCADDR_PARAM

Address offset | 0x000 08C0
Physical address | 0x0300 48C0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88C0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_AXI4_SLV0_SRCADDR_PARAM: AXI4 Slave 0 Address Translation Table 6 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LSB | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR6_AXI4_SLV0_SRC_ADDR

Address offset | 0x000 08C4
Physical address | 0x0300 48C4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88C4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_AXI4_SLV0_SRC_ADDR: AXI4 Slave 0 Address Translation Table 6 Source Address MSB.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR6_AXI4_SLV0_TRSL_ADDR_LSB

Address offset | 0x000 08C8
Physical address | 0x0300 48C8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88C8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_AXI4_SLV0_TRSL_ADDR_LSB: AXI4 Slave 0 Address Translation Table 6 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR6_AXI4_SLV0_TRSL_ADDR_UDW

Address offset | 0x000 08CC
Physical address | 0x0300 48CC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88CC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_AXI4_SLV0: AXI4 Slave 0 Address Translation Table 6 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR_UDW | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR6_AXI4_SLV0_TRSL_PARAM

Address offset | 0x000 08D0
Physical address | 0x0300 48D0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88D0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_AXI4_SLV0_TRSL_PARAM: AXI4 Slave 0 Address Translation Table 6 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR6_AXI4_SLV0_TRSL_MASK_DW0

Address offset | 0x000 08D8
Physical address | 0x0300 48D8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88D8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 6 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR6_AXI4_SLV0_TRSL_MASK_DW1

Address offset | 0x000 08DC
Physical address | 0x0300 48DC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88DC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR6_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 6 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR7_AXI4_SLV0_SRCADDR_PARAM

Address offset | 0x000 08E0
Physical address | 0x0300 48E0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88E0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_AXI4_SLV0_SRCADDR_PARAM: AXI4 Slave 0 Address Translation Table 7 Source Address and ATR parameters.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | SRC_ADDR_LDW | SRC_ADDR[31:12] | RW | 0x0 0000
11:7 | reserved7 | Reserved | RW | 0x00
6:1 | ATR_SIZE | ATR_SIZE is 6 bits long and defines the Address Translation Space Size. This space size in bytes is equal to 2^(ATR_SIZE +1). Allowed values for this field are from 6?d11 (2^12 = 4 KBytes) to 6?d63 (2^64 = 16 ExaBytes) only. | RW | 0x00
0 | ATR_IMPL | When set to 1, it indicates that the Translation Address Table is implemented. | RW | 0

### PF_PCIE_BRIDGE : ATR7_AXI4_SLV0_SRC_ADDR

Address offset | 0x000 08E4
Physical address | 0x0300 48E4 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88E4 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_AXI4_SLV0_SRC_ADDR: AXI4 Slave 0 Address Translation Table 7 Source Address UDW.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SRC_ADDR_UDW | SRC_ADDR [63:32] defines the starting address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR7_AXI4_SLV0_TRSL_ADDR_LDW

Address offset | 0x000 08E8
Physical address | 0x0300 48E8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88E8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_AXI4_SLV0_TRSL_ADDR_LSB: AXI4 Slave 0 Address Translation Table 7 LSB [31:12] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | TRSL_ADDR_LDW | Defines the LSB[31:12] bits starting translated address of the address translation space. | RW | 0x0 0000
11:0 | reserved0 | Reserved | RW | 0x000

### PF_PCIE_BRIDGE : ATR7_AXI4_SLV0_TRSL_ADDR_UDW

Address offset | 0x000 08EC
Physical address | 0x0300 48EC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88EC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_AXI4_SLV0: AXI4 Slave 0 Address Translation Table 7 MSB [63:22] of Starting Translated Address. Note: SRC_ADDR and TRSL_ADDR are aligned on the Address Translation Space Size. Therefore, SRC_ADDR [integer (ATR_SIZE):0] and TRSL_ADDR [integer(ATR_SIZE):0] are ignored
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TSLR_ADDR_UDW | Defines the MSB [63:32] bits starting translated address of the address translation space. | RW | 0x0000 0000

### PF_PCIE_BRIDGE : ATR7_AXI4_SLV0_TRSL_PARAM

Address offset | 0x000 08F0
Physical address | 0x0300 48F0 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88F0 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_AXI4_SLV0_TRSL_PARAM: AXI4 Slave 0 Address Translation Table 7 Translation parameters
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | reserved28 | Reserved | RW | 0x0
27:16 | TRSF_PARAM | TRSF_PARAM is 12 bits long and provides the Translated Parameter of the request. The Transfer Parameter field of a read or write request to an address that targets this address translation space will be converted to the TRSF_PARAMETER value | RW | 0x000
15:4 | reserved4 | Reserved | RW | 0x000
3:0 | TRSL_ID | TRSL_ID is 4 bits long and defines the Translated ID of the request. The Completer ID Field of a read or write request to an address that targets the specified translation space will be converted to a TRSL_ID value. | RW | 0x0
|  | 0x0 | [TRSL_ID_PCIE_RX_TX] PCIe Tx/Rx Interface |  |
|  | 0x1 | [TRSL_ID_PCIE_CONFIG] PCIe Config Interface |  |
|  | 0x2 | [TRSL_IS_AXI4L_M] AXI4-Lite Master Interface (External Registers) |  |
|  | 0x4 | [TRSL_ID_AX4_M0] AXI4 Master 0 Interface |  |
|  | 0x5 | [TRSL_ID_AX4_M1] AXI4 Master 1 Interface |  |
|  | 0x6 | [TRSL_ID_AX4_M2] AXI4 Master 2 Interface |  |
|  | 0x7 | [TRSL_ID_AX4_M3] AXI4 Master 3 Interface |  |
|  | 0x8 | [TRSL_ID_AX4_SI0] AXI4 Stream 0 Interface |  |
|  | 0x9 | [TRSL_ID_AX4_SI1] AXI4 Stream 1 Interface |  |
|  | 0xA | [TRSL_ID_AX4_SI2] AXI4 Stream 2 Interface |  |
|  | 0xB | [TRSL_ID_AX4_SI3] AXI4 Stream 3 Interface |  |
|  | 0xC | [TRSL_ID_BRIDGE_IR] Bridge Internal Registers |  |

### PF_PCIE_BRIDGE : ATR7_AXI4_SLV0_TRSL_MASK_DW0

Address offset | 0x000 08F8
Physical address | 0x0300 48F8 | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88F8 |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 7 TRSL_MASK defines the translation table mask address(bits[31:0])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW0 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

### PF_PCIE_BRIDGE : ATR7_AXI4_SLV0_TRSL_MASK_DW1

Address offset | 0x000 08FC
Physical address | 0x0300 48FC | Instance | pcie_top_0_PF_PCIE_BRIDGE
| 0x0300 88FC |  | pcie_top_1_PF_PCIE_BRIDGE
Description | ATR7_AXI4_SLV0_TRSL_MASK: AXI4 Slave 0 Address Translation Table 7 TRSL_MASK defines the translation table mask address(bits[63:32])
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TRSL_MASK_DW1 | It is equal to (0 - Table Size), where the table size is equal to 2^(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to (0 - 256KBytes) = 64?hFFFFFFFFFFFC0000. | RO | 0x0000 0000

PF_PCIE_BRIDGE has no common memories.