## IOSCB_ANALOGBLOCK2

This section provides information on the IOSCB_ANALOGBLOCK2 Module Instance. Each of the module registers is described below.

Return to mpfs_ioscb_memmap_dri

## IOSCB_ANALOGBLOCK2 Register Mapping Summary

### IOSCB_ANALOGBLOCK2 Common Register Mapping Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000
USR_GDET | RW | 32 | 0x0000 0000 | 0x004
USR_GDET2 | RW | 32 | 0x001F FE00 | 0x008
SPARE_REG | RW | 32 | 0x0000 0000 | 0x00C

## IOSCB_ANALOGBLOCK2 Instances Mapping Summary

### IOSCB_ANALOGBLOCK2 : corner_se_spares Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0D01 0000
USR_GDET | RW | 32 | 0x0000 0000 | 0x004 | 0x0D01 0004
USR_GDET2 | RW | 32 | 0x001F FE00 | 0x008 | 0x0D01 0008
SPARE_REG | RW | 32 | 0x0000 0000 | 0x00C | 0x0D01 000C

### IOSCB_ANALOGBLOCK2 : corner_ne_spares Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0D04 0000
USR_GDET | RW | 32 | 0x0000 0000 | 0x004 | 0x0D04 0004
USR_GDET2 | RW | 32 | 0x001F FE00 | 0x008 | 0x0D04 0008
SPARE_REG | RW | 32 | 0x0000 0000 | 0x00C | 0x0D04 000C

### IOSCB_ANALOGBLOCK2 : corner_nw_spares Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0D10 0000
USR_GDET | RW | 32 | 0x0000 0000 | 0x004 | 0x0D10 0004
USR_GDET2 | RW | 32 | 0x001F FE00 | 0x008 | 0x0D10 0008
SPARE_REG | RW | 32 | 0x0000 0000 | 0x00C | 0x0D10 000C

### IOSCB_ANALOGBLOCK2 : corner_sw_analog_spares Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0D40 0000
USR_GDET | RW | 32 | 0x0000 0000 | 0x004 | 0x0D40 0004
USR_GDET2 | RW | 32 | 0x001F FE00 | 0x008 | 0x0D40 0008
SPARE_REG | RW | 32 | 0x0000 0000 | 0x00C | 0x0D40 000C

## IOSCB_ANALOGBLOCK2 Register Descriptions

### IOSCB_ANALOGBLOCK2 : SOFT_RESET

Address offset | 0x000
Physical address | 0x0D01 0000 | Instance | corner_se_spares
| 0x0D04 0000 |  | corner_ne_spares
| 0x0D10 0000 |  | corner_nw_spares
| 0x0D40 0000 |  | corner_sw_analog_spares
Description | This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | BLOCKID | This returns the block type and chip location. (IO SCB bus only) | RO | 0x0000
|  | Read 0x0000 | [block_address_IOSCB_ANALOGBLOCK2] |  |
15:9 | Reserved |  | RO Rreturns0s | 0x00
8 | PERIPH | This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0. | WO | 0
|  | Write 0 | [scb_periph_not_in_soft_reset_IOSCB_ANALOGBLOCK2] |  |
|  | Write 1 | [scb_periph_reset_IOSCB_ANALOGBLOCK2] |  |
7:2 | Reserved |  | RO Rreturns0s | 0x00
1 | V_MAP | This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit | WO | 0
|  | Write 0 | [scb_v_regs_not_in_soft_reset_IOSCB_ANALOGBLOCK2] |  |
|  | Write 1 | [scb_v_regs_reset_IOSCB_ANALOGBLOCK2] |  |
0 | NV_MAP | This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit | WO | 0
|  | Write 0 | [scb_nv_regs_not_in_soft_reset_IOSCB_ANALOGBLOCK2] |  |
|  | Write 1 | [scb_nv_regs_reset_IOSCB_ANALOGBLOCK2] |  |

### IOSCB_ANALOGBLOCK2 : USR_GDET

Address offset | 0x004
Physical address | 0x0D01 0004 | Instance | corner_se_spares
| 0x0D04 0004 |  | corner_ne_spares
| 0x0D10 0004 |  | corner_nw_spares
| 0x0D40 0004 |  | corner_sw_analog_spares
Description | Glitch Detector Regiseter
Type | RW

Bits | Field Name | Description | Type | Reset
31:27 | Reserved |  | RO | 0x00
26 | sro_usr_gdet2p5_rdy |  | RO | 0
25 | sro_usr_gdet2p5_outl |  | RO | 0
24 | sro_usr_gdet2p5_outh |  | RO | 0
23:22 | usr_gdet2p5_threshold |  | RW | 0x0
21:20 | usr_gdet2p5_rate |  | RW | 0x0
19:18 | usr_gdet2p5_width |  | RW | 0x0
17 | sro_usr_gdet1p8_rdy |  | RO | 0
16 | sro_usr_gdet1p8_outl |  | RO | 0
15 | sro_usr_gdet1p8_outh |  | RO | 0
14:13 | usr_gdet1p8_threshold |  | RW | 0x0
12:11 | usr_gdet1p8_rate |  | RW | 0x0
10:9 | usr_gdet1p8_width |  | RW | 0x0
8 | sro_usr_gdet1p05_rdy |  | RO | 0
7 | sro_usr_gdet1p05_outl |  | RO | 0
6 | sro_usr_gdet1p05_outh |  | RO | 0
5:4 | usr_gdet1p05_threshold |  | RW | 0x0
3:2 | usr_gdet1p05_rate |  | RW | 0x0
1:0 | usr_gdet1p05_width |  | RW | 0x0

### IOSCB_ANALOGBLOCK2 : USR_GDET2

Address offset | 0x008
Physical address | 0x0D01 0008 | Instance | corner_se_spares
| 0x0D04 0008 |  | corner_ne_spares
| 0x0D10 0008 |  | corner_nw_spares
| 0x0D40 0008 |  | corner_sw_analog_spares
Description | Glitch Detector Regiseter 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:21 | Reserved |  | RO Rreturns0s | 0x000
20:19 | usr_gdet2p5_negtrim |  | RW | 0x3
18:17 | usr_gdet2p5_postrim |  | RW | 0x3
16:15 | usr_gdet1p8_negtrim |  | RW | 0x3
14:13 | usr_gdet1p8_postrim |  | RW | 0x3
12:11 | usr_gdet1p05_negtrim |  | RW | 0x3
10:9 | usr_gdet1p05_postrim |  | RW | 0x3
8 | usr_gdet_dac_enable |  | RW | 0
7 | usr_gtestdac_measure |  | RW | 0
6:4 | usr_gdet_testdac |  | RW | 0x0
3 | usr_gdet_testdac_scale |  | RW | 0
2 | usr_gdet2p5_testmode |  | RW | 0
1 | usr_gdet1p8_testmode |  | RW | 0
0 | usr_gdet1p05_testmode |  | RW | 0

### IOSCB_ANALOGBLOCK2 : SPARE_REG

Address offset | 0x00C
Physical address | 0x0D01 000C | Instance | corner_se_spares
| 0x0D04 000C |  | corner_ne_spares
| 0x0D10 000C |  | corner_nw_spares
| 0x0D40 000C |  | corner_sw_analog_spares
Description | Spare registers
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | scb_spare_ro | spare ro bits | RO | 0x0000
15:0 | scb_spare_rw | spare rw bits | RW | 0x0000

IOSCB_ANALOGBLOCK2 has no common memories.