## AXISWITCH15X9_DW_AXI

This section provides information on the AXISWITCH15X9_DW_AXI Module Instance. Each of the module registers is described below.

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## AXISWITCH15X9_DW_AXI Register Mapping Summary

### AXISW Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
AXI_VERSION_ID_REG | RO | 32 | 0x3430 322A | 0x000 | 0x2000 4000
AXI_HW_CFG_REG | RO | 32 | 0x0090 F105 | 0x004 | 0x2000 4004
AXI_CMD_REG | RW | 32 | 0x0000 0000 | 0x008 | 0x2000 4008
AXI_DATA_REG | RW | 32 | 0x0000 0000 | 0x00C | 0x2000 400C

## AXISWITCH15X9_DW_AXI Register Descriptions

### AXISWITCH15X9_DW_AXI : AXI_VERSION_ID_REG

Address offset | 0x000
Physical address | 0x2000 4000 | Instance | AXISW
Description | Version ID register
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | AXI_VERID_FIELDS | DW_AXI Version ID Number. ASCII value of each number in component version followed by *. For example, 33_30_30_2A represents the version 3.00*. | RO | 0x3430 322A

### AXISWITCH15X9_DW_AXI : AXI_HW_CFG_REG

Address offset | 0x004
Physical address | 0x2000 4004 | Instance | AXISW
Description | Hardware configuration register
Type | RO

Bits | Field Name | Description | Type | Reset
31:25 | Reserved |  | RO Rreturns0s | 0x00
24:20 | AXI_NUM_SLAVES | Number of AXI Slaves. | RO | 0x09
19:17 | Reserved |  | RO Rreturns0s | 0x0
16:12 | AXI_NUM_MASTERS | Number of AXI masters | RO | 0x0F
11:9 | Reserved |  | RO Rreturns0s | 0x0
8 | AXI_LOW_POWER_IF | Include/exclude low-power interface. 0x1 (REMAP_SUPPORTED): DW_axi- Low-power interface is included. 0x0 (REMAP_NOT_SUPPORTED): DW_axi- Low-power interface is not included. | RO | 1
7 | AXI_BI_DIR_CMD_EN | Support for Enable Bi-directional Command.0x1 (REMAP_SUPPORTED): DW_axi supports the bi-directional command. 0x0 (REMAP_NOT_SUPPORTED): DW_axi does not support the bi-directional command | RO | 0
6 | AXI_REMAP_EN | Support for Enable Remap mode.0x1 (REMAP_SUPPORTED): DW_axi supports Enable Remap mode. 0x0 (REMAP_NOT_SUPPORTED): DW_axi does not support Enable Remap mode | RO | 0
5 | AXI_DECODER_TYPE | Use of External/Internal Decoder.0x1 (EXT_DECODER): DW_axi uses external decoder. 0x0 (INT_DECODER): DW_axi does not use the external decoder | RO | 0
4 | AXI_HWCFG_TRUST_ZONE_EN | Support for Enable Trust Zone. 0x1 (TZEN_SUPPORTED): DW_axi-Trust Zone features are Enabled. 0x0 (TZEN_NOT_SUPPORTED): DW_axi-Trust Zone features are Disabled. | RO | 0
3 | AXI_HWCFG_LOCK_EN | Support for Enable Lock transactions. 0x1 (LOCKEN_SUPPORTED): DW_axi-Locking feature is Enabled. 0x0 (LOCKEN_NOT_SUPPORTED): DW_axi-Locking feature is Disabled | RO | 0
2 | AXI_HWCFG_AXI4_SUPPORT | Support for AXI4 features. 0x1 (AXI4_SUPPORTED): DW_axi supports AXI4 features. 0x0 (AXI4_NOT_SUPPORTED): DW_axi does not support AXI4 features. | RO | 1
1 | AXI_HWCFG_APB3_SUPPORT | Has APB3 support. 0x1 (APB3_SUPPORTED): DW_axi has APB3 support. 0x0 (APB3_NOT_SUPPORTED): DW_axi does not have APB3 support. | RO | 0
0 | AXI_HWCFG_QOS_SUPPORT | QOS Support. 0x1 (QOS_ENABLED): DW_axi QOS support is enabled. 0x0 (QOS_DISABLED): DW_axi QOS support is disabled | RO | 1

### AXISWITCH15X9_DW_AXI : AXI_CMD_REG

Address offset | 0x008
Physical address | 0x2000 4008 | Instance | AXISW
Description | command register
Type | RW

Bits | Field Name | Description | Type | Reset
31 | AXI_CMD_EN | 1: The command in the register is valid and it is not yet completed by the interconnect. The command and data registers are locked for any updates till this bit is reset to 0. Any write to this bit by APB master when it is already set to 1 will be ignored without any error. 0: The command register is ready to accept new commands. The data register holds the data of the last successful transaction depending on whether it was for a read or write | RW | 0
30 | AXI_RD_WR_CMD | 0: Read command. 1: Write command | RW | 0
29 | AXI_SOFT_RESET_BIT | Internal Register reset. When this bit is set to 1 by the APB master, it resets all registers in the interconnect to their reset values. It is valid when command enable is set to 1 by the APB master. If this bit is 1 along with the command enable bit then it will execute Internal Registers Reset command irrespective of other bits value. | RW | 0
28 | AXI_ERR_BIT | Error Bit. This bit is a read-only bit as it is set to 1 only by the interconnect in case of error scenarios. It is valid only once command enable is reset to 0 by the interconnect. It will be cleared to 0 on next write to the command register by APB master. | RO | 0
27:12 | Reserved |  | RO Rreturns0s | 0x0000
11:8 | AXI_MASTER_PORT | Master Port ID. Identifies the master port for which command (bit[2:0]) is configured. | RW | 0x0
7 | AXI_RD_WR_CHAN | Read Address Channel /Write Address Channel. Identifies that the command is for read address channel or write address channel of the master port (bit[11:8]). 0: the command is for read address channel. 1: the command is for write address channel. It is valid when command enable bit is set to 1 by the APB master | RW | 0
6:3 | Reserved |  | RO Rreturns0s | 0x0
2:0 | AXI_CMD | 3'b000: BURSTINESS_REGULATOR_EN , 3'b001: PEAK_RATE_XCT_RATE , 3'b010: QOS_VALUE , 3'b011: SLV_READY | RW | 0x0

### AXISWITCH15X9_DW_AXI : AXI_DATA_REG

Address offset | 0x00C
Physical address | 0x2000 400C | Instance | AXISW
Description | Data register
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | AXI_DATA | Data to be written into the QoS internal register or the data read from the QoS internal register | RW RW | 0x0000 0000

AXISWITCH15X9_DW_AXI has no common memories.