## PCSLANE

This section provides information on the PCSLANE Module Instance. Each of the module registers is described below.

Register Lock Bits can prevent the XCVR configuration registers from being overwritten by hosts that have access to these registers. The lock bits can be managed using the Configure Register Lock Bits utility in the Libero SoC. The following registers can be locked.

· PCIESS_PCS_LN0_L8_R0

· PCIESS_PCS_LN0_LCLK_R0

· PCIESS_PCS_LN0_LCLK_R1

· PCIESS_PCS_LN0_LFWF_R0

· PCIESS_PCS_LN0_LNTV_R0

· PCIESS_PCS_LN0_LOVR_R0

· PCIESS_PCS_LN0_LPIP_R0

· PCIESS_PCS_LN0_PMA_CTRL_R0

Return to mpfs_ioscb_memmap_dri

## PCSLANE Register Mapping Summary

### PCSLANE Common Register Mapping Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094

## PCSLANE Instances Mapping Summary

### PCSLANE : serdes_0_pcs_lane0 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0004 1000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0004 1004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0004 1008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0004 100C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0004 1010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0004 1014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0004 1018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0004 101C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0004 1020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0004 1024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0004 1028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0004 102C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0004 1030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0004 1034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0004 1038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0004 1040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0004 1050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0004 1058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0004 105C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0004 1068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0004 106C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0004 1078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0004 107C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0004 1080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0004 1084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0004 1088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0004 108C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0004 1090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0004 1094

### PCSLANE : serdes_0_pcs_lane1 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0004 2000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0004 2004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0004 2008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0004 200C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0004 2010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0004 2014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0004 2018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0004 201C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0004 2020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0004 2024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0004 2028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0004 202C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0004 2030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0004 2034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0004 2038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0004 2040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0004 2050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0004 2058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0004 205C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0004 2068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0004 206C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0004 2078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0004 207C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0004 2080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0004 2084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0004 2088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0004 208C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0004 2090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0004 2094

### PCSLANE : serdes_0_pcs_lane2 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0004 4000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0004 4004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0004 4008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0004 400C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0004 4010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0004 4014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0004 4018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0004 401C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0004 4020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0004 4024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0004 4028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0004 402C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0004 4030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0004 4034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0004 4038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0004 4040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0004 4050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0004 4058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0004 405C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0004 4068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0004 406C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0004 4078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0004 407C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0004 4080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0004 4084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0004 4088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0004 408C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0004 4090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0004 4094

### PCSLANE : serdes_0_pcs_lane3 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0004 8000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0004 8004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0004 8008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0004 800C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0004 8010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0004 8014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0004 8018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0004 801C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0004 8020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0004 8024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0004 8028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0004 802C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0004 8030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0004 8034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0004 8038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0004 8040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0004 8050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0004 8058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0004 805C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0004 8068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0004 806C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0004 8078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0004 807C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0004 8080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0004 8084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0004 8088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0004 808C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0004 8090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0004 8094

### PCSLANE : serdes_1_pcs_lane0 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0008 1000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0008 1004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0008 1008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0008 100C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0008 1010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0008 1014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0008 1018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0008 101C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0008 1020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0008 1024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0008 1028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0008 102C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0008 1030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0008 1034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0008 1038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0008 1040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0008 1050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0008 1058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0008 105C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0008 1068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0008 106C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0008 1078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0008 107C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0008 1080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0008 1084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0008 1088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0008 108C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0008 1090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0008 1094

### PCSLANE : serdes_1_pcs_lane1 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0008 2000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0008 2004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0008 2008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0008 200C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0008 2010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0008 2014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0008 2018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0008 201C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0008 2020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0008 2024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0008 2028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0008 202C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0008 2030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0008 2034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0008 2038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0008 2040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0008 2050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0008 2058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0008 205C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0008 2068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0008 206C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0008 2078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0008 207C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0008 2080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0008 2084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0008 2088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0008 208C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0008 2090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0008 2094

### PCSLANE : serdes_1_pcs_lane2 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0008 4000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0008 4004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0008 4008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0008 400C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0008 4010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0008 4014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0008 4018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0008 401C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0008 4020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0008 4024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0008 4028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0008 402C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0008 4030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0008 4034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0008 4038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0008 4040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0008 4050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0008 4058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0008 405C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0008 4068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0008 406C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0008 4078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0008 407C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0008 4080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0008 4084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0008 4088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0008 408C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0008 4090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0008 4094

### PCSLANE : serdes_1_pcs_lane3 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0008 8000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0008 8004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0008 8008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0008 800C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0008 8010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0008 8014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0008 8018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0008 801C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0008 8020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0008 8024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0008 8028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0008 802C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0008 8030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0008 8034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0008 8038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0008 8040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0008 8050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0008 8058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0008 805C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0008 8068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0008 806C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0008 8078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0008 807C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0008 8080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0008 8084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0008 8088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0008 808C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0008 8090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0008 8094

### PCSLANE : serdes_2_pcs_lane0 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0010 1000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0010 1004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0010 1008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0010 100C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0010 1010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0010 1014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0010 1018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0010 101C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0010 1020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0010 1024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0010 1028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0010 102C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0010 1030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0010 1034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0010 1038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0010 1040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0010 1050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0010 1058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0010 105C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0010 1068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0010 106C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0010 1078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0010 107C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0010 1080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0010 1084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0010 1088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0010 108C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0010 1090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0010 1094

### PCSLANE : serdes_2_pcs_lane1 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0010 2000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0010 2004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0010 2008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0010 200C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0010 2010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0010 2014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0010 2018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0010 201C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0010 2020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0010 2024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0010 2028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0010 202C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0010 2030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0010 2034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0010 2038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0010 2040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0010 2050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0010 2058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0010 205C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0010 2068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0010 206C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0010 2078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0010 207C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0010 2080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0010 2084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0010 2088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0010 208C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0010 2090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0010 2094

### PCSLANE : serdes_2_pcs_lane2 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0010 4000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0010 4004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0010 4008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0010 400C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0010 4010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0010 4014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0010 4018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0010 401C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0010 4020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0010 4024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0010 4028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0010 402C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0010 4030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0010 4034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0010 4038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0010 4040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0010 4050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0010 4058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0010 405C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0010 4068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0010 406C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0010 4078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0010 407C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0010 4080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0010 4084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0010 4088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0010 408C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0010 4090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0010 4094

### PCSLANE : serdes_2_pcs_lane3 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0010 8000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0010 8004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0010 8008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0010 800C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0010 8010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0010 8014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0010 8018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0010 801C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0010 8020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0010 8024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0010 8028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0010 802C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0010 8030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0010 8034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0010 8038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0010 8040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0010 8050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0010 8058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0010 805C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0010 8068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0010 806C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0010 8078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0010 807C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0010 8080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0010 8084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0010 8088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0010 808C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0010 8090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0010 8094

### PCSLANE : serdes_3_pcs_lane0 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0020 1000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0020 1004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0020 1008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0020 100C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0020 1010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0020 1014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0020 1018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0020 101C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0020 1020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0020 1024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0020 1028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0020 102C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0020 1030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0020 1034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0020 1038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0020 1040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0020 1050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0020 1058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0020 105C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0020 1068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0020 106C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0020 1078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0020 107C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0020 1080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0020 1084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0020 1088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0020 108C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0020 1090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0020 1094

### PCSLANE : serdes_3_pcs_lane1 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0020 2000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0020 2004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0020 2008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0020 200C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0020 2010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0020 2014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0020 2018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0020 201C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0020 2020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0020 2024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0020 2028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0020 202C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0020 2030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0020 2034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0020 2038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0020 2040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0020 2050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0020 2058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0020 205C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0020 2068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0020 206C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0020 2078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0020 207C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0020 2080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0020 2084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0020 2088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0020 208C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0020 2090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0020 2094

### PCSLANE : serdes_3_pcs_lane2 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0020 4000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0020 4004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0020 4008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0020 400C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0020 4010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0020 4014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0020 4018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0020 401C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0020 4020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0020 4024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0020 4028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0020 402C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0020 4030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0020 4034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0020 4038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0020 4040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0020 4050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0020 4058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0020 405C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0020 4068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0020 406C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0020 4078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0020 407C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0020 4080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0020 4084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0020 4088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0020 408C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0020 4090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0020 4094

### PCSLANE : serdes_3_pcs_lane3 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0020 8000
LFWF_R0 | RW | 32 | 0x0000 0000 | 0x004 | 0x0020 8004
LOVR_R0 | RW | 32 | 0x0000 0010 | 0x008 | 0x0020 8008
LPIP_R0 | RW | 32 | 0x0000 005D | 0x00C | 0x0020 800C
L64_R0 | RW | 32 | 0x0140 0000 | 0x010 | 0x0020 8010
L64_R1 | RW | 32 | 0x0000 0001 | 0x014 | 0x0020 8014
L64_R2 | RW | 32 | 0x0000 0000 | 0x018 | 0x0020 8018
L64_R3 | RW | 32 | 0x0000 0000 | 0x01C | 0x0020 801C
L64_R4 | RW | 32 | 0x0000 0000 | 0x020 | 0x0020 8020
L64_R5 | RW | 32 | 0x0000 0000 | 0x024 | 0x0020 8024
L64_R6 | RW | 32 | 0x0000 0000 | 0x028 | 0x0020 8028
L64_R7 | RW | 32 | 0x0000 0000 | 0x02C | 0x0020 802C
L64_R8 | RO | 32 | 0x0000 0000 | 0x030 | 0x0020 8030
L64_R9 | RO | 32 | 0x0000 0000 | 0x034 | 0x0020 8034
L64_R10 | RO | 32 | 0x0000 0000 | 0x038 | 0x0020 8038
L8_R0 | RW | 32 | 0x0000 0000 | 0x040 | 0x0020 8040
LNTV_R0 | RW | 32 | 0x0000 0E0E | 0x050 | 0x0020 8050
LCLK_R0 | RW | 32 | 0x0000 0000 | 0x058 | 0x0020 8058
LCLK_R1 | RW | 32 | 0x0300 0000 | 0x05C | 0x0020 805C
LRST_R0 | RW | 32 | 0x0000 0004 | 0x068 | 0x0020 8068
LRST_OPT | RW | 32 | 0x0000 0000 | 0x06C | 0x0020 806C
OOB_R0 | RW | 32 | 0x110F 110F | 0x078 | 0x0020 8078
OOB_R1 | RW | 32 | 0x9888 332D | 0x07C | 0x0020 807C
OOB_R2 | RW | 32 | 0x0000 0000 | 0x080 | 0x0020 8080
OOB_R3 | RW | 32 | 0x0000 0000 | 0x084 | 0x0020 8084
PMA_CTRL_R0 | RW | 32 | 0x0303 0347 | 0x088 | 0x0020 8088
PMA_CTRL_R1 | RW | 32 | 0x000A 0640 | 0x08C | 0x0020 808C
PMA_CTRL_R2 | RW | 32 | 0x0000 00A6 | 0x090 | 0x0020 8090
MSTR_CTRL | RW | 32 | 0x0000 0000 | 0x094 | 0x0020 8094

## PCSLANE Register Descriptions

### PCSLANE : SOFT_RESET

Address offset | 0x000
Physical address | 0x0004 1000 | Instance | serdes_0_pcs_lane0
| 0x0004 4000 |  | serdes_0_pcs_lane2
| 0x0008 2000 |  | serdes_1_pcs_lane1
| 0x0010 4000 |  | serdes_2_pcs_lane2
| 0x0020 4000 |  | serdes_3_pcs_lane2
| 0x0010 8000 |  | serdes_2_pcs_lane3
| 0x0008 8000 |  | serdes_1_pcs_lane3
| 0x0004 2000 |  | serdes_0_pcs_lane1
| 0x0004 8000 |  | serdes_0_pcs_lane3
| 0x0008 1000 |  | serdes_1_pcs_lane0
| 0x0010 2000 |  | serdes_2_pcs_lane1
| 0x0020 8000 |  | serdes_3_pcs_lane3
| 0x0010 1000 |  | serdes_2_pcs_lane0
| 0x0020 2000 |  | serdes_3_pcs_lane1
| 0x0020 1000 |  | serdes_3_pcs_lane0
| 0x0008 4000 |  | serdes_1_pcs_lane2
Description | Compulsory register for all SCB slaves, facilitating global soft reset.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | BLOCKID | This returns the block type and chip location. The value of BLOCKID depends on the block type and instance of Serial block containing this page and upon the page (lane) instance number as follows: {4'h0, SLVTYPE, CHIPID, SUBID}. The SLVTPE value is 4'h0 for PCS. The CHIPID is determined by integration via constant applied to tieoff_chipid[3:0] . The SUBID is the identity of the lane instance copy of this register page (lane 0 has SUBID=0, lane 1 has SUBID=1, lane 2, lane 3 has SUBID=3). | RO | 0x0000
|  | Read 0x0000 | [block_address_PCSLANE] Indicates the Block chip location. |  |
15:9 | Reserved |  | RO Rreturns0s | 0x00
8 | PERIPH | This asserts functional reset of the peripheral block. It is asserted and left asserted at power-up. | WO | 0
|  | Write 0 | [scb_periph_not_in_soft_reset_PCSLANE] Reset not asserted. |  |
|  | Write 1 | [scb_periph_reset_PCSLANE] SCB registers reset pulsed. |  |
7:2 | Reserved |  | RO Rreturns0s | 0x00
1 | V_MAP | Resets all the volatile register bits. | WO | 0
|  | Write 0 | [scb_v_regs_not_in_soft_reset_PCSLANE] Reset not asserted. |  |
|  | Write 1 | [scb_v_regs_reset_PCSLANE] SCB Volatile reset (i.e. RW-X registers are reset) |  |
0 | NV_MAP | Resets all the non-volatile register bits (e.g. RW-P bits). | WO | 0
|  | Write 0 | [scb_nv_regs_not_in_soft_reset_PCSLANE] Reset not asserted. |  |
|  | Write 1 | [scb_nv_regs_reset_PCSLANE] SCB Non-Volatile reset (i.e. RW-P registers are reset. |  |

### PCSLANE : LFWF_R0

Address offset | 0x004
Physical address | 0x0004 1004 | Instance | serdes_0_pcs_lane0
| 0x0004 4004 |  | serdes_0_pcs_lane2
| 0x0008 2004 |  | serdes_1_pcs_lane1
| 0x0010 4004 |  | serdes_2_pcs_lane2
| 0x0020 4004 |  | serdes_3_pcs_lane2
| 0x0010 8004 |  | serdes_2_pcs_lane3
| 0x0008 8004 |  | serdes_1_pcs_lane3
| 0x0004 2004 |  | serdes_0_pcs_lane1
| 0x0004 8004 |  | serdes_0_pcs_lane3
| 0x0008 1004 |  | serdes_1_pcs_lane0
| 0x0010 2004 |  | serdes_2_pcs_lane1
| 0x0020 8004 |  | serdes_3_pcs_lane3
| 0x0010 1004 |  | serdes_2_pcs_lane0
| 0x0020 2004 |  | serdes_3_pcs_lane1
| 0x0020 1004 |  | serdes_3_pcs_lane0
| 0x0008 4004 |  | serdes_1_pcs_lane2
Description | Fly-wheel FIFO configuration and status.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7 | TXFWF_ERROR | Diagnostic boolean about TxFWF status. If this is set, the Tx FWF clocks are configured incorrectly or these clocks may have stopped or changed frequency. A reset of the Tx FWF is indicated when this error is flagged. | RO | 0
|  | Read 0 | [txfwf_error_false] |  |
|  | Read 1 | [txfwf_error_true] |  |
6:5 | TXFWF_RATIO | Ratio of write clock frequency to read clock frequency for the Tx FWF. Anything but 1:1 implies the fabric is using synchronous enable with a faster clock so that the fabric can operate with a narrower data path. | RW | 0x0
|  | 0x0 | [txfwf_equal_freq] The fabric clock is same frequency as PMA side of Rx FWF. |  |
|  | 0x1 | [txfwf_r_2x_w_freq] The fabric clock is twice the frequency of the PMA side of the Rx FWF. |  |
|  | 0x2 | [txfwf_r_4x_w_freq] The fabric clock is four times the frequency of the PMA side of the Rx FWF. |  |
|  | 0x3 | [txfwf_equal_freq_2] The fabric clock is the same frequency as the PMA side of the Rx FWF. |  |
4 | TXFWF_WMARK | This bit controls the approximate depth of buffering done by the Tx FWF. | RW | 0
|  | 0 | [fwf_depth_4] The initial depth of the FWF is 4 +/- 1. |  |
|  | 1 | [fwf_depth_3] The initial depth of the FWF is 3 +/- 1. |  |
3 | RXFWF_ERROR | Diagnostic boolean about RxFWF status. If this is set, the Rx FWF clocks are configured incorrectly or these clocks may have stopped or changed frequency. A reset of the Rx FWF is indicated when this error is flagged. | RO | 0
|  | Read 0 | [rxfwf_error_false] |  |
|  | Read 1 | [rxfwf_error_true] |  |
2:1 | RXFWF_RATIO | Ratio of read clock frequency to write clock frequency for the Rx FWF. Anything but 1:1 implies the fabric is using synchronous enable with a faster clock so that the fabric can operate with a narrower data path. | RW | 0x0
|  | 0x0 | [rxfwf_equal_freq] The fabric clock is same frequency as PMA side of Rx FWF. |  |
|  | 0x1 | [rxfwf_r_2x_w_freq] The fabric clock is twice the frequency of the PMA side of the Rx FWF. |  |
|  | 0x2 | [rxfwf_r_4x_w_freq] The fabric clock is four times the frequency of the PMA side of the Rx FWF. |  |
|  | 0x3 | [rxfwf_equal_freq_2] The fabric clock is the same frequency as the PMA side of the Rx FWF. |  |
0 | RXFWF_WMARK | This bit controls the approximate depth of buffering done by the Rx FWF. | RW | 0
|  | 0 | [fwf_depth_4] The initial depth of the FWF is 4 +/- 1. |  |
|  | 1 | [fwf_depth_3] The initial depth of the FWF is 3 +/- 1. |  |

### PCSLANE : LOVR_R0

Address offset | 0x008
Physical address | 0x0004 1008 | Instance | serdes_0_pcs_lane0
| 0x0004 4008 |  | serdes_0_pcs_lane2
| 0x0008 2008 |  | serdes_1_pcs_lane1
| 0x0010 4008 |  | serdes_2_pcs_lane2
| 0x0020 4008 |  | serdes_3_pcs_lane2
| 0x0010 8008 |  | serdes_2_pcs_lane3
| 0x0008 8008 |  | serdes_1_pcs_lane3
| 0x0004 2008 |  | serdes_0_pcs_lane1
| 0x0004 8008 |  | serdes_0_pcs_lane3
| 0x0008 1008 |  | serdes_1_pcs_lane0
| 0x0010 2008 |  | serdes_2_pcs_lane1
| 0x0020 8008 |  | serdes_3_pcs_lane3
| 0x0010 1008 |  | serdes_2_pcs_lane0
| 0x0020 2008 |  | serdes_3_pcs_lane1
| 0x0020 1008 |  | serdes_3_pcs_lane0
| 0x0008 4008 |  | serdes_1_pcs_lane2
Description | Lane Overlay
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:4 | PCSPMA_IFC_MODE | Lane overlay control for PMA interfaces. | RW | 0x1
|  | 0x0 | [lane_pma_interface_unused] The lane PMA interface is tied to any PCS function. |  |
|  | 0x1 | [lane_pma_interface_pipe_mode] The lane PMA interface is tied to the PIPE PCS logic. |  |
|  | 0x2 | [lane_pma_interface_646xb_mode] The lane PMA interface is tied to the 646xb PCS logic. |  |
|  | 0x4 | [lane_pma_interface_8b10b_mode] The lane PMA interface is tied to the native lane logic. |  |
|  | 0x8 | [lane_pma_interface_native_mode] The lane PMA pins are configured |  |
3:0 | FAB_IFC_MODE | Lane overlay control field for fabric interfaces. | RW | 0x0
|  | 0x0 | [lane_fabric_interface_unused] The lane fabric interface is not used because the lane is bound to a PCIe hard controller. |  |
|  | 0x1 | [lane_fabric_pipe_mode] The lane fabric pins are configured for PIPE mode. |  |
|  | 0x2 | [lane_fabric_64b6xb_mode] The lane fabric pins are configured for 64x6xb mode. |  |
|  | 0x4 | [lane_fabric_8b10b_mode] The lane fabric pins are configured for 8b10b mode. |  |
|  | 0x8 | [lane_fabric_native_mode] The lane fabric pins are configured for native mode. |  |

### PCSLANE : LPIP_R0

Address offset | 0x00C
Physical address | 0x0004 100C | Instance | serdes_0_pcs_lane0
| 0x0004 400C |  | serdes_0_pcs_lane2
| 0x0008 200C |  | serdes_1_pcs_lane1
| 0x0010 400C |  | serdes_2_pcs_lane2
| 0x0020 400C |  | serdes_3_pcs_lane2
| 0x0010 800C |  | serdes_2_pcs_lane3
| 0x0008 800C |  | serdes_1_pcs_lane3
| 0x0004 200C |  | serdes_0_pcs_lane1
| 0x0004 800C |  | serdes_0_pcs_lane3
| 0x0008 100C |  | serdes_1_pcs_lane0
| 0x0010 200C |  | serdes_2_pcs_lane1
| 0x0020 800C |  | serdes_3_pcs_lane3
| 0x0010 100C |  | serdes_2_pcs_lane0
| 0x0020 200C |  | serdes_3_pcs_lane1
| 0x0020 100C |  | serdes_3_pcs_lane0
| 0x0008 400C |  | serdes_1_pcs_lane2
Description | Configuration of PIPE lane logic.
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved |  | RO Rreturns0s | 0x000 0000
6:5 | PIPE_OOB_IDLEBURST_TIMING | Chooses how the the timing of bursts of data and electrical-idle for OOB signaling are controlled. | RW | 0x2
|  | 0x0 | [pipe_tx_idlbrst_pwrdn_mode] MAC controls timing using PIPE PowerDown |  |
|  | 0x1 | [pipe_tx_idlbrst_txelecidle_mode] MAC controls timing using PIPE TxElecIdle |  |
|  | 0x2 | [pipe_tx_idlbrst_internal_mode] PHY logic controls timing. |  |
4 | PIPE_INITIALIZATION_DONE | This configuration bit must be written to 1 after the rest of the configuration bits affecting PIPE logic operation are stable. | RW | 1
3 | PIPE_SHAREDPLL | This field indicates that this PIPE lane shares a Tx PLL source and this lane's logic should not power-down the PLL in P2 power-state. | RW | 1
|  | 0 | [pipe_lane_is_pll_master] PIPE lane Tx PLL source may be powered off by this lane's power-state logic. |  |
|  | 1 | [pipe_lane_pll_is_shared] PIPE lane Tx PLL source may not be powered off by this lane's power-state logic. |  |
2 | PIPE_PCIE_HC | PIPE lane logic source context switch. | RW | 1
|  | 0 | [pipe_mac_is_fabric] PIPE lane is mastered by a soft controller resident in the fabric. |  |
|  | 1 | [pipe_mac_is_hard_controller] PIPE lane is mastered by a hard controller. |  |
1 | PIPEMODE | Operational sub-mode of the PIPE lane logic. | RW | 0
|  | 0 | [pipe_is_pci_express] PIPE lane logic is performing PCI-Express function. |  |
|  | 1 | [pipe_is_sata] PIPE lane logic is performing SATA function. |  |
0 | PIPEENABLE | PIPE function enable | RW | 1
|  | 0 | [pipe_function_disabled] PIPE datapath and special PIPE functionality of PMA controller are disabled. |  |
|  | 1 | [pipe_function_enabled] PIPE datapath and special PIPE functionality of PMA controller are enabled. |  |

### PCSLANE : L64_R0

Address offset | 0x010
Physical address | 0x0004 1010 | Instance | serdes_0_pcs_lane0
| 0x0004 4010 |  | serdes_0_pcs_lane2
| 0x0008 2010 |  | serdes_1_pcs_lane1
| 0x0010 4010 |  | serdes_2_pcs_lane2
| 0x0020 4010 |  | serdes_3_pcs_lane2
| 0x0010 8010 |  | serdes_2_pcs_lane3
| 0x0008 8010 |  | serdes_1_pcs_lane3
| 0x0004 2010 |  | serdes_0_pcs_lane1
| 0x0004 8010 |  | serdes_0_pcs_lane3
| 0x0008 1010 |  | serdes_1_pcs_lane0
| 0x0010 2010 |  | serdes_2_pcs_lane1
| 0x0020 8010 |  | serdes_3_pcs_lane3
| 0x0010 1010 |  | serdes_2_pcs_lane0
| 0x0020 2010 |  | serdes_3_pcs_lane1
| 0x0020 1010 |  | serdes_3_pcs_lane0
| 0x0008 4010 |  | serdes_1_pcs_lane2
Description | Configuration of 64b6xb logic.
Type | RW

Bits | Field Name | Description | Type | Reset
31:27 | Reserved |  | RO Rreturns0s | 0x00
26:16 | L64_CFG_BER_1US_TIMER_VAL | IEEE Clause 49 BER Monitor 1us timer value | RW | 0x140
15:8 | Reserved |  | RO Rreturns0s | 0x00
7 | L64_CFG_GRBX_SM_C82 | IEEE Clause 82 state machine enable. | RW | 0
|  | 0 | [clause_82_sm_disable] Disable clause 82 state machine. |  |
|  | 1 | [clause_82_sm_enable] Enable clause-82 state machine. |  |
6 | L64_CFG_GRBX_SM_C49 | IEEE Clause 49 state machine enable. | RW | 0
|  | 0 | [clause_49_sm_disable] Disable clause 49 state machine. |  |
|  | 1 | [clause_49_sm_enable] Enable clause-49 state machine. |  |
5 | L64_CFG_BYPASS_8B_MODE | Selects width of 64b6xb fabric interface. | RW | 0
|  | 0 | [width_8_byte] Select eight-byte fabric interface width. |  |
|  | 1 | [width_4_byte] Select four-byte fabric interface width. |  |
4 | L64_CFG_BER_MON_EN | Enable for bit error monitor state machine. | RW | 0
|  | 0 | [ber_sm_disabled] Disable BER state machine. |  |
|  | 1 | [ber_sm_enabled] Enable BER state machine. |  |
3 | L64_CFG_GRBX_64B67B | Enable for 64b67b gearbox function. | RW | 0
|  | 0 | [gearbox_64b66b_mode] Configure gearbox function for 64b66b. |  |
|  | 1 | [gearbox_64b67b_mode] Configure gearbox function for 64b67b . |  |
2 | L64_CFG_BYPASS_GEARBOX | Enable for 64b6xb gearbox function. | RW | 0
|  | 0 | [gearbox_64b6xb_enabled] Enable 64b6xb gearbox function. |  |
|  | 1 | [gearbox_64b6xb_bypassed] Bypass 64b6xb gearbox function. |  |
1 | L64_CFG_BYPASS_DISPARITY | Enable disparity calculation for Interlaken. | RW | 0
|  | 0 | [disparity_calc_enabled] Enable 64b67b block disparity function. |  |
|  | 1 | [disparity_calc_bypassed] Bypass 64b67b block disparity function. |  |
0 | L64_CFG_BYPASS_SCRAMBLER | Enable for 64b66b scrambler function. | RW | 0
|  | 0 | [scrambler_64b66b_enabled] The 64b66b scrambler is enabled. |  |
|  | 1 | [scrambler_64b66b_bypassed] The 64b66b scrambler is bypassed. |  |

### PCSLANE : L64_R1

Address offset | 0x014
Physical address | 0x0004 1014 | Instance | serdes_0_pcs_lane0
| 0x0004 4014 |  | serdes_0_pcs_lane2
| 0x0008 2014 |  | serdes_1_pcs_lane1
| 0x0010 4014 |  | serdes_2_pcs_lane2
| 0x0020 4014 |  | serdes_3_pcs_lane2
| 0x0010 8014 |  | serdes_2_pcs_lane3
| 0x0008 8014 |  | serdes_1_pcs_lane3
| 0x0004 2014 |  | serdes_0_pcs_lane1
| 0x0004 8014 |  | serdes_0_pcs_lane3
| 0x0008 1014 |  | serdes_1_pcs_lane0
| 0x0010 2014 |  | serdes_2_pcs_lane1
| 0x0020 8014 |  | serdes_3_pcs_lane3
| 0x0010 1014 |  | serdes_2_pcs_lane0
| 0x0020 2014 |  | serdes_3_pcs_lane1
| 0x0020 1014 |  | serdes_3_pcs_lane0
| 0x0008 4014 |  | serdes_1_pcs_lane2
Description | Test functions of 64b6xb logic.
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | Reserved |  | RO Rreturns0s | 0x000 0000
4 | L64_CFG_TEST_PATT_DATA_SEL | Selects pattern when test_pattern_enabled. | RW | 0
|  | 0 | [local_faults_pattern] Local faults test pattern data. |  |
|  | 1 | [all_zeroes_pattern] All-zeroes test pattern data. |  |
3 | L64_CFG_TEST_PRBS31_EN | PRBS-31 test control | RW | 0
|  | 0 | [test_prbs_31_disabled] PRBS-31 test pattern disabled. |  |
|  | 1 | [test_prbs_31_enabled] PRBS-31 test pattern enabled. |  |
2 | L64_CFG_TEST_PATT_TYPE_SEL | Test pattern type selection. | RW | 0
|  | 0 | [test_pattern_square] Select square wave test pattern. |  |
|  | 1 | [test_pattern_prbs] Select PRBS test pattern. |  |
1 | L64_CFG_TEST_PATTERN_EN | Test pattern control. | RW | 0
|  | 0 | [test_pattern_disabled] Disable test pattern. |  |
|  | 1 | [test_pattern_enabled] Enable test pattern. |  |
0 | L64_BYPASS_TEST | Bypass test for 64b6xb logic. | RW | 1
|  | 0 | [test_64b6xb_enabled] Enable 64b6xb test mode. |  |
|  | 1 | [test_64b6xb_disabled] Disable 64b6xb test mode. |  |

### PCSLANE : L64_R2

Address offset | 0x018
Physical address | 0x0004 1018 | Instance | serdes_0_pcs_lane0
| 0x0004 4018 |  | serdes_0_pcs_lane2
| 0x0008 2018 |  | serdes_1_pcs_lane1
| 0x0010 4018 |  | serdes_2_pcs_lane2
| 0x0020 4018 |  | serdes_3_pcs_lane2
| 0x0010 8018 |  | serdes_2_pcs_lane3
| 0x0008 8018 |  | serdes_1_pcs_lane3
| 0x0004 2018 |  | serdes_0_pcs_lane1
| 0x0004 8018 |  | serdes_0_pcs_lane3
| 0x0008 1018 |  | serdes_1_pcs_lane0
| 0x0010 2018 |  | serdes_2_pcs_lane1
| 0x0020 8018 |  | serdes_3_pcs_lane3
| 0x0010 1018 |  | serdes_2_pcs_lane0
| 0x0020 2018 |  | serdes_3_pcs_lane1
| 0x0020 1018 |  | serdes_3_pcs_lane0
| 0x0008 4018 |  | serdes_1_pcs_lane2
Description | Seed A, part 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | L64_SEED_A_VALUE_LO32 | Lower 32 bits of 58-bit Seed A value. This is used when test_pattern_enabled and test_pattern_prbs are both set. | RW | 0x0000 0000

### PCSLANE : L64_R3

Address offset | 0x01C
Physical address | 0x0004 101C | Instance | serdes_0_pcs_lane0
| 0x0004 401C |  | serdes_0_pcs_lane2
| 0x0008 201C |  | serdes_1_pcs_lane1
| 0x0010 401C |  | serdes_2_pcs_lane2
| 0x0020 401C |  | serdes_3_pcs_lane2
| 0x0010 801C |  | serdes_2_pcs_lane3
| 0x0008 801C |  | serdes_1_pcs_lane3
| 0x0004 201C |  | serdes_0_pcs_lane1
| 0x0004 801C |  | serdes_0_pcs_lane3
| 0x0008 101C |  | serdes_1_pcs_lane0
| 0x0010 201C |  | serdes_2_pcs_lane1
| 0x0020 801C |  | serdes_3_pcs_lane3
| 0x0010 101C |  | serdes_2_pcs_lane0
| 0x0020 201C |  | serdes_3_pcs_lane1
| 0x0020 101C |  | serdes_3_pcs_lane0
| 0x0008 401C |  | serdes_1_pcs_lane2
Description | Seed A, part 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:26 | Reserved |  | RO Rreturns0s | 0x00
25:0 | L64_SEED_A_VALUE_HI26 | Upper 26 bits of 58-bit Seed A value. | RW | 0x000 0000

### PCSLANE : L64_R4

Address offset | 0x020
Physical address | 0x0004 1020 | Instance | serdes_0_pcs_lane0
| 0x0004 4020 |  | serdes_0_pcs_lane2
| 0x0008 2020 |  | serdes_1_pcs_lane1
| 0x0010 4020 |  | serdes_2_pcs_lane2
| 0x0020 4020 |  | serdes_3_pcs_lane2
| 0x0010 8020 |  | serdes_2_pcs_lane3
| 0x0008 8020 |  | serdes_1_pcs_lane3
| 0x0004 2020 |  | serdes_0_pcs_lane1
| 0x0004 8020 |  | serdes_0_pcs_lane3
| 0x0008 1020 |  | serdes_1_pcs_lane0
| 0x0010 2020 |  | serdes_2_pcs_lane1
| 0x0020 8020 |  | serdes_3_pcs_lane3
| 0x0010 1020 |  | serdes_2_pcs_lane0
| 0x0020 2020 |  | serdes_3_pcs_lane1
| 0x0020 1020 |  | serdes_3_pcs_lane0
| 0x0008 4020 |  | serdes_1_pcs_lane2
Description | Seed B, part 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | L64_SEED_B_VALUE_LO32 | Lower 32 bits of 58-bit Seed B value. This is used when test_pattern_enabled and test_pattern_prbs are both set. | RW | 0x0000 0000

### PCSLANE : L64_R5

Address offset | 0x024
Physical address | 0x0004 1024 | Instance | serdes_0_pcs_lane0
| 0x0004 4024 |  | serdes_0_pcs_lane2
| 0x0008 2024 |  | serdes_1_pcs_lane1
| 0x0010 4024 |  | serdes_2_pcs_lane2
| 0x0020 4024 |  | serdes_3_pcs_lane2
| 0x0010 8024 |  | serdes_2_pcs_lane3
| 0x0008 8024 |  | serdes_1_pcs_lane3
| 0x0004 2024 |  | serdes_0_pcs_lane1
| 0x0004 8024 |  | serdes_0_pcs_lane3
| 0x0008 1024 |  | serdes_1_pcs_lane0
| 0x0010 2024 |  | serdes_2_pcs_lane1
| 0x0020 8024 |  | serdes_3_pcs_lane3
| 0x0010 1024 |  | serdes_2_pcs_lane0
| 0x0020 2024 |  | serdes_3_pcs_lane1
| 0x0020 1024 |  | serdes_3_pcs_lane0
| 0x0008 4024 |  | serdes_1_pcs_lane2
Description | Seed B, part 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:26 | Reserved |  | RO Rreturns0s | 0x00
25:0 | L64_SEED_B_VALUE_HI26 | Upper 26 bits of 58-bit Seed B value. | RW | 0x000 0000

### PCSLANE : L64_R6

Address offset | 0x028
Physical address | 0x0004 1028 | Instance | serdes_0_pcs_lane0
| 0x0004 4028 |  | serdes_0_pcs_lane2
| 0x0008 2028 |  | serdes_1_pcs_lane1
| 0x0010 4028 |  | serdes_2_pcs_lane2
| 0x0020 4028 |  | serdes_3_pcs_lane2
| 0x0010 8028 |  | serdes_2_pcs_lane3
| 0x0008 8028 |  | serdes_1_pcs_lane3
| 0x0004 2028 |  | serdes_0_pcs_lane1
| 0x0004 8028 |  | serdes_0_pcs_lane3
| 0x0008 1028 |  | serdes_1_pcs_lane0
| 0x0010 2028 |  | serdes_2_pcs_lane1
| 0x0020 8028 |  | serdes_3_pcs_lane3
| 0x0010 1028 |  | serdes_2_pcs_lane0
| 0x0020 2028 |  | serdes_3_pcs_lane1
| 0x0020 1028 |  | serdes_3_pcs_lane0
| 0x0008 4028 |  | serdes_1_pcs_lane2
Description | CPRI transmit delay reporting configuration.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | L64_TX_ADD_UI | Additional UI for PMA Transmit.Used in CPRI applications only. | RW | 0x0000
15:5 | Reserved |  | RO Rreturns0s | 0x000
4:0 | L64_TX_ADV_CYC_DLY | Advance delay cycle value for transmit. Used in CPRI applications only. | RW | 0x00

### PCSLANE : L64_R7

Address offset | 0x02C
Physical address | 0x0004 102C | Instance | serdes_0_pcs_lane0
| 0x0004 402C |  | serdes_0_pcs_lane2
| 0x0008 202C |  | serdes_1_pcs_lane1
| 0x0010 402C |  | serdes_2_pcs_lane2
| 0x0020 402C |  | serdes_3_pcs_lane2
| 0x0010 802C |  | serdes_2_pcs_lane3
| 0x0008 802C |  | serdes_1_pcs_lane3
| 0x0004 202C |  | serdes_0_pcs_lane1
| 0x0004 802C |  | serdes_0_pcs_lane3
| 0x0008 102C |  | serdes_1_pcs_lane0
| 0x0010 202C |  | serdes_2_pcs_lane1
| 0x0020 802C |  | serdes_3_pcs_lane3
| 0x0010 102C |  | serdes_2_pcs_lane0
| 0x0020 202C |  | serdes_3_pcs_lane1
| 0x0020 102C |  | serdes_3_pcs_lane0
| 0x0008 402C |  | serdes_1_pcs_lane2
Description | CPRI receive delay reporting configuration.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | L64_RX_ADD_UI | Additional UI for PMA Receive.Used in CPRI applications only. | RW | 0x0000
15:5 | Reserved |  | RO Rreturns0s | 0x000
4:0 | L64_RX_ADV_CYC_DLY | Advance delay cycle value for receive. Used in CPRI applications only. | RW | 0x00

### PCSLANE : L64_R8

Address offset | 0x030
Physical address | 0x0004 1030 | Instance | serdes_0_pcs_lane0
| 0x0004 4030 |  | serdes_0_pcs_lane2
| 0x0008 2030 |  | serdes_1_pcs_lane1
| 0x0010 4030 |  | serdes_2_pcs_lane2
| 0x0020 4030 |  | serdes_3_pcs_lane2
| 0x0010 8030 |  | serdes_2_pcs_lane3
| 0x0008 8030 |  | serdes_1_pcs_lane3
| 0x0004 2030 |  | serdes_0_pcs_lane1
| 0x0004 8030 |  | serdes_0_pcs_lane3
| 0x0008 1030 |  | serdes_1_pcs_lane0
| 0x0010 2030 |  | serdes_2_pcs_lane1
| 0x0020 8030 |  | serdes_3_pcs_lane3
| 0x0010 1030 |  | serdes_2_pcs_lane0
| 0x0020 2030 |  | serdes_3_pcs_lane1
| 0x0020 1030 |  | serdes_3_pcs_lane0
| 0x0008 4030 |  | serdes_1_pcs_lane2
Description | Status for 64b6xb optional blocks.
Type | RO

Bits | Field Name | Description | Type | Reset
31:17 | Reserved |  | RO Rreturns0s | 0x0000
16 | L64_BER_COUNT_AVAIL | Boolean flag of L64_BER_COUNT validity. | RO | 0
15:8 | L64_BER_COUNT | Count of invalid block-sync headers. | RO | 0x00
7:4 | Reserved |  | RO Rreturns0s | 0x0
3 | L64_GRBX_RDY | Boolean for gearbox ready. | RO | 0
2 | L64_STATUS | Boolean for HI_BER=FALSE and LOCK=TRUE. (LOCK can only occur with HI_BER=FALSE; is this meaningful?) | RO | 0
1 | L64_LOCK | Boolean for block-alignment status. | RO | 0
0 | L64_HI_BER_STATUS | Boolean for bit error rate exceeds 1e-4. | RO | 0

### PCSLANE : L64_R9

Address offset | 0x034
Physical address | 0x0004 1034 | Instance | serdes_0_pcs_lane0
| 0x0004 4034 |  | serdes_0_pcs_lane2
| 0x0008 2034 |  | serdes_1_pcs_lane1
| 0x0010 4034 |  | serdes_2_pcs_lane2
| 0x0020 4034 |  | serdes_3_pcs_lane2
| 0x0010 8034 |  | serdes_2_pcs_lane3
| 0x0008 8034 |  | serdes_1_pcs_lane3
| 0x0004 2034 |  | serdes_0_pcs_lane1
| 0x0004 8034 |  | serdes_0_pcs_lane3
| 0x0008 1034 |  | serdes_1_pcs_lane0
| 0x0010 2034 |  | serdes_2_pcs_lane1
| 0x0020 8034 |  | serdes_3_pcs_lane3
| 0x0010 1034 |  | serdes_2_pcs_lane0
| 0x0020 2034 |  | serdes_3_pcs_lane1
| 0x0020 1034 |  | serdes_3_pcs_lane0
| 0x0008 4034 |  | serdes_1_pcs_lane2
Description | Status of 64b6xb test blocks.
Type | RO

Bits | Field Name | Description | Type | Reset
31:9 | Reserved |  | RO Rreturns0s | 0x00 0000
8 | L64_TEST_ERR_COUNT_AVAIL | Boolean flag of L64_TEST_ERR_COUNT validity. | RO | 0
7:0 | L64_TEST_ERR_COUNT | Test error count. | RO | 0x00

### PCSLANE : L64_R10

Address offset | 0x038
Physical address | 0x0004 1038 | Instance | serdes_0_pcs_lane0
| 0x0004 4038 |  | serdes_0_pcs_lane2
| 0x0008 2038 |  | serdes_1_pcs_lane1
| 0x0010 4038 |  | serdes_2_pcs_lane2
| 0x0020 4038 |  | serdes_3_pcs_lane2
| 0x0010 8038 |  | serdes_2_pcs_lane3
| 0x0008 8038 |  | serdes_1_pcs_lane3
| 0x0004 2038 |  | serdes_0_pcs_lane1
| 0x0004 8038 |  | serdes_0_pcs_lane3
| 0x0008 1038 |  | serdes_1_pcs_lane0
| 0x0010 2038 |  | serdes_2_pcs_lane1
| 0x0020 8038 |  | serdes_3_pcs_lane3
| 0x0010 1038 |  | serdes_2_pcs_lane0
| 0x0020 2038 |  | serdes_3_pcs_lane1
| 0x0020 1038 |  | serdes_3_pcs_lane0
| 0x0008 4038 |  | serdes_1_pcs_lane2
Description | Delay of Transmit and Receive Paths
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | L64_RX_DLY | Total UI delay of 64b66b receive datapath for CPRI 7A, 8 and 9. | RO | 0x0000
15:0 | L64_TX_DLY | Total UI delay of 64b66b transmit datapath for CPRI 7A, 8 and 9. | RO | 0x0000

### PCSLANE : L8_R0

Address offset | 0x040
Physical address | 0x0004 1040 | Instance | serdes_0_pcs_lane0
| 0x0004 4040 |  | serdes_0_pcs_lane2
| 0x0008 2040 |  | serdes_1_pcs_lane1
| 0x0010 4040 |  | serdes_2_pcs_lane2
| 0x0020 4040 |  | serdes_3_pcs_lane2
| 0x0010 8040 |  | serdes_2_pcs_lane3
| 0x0008 8040 |  | serdes_1_pcs_lane3
| 0x0004 2040 |  | serdes_0_pcs_lane1
| 0x0004 8040 |  | serdes_0_pcs_lane3
| 0x0008 1040 |  | serdes_1_pcs_lane0
| 0x0010 2040 |  | serdes_2_pcs_lane1
| 0x0020 8040 |  | serdes_3_pcs_lane3
| 0x0010 1040 |  | serdes_2_pcs_lane0
| 0x0020 2040 |  | serdes_3_pcs_lane1
| 0x0020 1040 |  | serdes_3_pcs_lane0
| 0x0008 4040 |  | serdes_1_pcs_lane2
Description | Control for 8b10b blocks.
Type | RW

Bits | Field Name | Description | Type | Reset
31:18 | Reserved |  | RO Rreturns0s | 0x0000
17:16 | L8_GEARMODE | Sets gearing of Tx and Rx data of fabric relative to PMA. 0 := fabric width = PMA width, 4-octets 1 := fabric width = 2-octets, PMA = 4-octets 2 := fabric width = 8-octets, PMA = 4-octets | RW | 0x0
|  | 0x0 | [8b10b_fabric_width_4_octets] |  |
|  | 0x1 | [8b10b_fabric_width_2_octets] |  |
|  | 0x2 | [8b10b_fabric_width_8_octets] |  |
15:1 | Reserved |  | RO Rreturns0s | 0x0000
0 | L8_TXENCSWAPSEL | Transmit 8b10b encoder disparity octet-swapping mode select. | RW | 0
|  | 0 | [txswap_gbe_mode] Transmit octet swap mode is set for IEEE 1GBASE-* operation. |  |
|  | 1 | [txswap_fc_mode] Transmit octet swap mode is set for FibreChannel operation. |  |

### PCSLANE : LNTV_R0

Address offset | 0x050
Physical address | 0x0004 1050 | Instance | serdes_0_pcs_lane0
| 0x0004 4050 |  | serdes_0_pcs_lane2
| 0x0008 2050 |  | serdes_1_pcs_lane1
| 0x0010 4050 |  | serdes_2_pcs_lane2
| 0x0020 4050 |  | serdes_3_pcs_lane2
| 0x0010 8050 |  | serdes_2_pcs_lane3
| 0x0008 8050 |  | serdes_1_pcs_lane3
| 0x0004 2050 |  | serdes_0_pcs_lane1
| 0x0004 8050 |  | serdes_0_pcs_lane3
| 0x0008 1050 |  | serdes_1_pcs_lane0
| 0x0010 2050 |  | serdes_2_pcs_lane1
| 0x0020 8050 |  | serdes_3_pcs_lane3
| 0x0010 1050 |  | serdes_2_pcs_lane0
| 0x0020 2050 |  | serdes_3_pcs_lane1
| 0x0020 1050 |  | serdes_3_pcs_lane0
| 0x0008 4050 |  | serdes_1_pcs_lane2
Description | Native mode options
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | Reserved |  | RO Rreturns0s | 0x0 0000
12 | LNTV_TX_MODE | Boolean for selecting native transmit data path. | RW | 0
11:9 | LNTV_TX_OUT_WIDTH | Native transmit bus-width to PMA. | RW | 0x7
|  | 0x0 | [native_tx_pma_width_8] Transmit PMA data bus width is 8 bits. |  |
|  | 0x1 | [native_tx_pma_width_10] Transmit PMA data bus width is 10 bits. |  |
|  | 0x2 | [native_tx_pma_width_8a] Transmit PMA data bus width is 8 bits. |  |
|  | 0x3 | [native_tx_pma_width_10a] Transmit PMA data bus width is 10 bits. |  |
|  | 0x4 | [native_tx_pma_width_16] Transmit PMA data bus width is 16 bits. |  |
|  | 0x5 | [native_tx_pma_width_20] Transmit PMA data bus width is 20 bits. |  |
|  | 0x6 | [native_tx_pma_width_32] Transmit PMA data bus width is 32 bits. |  |
|  | 0x7 | [native_tx_pma_width_40] Transmit PMA data bus width is 40 bits. |  |
8 | LNTV_TX_GEAR | Native transmit fabric interface configuration. | RW | 0
|  | 0 | [fabric_same_freq_as_pma] No gearing between PMA and fabric. |  |
|  | 1 | [fabric_half_freq_of_pma] Fabric interface runs half frequency of PMA. |  |
7:5 | Reserved |  | RO Rreturns0s | 0x0
4 | LNTV_RX_MODE | Boolean for selecting native receive data path. | RW | 0
3:1 | LNTV_RX_IN_WIDTH | Native receive bus-width from PMA. | RW | 0x7
|  | 0x0 | [native_rx_pma_width_8] Receive PMA data bus width is 8 bits. |  |
|  | 0x1 | [native_rx_pma_width_10] Receive PMA data bus width is 10 bits. |  |
|  | 0x2 | [native_rx_pma_width_8a] Receive PMA data bus width is 8 bits. |  |
|  | 0x3 | [native_rx_pma_width_10a] Receive PMA data bus width is 10 bits. |  |
|  | 0x4 | [native_rx_pma_width_16] Receive PMA data bus width is 16 bits. |  |
|  | 0x5 | [native_rx_pma_width_20] Receive PMA data bus width is 20 bits. |  |
|  | 0x6 | [native_rx_pma_width_32] Receive PMA data bus width is 32 bits. |  |
|  | 0x7 | [native_rx_pma_width_40] Receive PMA data bus width is 40 bits. |  |
0 | LNTV_RX_GEAR | Native receive fabric interface configuration. | RW | 0
|  | 0 | [fabric_same_freq_as_pma] No gearing between PMA and fabric. |  |
|  | 1 | [fabric_half_freq_of_pma] Fabric interface runs half frequency of PMA. |  |

### PCSLANE : LCLK_R0

Address offset | 0x058
Physical address | 0x0004 1058 | Instance | serdes_0_pcs_lane0
| 0x0004 4058 |  | serdes_0_pcs_lane2
| 0x0008 2058 |  | serdes_1_pcs_lane1
| 0x0010 4058 |  | serdes_2_pcs_lane2
| 0x0020 4058 |  | serdes_3_pcs_lane2
| 0x0010 8058 |  | serdes_2_pcs_lane3
| 0x0008 8058 |  | serdes_1_pcs_lane3
| 0x0004 2058 |  | serdes_0_pcs_lane1
| 0x0004 8058 |  | serdes_0_pcs_lane3
| 0x0008 1058 |  | serdes_1_pcs_lane0
| 0x0010 2058 |  | serdes_2_pcs_lane1
| 0x0020 8058 |  | serdes_3_pcs_lane3
| 0x0010 1058 |  | serdes_2_pcs_lane0
| 0x0020 2058 |  | serdes_3_pcs_lane1
| 0x0020 1058 |  | serdes_3_pcs_lane0
| 0x0008 4058 |  | serdes_1_pcs_lane2
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:21 | Reserved |  | RO Rreturns0s | 0x000
20 | LCLK_RXFWF_WCLK_PIPE | Forces use of PIPE Tx clock for writing into Rx FWF. | RW | 0
|  | 0 | [rxfwf_wclk_neq_pipe_tx_clock] Rx FWF PIPE sub-mode disabled |  |
|  | 1 | [rxfwf_wclk_eq_pipe_tx_clock] Rx FWF PIPE sub-mode enabled |  |
19:18 | LCLK_TXFWF_RCLK_SEL | Source selection for Tx FWF read clock. | RW | 0x0
|  | 0x0 | [txfwf_rclk_suppressed] Tx FWF read clock is not toggled. |  |
|  | 0x1 | [txfwf_rclk_follows_pcs_tx_clk] Tx FWF read clock is same as pcs_tx_clk. |  |
|  | 0x2 | [txfwf_rclk_is_pcs_tx_clk_div_2] Tx FWF read clock is pcs_tx_clk divided by two. |  |
|  | 0x3 | [txfwf_rclk_is_pcs_tx_clk_times_2] Tx FWF read clock toggles twice rate of Tx PCS. |  |
17:16 | LCLK_RXFWF_WCLK_SEL | Source selection for Rx FWF write clock. | RW | 0x0
|  | 0x0 | [rxfwf_wclk_suppressed] Rx FWF write clock is not toggled. |  |
|  | 0x1 | [rxfwf_wclk_follows_pcs_rx_clk] Rx FWF write clock is same as pcs_rx_clk. |  |
|  | 0x2 | [rxfwf_wclk_is_pcs_rx_clk_div_2] Rx FWF write clock is pcs_rx_clk divided by two. |  |
|  | 0x3 | [rxfwf_wclk_is_pcs_rx_clk_times_2] Rx FWF write clock toggles twice rate of Rx PCS |  |
15:13 | Reserved |  | RO Rreturns0s | 0x0
12:11 | LCLK_PCS_TX_CLK_SEL | Source selection for internal transmitter clock, known as pcs_tx_clk. | RW | 0x0
|  | 0x0 | [pcs_tx_clk_suppressed] Internal transmit clock in PCS is not toggling. |  |
|  | 0x1 | [pcs_tx_clk_follows_pma_10_clk] Internal transmit clock in PCS sources from PMA 8/10-bit bus clock. |  |
|  | 0x2 | [pcs_tx_clk_follows_pma_20_clk] Internal transmit clock in PCS sources from PMA 16/20-bit bus clock. |  |
|  | 0x3 | [pcs_tx_clk_follows_pma_40_clk] Internal transmit clock in PCS sources from PMA 32/40-bit bus clock. |  |
10:9 | LCLK_PCS_RX_CLK_SEL | Source selection for internal receiver clock, known as pcs_rx_clk. | RW | 0x0
|  | 0x0 | [pcs_rx_clk_suppressed] Internal receive clock in PCS is not toggling. |  |
|  | 0x1 | [pcs_rx_clk_follows_pma_10_clk] Internal receive clock in PCS sources from PMA 8/10-bit bus clock. |  |
|  | 0x2 | [pcs_rx_clk_follows_pma_20_clk] Internal receive clock in PCS sources from PMA 16/20-bit bus clock. |  |
|  | 0x3 | [pcs_rx_clk_follows_pma_40_clk] Internal receive clock in PCS sources from PMA 32/40-bit bus clock. |  |
8 | LCLK_TXFWF_TMG_MODE | Fabric interface timing mode for the Tx FWF. | RW | 0
|  | 0 | [txfwf_phase_compensating] Fabric clock for Tx FWF writes is allowed to have arbitrary phase with respect to the Rx FWF read clock. |  |
|  | 1 | [txfwf_deterministic] Fabric clock for Tx FWF writes must meet a maximum delay with respect to the Tx FWF read clock. |  |
7 | Reserved |  | RO Rreturns0s | 0
6 | LCLK_EPCS_TX_CLK_ERR | Boolean error flag regarding source selection of the tx_clk clock output to the fabric. | RO | 0
5:4 | LCLK_EPCS_TX_CLK_SEL | Transmit fabric output clock source selection. If selection is not possible, then the TX_CLK_ERR status bit flag will be raised. | RW | 0x0
|  | 0x0 | [tx_clk_suppress] Fabric tx_clk will not toggle. |  |
|  | 0x1 | [tx_clk_same_as_txfwf_rclk] Fabric tx_clk same freq as Tx FWF rclk. |  |
|  | 0x2 | [tx_clk_2xfreq_of_txfwf_rclk] Fabric tx_clk twice freq of Tx FWF rclk. |  |
|  | 0x3 | [tx_clk_4xfreq_of_txfwf_rclk] Fabric tx_clk four times freq of Tx FWF rclk. |  |
3 | Reserved |  | RO Rreturns0s | 0
2 | LCLK_EPCS_RX_CLK_ERR | Boolean error flag regarding source selection of the rx_clk clock output to the fabric. | RO | 0
1:0 | LCLK_EPCS_RX_CLK_SEL | Receive fabric output clock source selection. If selection is not possible, then the RX_CLK_ERR status bit flag will be raised. | RW | 0x0
|  | 0x0 | [rx_clk_suppress] Fabric rx_clk will not toggle. |  |
|  | 0x1 | [rx_clk_same_as_rxfwf_wclk] Fabric rx_clk same freq as Rx FWF wclk. |  |
|  | 0x2 | [rx_clk_2xfreq_of_rxfwf_wclk] Fabric rx_clk twice freq of Rx FWF wclk. |  |
|  | 0x3 | [rx_clk_4xfreq_of_rxfwf_wclk] Fabric rx_clk four times freq of Rx FWF wclk. |  |

### PCSLANE : LCLK_R1

Address offset | 0x05C
Physical address | 0x0004 105C | Instance | serdes_0_pcs_lane0
| 0x0004 405C |  | serdes_0_pcs_lane2
| 0x0008 205C |  | serdes_1_pcs_lane1
| 0x0010 405C |  | serdes_2_pcs_lane2
| 0x0020 405C |  | serdes_3_pcs_lane2
| 0x0010 805C |  | serdes_2_pcs_lane3
| 0x0008 805C |  | serdes_1_pcs_lane3
| 0x0004 205C |  | serdes_0_pcs_lane1
| 0x0004 805C |  | serdes_0_pcs_lane3
| 0x0008 105C |  | serdes_1_pcs_lane0
| 0x0010 205C |  | serdes_2_pcs_lane1
| 0x0020 805C |  | serdes_3_pcs_lane3
| 0x0010 105C |  | serdes_2_pcs_lane0
| 0x0020 205C |  | serdes_3_pcs_lane1
| 0x0020 105C |  | serdes_3_pcs_lane0
| 0x0008 405C |  | serdes_1_pcs_lane2
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:26 | Reserved |  | RO Rreturns0s | 0x00
25 | LCLK_ENA_PIPE_OUT | Enable for pipe_lane_clk_out to quad-level logic. | RW | 1
|  | 0 | [pipe_quad_clk_disabled] |  |
|  | 1 | [pipe_quad_clk_enabled] |  |
24 | LCLK_ENA_PIPE_LCL | Enable for pipe_rxclk and pipe_pclk_fab clocks. | RW | 1
|  | 0 | [pipe_local_clk_disabled] |  |
|  | 1 | [pipe_local_clk_enabled] |  |
23:20 | Reserved |  | RO Rreturns0s | 0x0
19 | LCLK_ENA_NATIVE_TXFWF_RCLK | Clock enable for native mode Tx FWF read clock. | RW | 0
|  | 0 | [native_txfwf_rclk_disabled] |  |
|  | 1 | [native_txfwf_rclk_enabled] |  |
18 | LCLK_ENA_NATIVE_TX_CLK | Clock enable for native mode Tx data path. | RW | 0
|  | 0 | [native_tx_data_clk_disabled] |  |
|  | 1 | [native_tx_data_clk_enabled] |  |
17 | LCLK_ENA_NATIVE_RXFWF_WCLK | Clock enable for native mode Rx FWF write clock. | RW | 0
|  | 0 | [native_rxfwf_wclk_disabled] |  |
|  | 1 | [native_rxfwf_wclk_enabled] |  |
16 | LCLK_ENA_NATIVE_RX_CLK | Clock enable for native mode Rx data path. | RW | 0
|  | 0 | [native_rx_data_clk_disabled] |  |
|  | 1 | [native_rx_data_clk_enabled] |  |
15:12 | Reserved |  | RO Rreturns0s | 0x0
11 | LCLK_ENA_8B10B_TXFWF_RCLK | Clock enable for 8b10b mode Tx FWF read clock. | RW | 0
|  | 0 | [8b10b_txfwf_rclk_disabled] |  |
|  | 1 | [8b10b_txfwf_rclk_enabled] |  |
10 | LCLK_ENA_8B10B_TX_CLK | Clock enable for 8b10b mode Tx data path clock. | RW | 0
|  | 0 | [8b10b_tx_data_clk_disabled] |  |
|  | 1 | [8b10b_tx_data_clk_enabled] |  |
9 | LCLK_ENA_8B10B_RXFWF_WCLK | Clock enable for 8b10b mode Rx FWF write clock. | RW | 0
|  | 0 | [8b10b_rxfwf_wclk_disabled] |  |
|  | 1 | [8b10b_rxfwf_wclk_enabled] |  |
8 | LCLK_ENA_8B10B_RX_CLK | Clock enable for 8b10b mode Rx data path clock. | RW | 0
|  | 0 | [8b10b_rx_data_clk_disabled] |  |
|  | 1 | [8b10b_rx_data_clk_enabled] |  |
7:4 | Reserved |  | RO Rreturns0s | 0x0
3 | LCLK_ENA_64B6XB_TX_CLK_DIV2 | Clock enable for 64b6xb mode Tx data path div2 clock. | RW | 0
|  | 0 | [64b6x_tx_data_clk_div2_disabled] |  |
|  | 1 | [64b6x_tx_data_clk_div2_enabled] |  |
2 | LCLK_ENA_64B6XB_TX_CLK | Clock enable for 64b6xb mode Tx data path clock. | RW | 0
|  | 0 | [64b6x_tx_data_clk_disabled] |  |
|  | 1 | [64b6x_tx_data_clk_enabled] |  |
1 | LCLK_ENA_64B6XB_RX_CLK_DIV2 | Clock enable for 64b6xb mode Rx data path div2 clock. | RW | 0
|  | 0 | [64b6x_rx_data_clk_div2_disabled] |  |
|  | 1 | [64b6x_rx_data_clk_div2_enabled] |  |
0 | LCLK_ENA_64B6XB_RX_CLK | Clock enable for 64b6xb mode Rx data path clock. | RW | 0
|  | 0 | [64b6x_rx_data_clk_disabled] |  |
|  | 1 | [64b6x_rx_data_clk_enabled] |  |

### PCSLANE : LRST_R0

Address offset | 0x068
Physical address | 0x0004 1068 | Instance | serdes_0_pcs_lane0
| 0x0004 4068 |  | serdes_0_pcs_lane2
| 0x0008 2068 |  | serdes_1_pcs_lane1
| 0x0010 4068 |  | serdes_2_pcs_lane2
| 0x0020 4068 |  | serdes_3_pcs_lane2
| 0x0010 8068 |  | serdes_2_pcs_lane3
| 0x0008 8068 |  | serdes_1_pcs_lane3
| 0x0004 2068 |  | serdes_0_pcs_lane1
| 0x0004 8068 |  | serdes_0_pcs_lane3
| 0x0008 1068 |  | serdes_1_pcs_lane0
| 0x0010 2068 |  | serdes_2_pcs_lane1
| 0x0020 8068 |  | serdes_3_pcs_lane3
| 0x0010 1068 |  | serdes_2_pcs_lane0
| 0x0020 2068 |  | serdes_3_pcs_lane1
| 0x0020 1068 |  | serdes_3_pcs_lane0
| 0x0008 4068 |  | serdes_1_pcs_lane2
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | Reserved |  | RO Rreturns0s | 0x0000
16 | LRST_SOFT_PIPE_RESET | Soft reset for PIPE logic. | RW | 0
|  | 0 | [pipe_soft_reset_false] |  |
|  | 1 | [pipe_soft_reset_true] |  |
15:12 | Reserved |  | RO Rreturns0s | 0x0
11 | LRST_SOFT_TXFWF_RESET | Soft reset for Tx Fly-Wheel FIFO. | RW | 0
|  | 0 | [txfwf_soft_reset_false] |  |
|  | 1 | [txfwf_soft_reset_true] |  |
10 | LRST_ULCKD_PLL_RESETS_PCS_TX | Unlocked PLL automatically resets PCS Tx domain logic. | RW | 0
|  | 0 | [pcs_tx_rst_upon_unlocked_plll_false] |  |
|  | 1 | [pcs_tx_rst_upon_unlocked_plll_true] |  |
9 | LRST_SOFT_PCS_TX_DIV2_RESET | Soft reset for PCS Tx clock divider. | RW | 0
|  | 0 | [pcs_tx_clk_div_soft_reset_false] |  |
|  | 1 | [pcs_tx_clk_div_soft_reset_true] |  |
8 | LRST_SOFT_PCS_TX_RESET | Soft reset for PCS Tx. | RW | 0
|  | 0 | [pcs_tx_soft_reset_false] |  |
|  | 1 | [pcs_tx_soft_reset_true] |  |
7:4 | Reserved |  | RO Rreturns0s | 0x0
3 | LRST_SOFT_RXFWF_RESET | Soft reset for Rx Fly-Wheel FIFO. | RW | 0
|  | 0 | [rxfwf_soft_reset_false] |  |
|  | 1 | [rxfwf_soft_reset_true] |  |
2 | LRST_ULCKD_CDR_RESETS_PCS_RX | Unlocked CDR automatically resets PCS Rx domain logic. | RW | 1
|  | 0 | [pcs_rx_rst_upon_unlocked_cdr_false] |  |
|  | 1 | [pcs_rx_rst_upon_unlocked_cdr_true] |  |
1 | LRST_SOFT_PCS_RX_DIV2_RESET | Soft reset for PCS Rx clock divider. | RW | 0
|  | 0 | [pcs_rx_clk_div_soft_reset_false] |  |
|  | 1 | [pcs_rx_clk_div_soft_reset_true] |  |
0 | LRST_SOFT_PCS_RX_RESET | Soft reset for PCS Rx. | RW | 0
|  | 0 | [pcs_rx_soft_reset_false] |  |
|  | 1 | [pcs_rx_soft_reset_true] |  |

### PCSLANE : LRST_OPT

Address offset | 0x06C
Physical address | 0x0004 106C | Instance | serdes_0_pcs_lane0
| 0x0004 406C |  | serdes_0_pcs_lane2
| 0x0008 206C |  | serdes_1_pcs_lane1
| 0x0010 406C |  | serdes_2_pcs_lane2
| 0x0020 406C |  | serdes_3_pcs_lane2
| 0x0010 806C |  | serdes_2_pcs_lane3
| 0x0008 806C |  | serdes_1_pcs_lane3
| 0x0004 206C |  | serdes_0_pcs_lane1
| 0x0004 806C |  | serdes_0_pcs_lane3
| 0x0008 106C |  | serdes_1_pcs_lane0
| 0x0010 206C |  | serdes_2_pcs_lane1
| 0x0020 806C |  | serdes_3_pcs_lane3
| 0x0010 106C |  | serdes_2_pcs_lane0
| 0x0020 206C |  | serdes_3_pcs_lane1
| 0x0020 106C |  | serdes_3_pcs_lane0
| 0x0008 406C |  | serdes_1_pcs_lane2
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | Reserved |  | RO Rreturns0s | 0x0000 0000
1 | LRST_DISABLE_FAB_PCS_RESET_FOR_TX | Optional disable preventing PCS Tx logic reset from being activated by the fabric pcs_reset_n port. | RW | 0
|  | 0 | [enable_fab_pcs_reset_impact_pcs_tx] |  |
|  | 1 | [disable_fab_pcs_reset_impact_pcs_tx] |  |
0 | LRST_DISABLE_FAB_PCS_RESET_FOR_RX | Optional disable preventing PCS Rx logic reset from being activated by the fabric pcs_reset_n port. | RW | 0
|  | 0 | [enable_fab_pcs_reset_impact_pcs_rx] |  |
|  | 1 | [disable_fab_pcs_reset_impact_pcs_rx] |  |

### PCSLANE : OOB_R0

Address offset | 0x078
Physical address | 0x0004 1078 | Instance | serdes_0_pcs_lane0
| 0x0004 4078 |  | serdes_0_pcs_lane2
| 0x0008 2078 |  | serdes_1_pcs_lane1
| 0x0010 4078 |  | serdes_2_pcs_lane2
| 0x0020 4078 |  | serdes_3_pcs_lane2
| 0x0010 8078 |  | serdes_2_pcs_lane3
| 0x0008 8078 |  | serdes_1_pcs_lane3
| 0x0004 2078 |  | serdes_0_pcs_lane1
| 0x0004 8078 |  | serdes_0_pcs_lane3
| 0x0008 1078 |  | serdes_1_pcs_lane0
| 0x0010 2078 |  | serdes_2_pcs_lane1
| 0x0020 8078 |  | serdes_3_pcs_lane3
| 0x0010 1078 |  | serdes_2_pcs_lane0
| 0x0020 2078 |  | serdes_3_pcs_lane1
| 0x0020 1078 |  | serdes_3_pcs_lane0
| 0x0008 4078 |  | serdes_1_pcs_lane2
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | OOB_WAKE_MAX_CYCLE | The maximum time allowed for COMWAKE Idle in terms of 10 UI (150MHz). | RW | 0x11
23:16 | OOB_WAKE_MIN_CYCLE | The minimum time allowed for COMWAKE Idle in terms of10 UI (150MHz). | RW | 0x0F
15:8 | OOB_BURST_MAX_CYCLE | The maximum time allowed for OOB Burst in terms of 10 UI (150MHz). | RW | 0x11
7:0 | OOB_BURST_MIN_CYCLE | The minimum time allowed for OOB Burst in terms of 10 UI (150MHz). | RW | 0x0F

### PCSLANE : OOB_R1

Address offset | 0x07C
Physical address | 0x0004 107C | Instance | serdes_0_pcs_lane0
| 0x0004 407C |  | serdes_0_pcs_lane2
| 0x0008 207C |  | serdes_1_pcs_lane1
| 0x0010 407C |  | serdes_2_pcs_lane2
| 0x0020 407C |  | serdes_3_pcs_lane2
| 0x0010 807C |  | serdes_2_pcs_lane3
| 0x0008 807C |  | serdes_1_pcs_lane3
| 0x0004 207C |  | serdes_0_pcs_lane1
| 0x0004 807C |  | serdes_0_pcs_lane3
| 0x0008 107C |  | serdes_1_pcs_lane0
| 0x0010 207C |  | serdes_2_pcs_lane1
| 0x0020 807C |  | serdes_3_pcs_lane3
| 0x0010 107C |  | serdes_2_pcs_lane0
| 0x0020 207C |  | serdes_3_pcs_lane1
| 0x0020 107C |  | serdes_3_pcs_lane0
| 0x0008 407C |  | serdes_1_pcs_lane2
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | OOB_SAS_MAX_CYCLE | The maximum time allowed for COMSAS Idle in terms of 10 UI (150MHz). | RW | 0x98
23:16 | OOB_SAS_MIN_CYCLE | The minimum time allowed for COMSAS Idle in terms of 10 UI (150MHz). | RW | 0x88
15:8 | OOB_RST_INIT_MAX_CYCLE | The maximum time allowed for COMRESET / COMINIT Idle in terms of 10 UI (150MHz). | RW | 0x33
7:0 | OOB_RST_INIT_MIN_CYCLE | The minimum time allowed for COMRESET / COMINIT Idle in terms of 10 UI (150MHz). | RW | 0x2D

### PCSLANE : OOB_R2

Address offset | 0x080
Physical address | 0x0004 1080 | Instance | serdes_0_pcs_lane0
| 0x0004 4080 |  | serdes_0_pcs_lane2
| 0x0008 2080 |  | serdes_1_pcs_lane1
| 0x0010 4080 |  | serdes_2_pcs_lane2
| 0x0020 4080 |  | serdes_3_pcs_lane2
| 0x0010 8080 |  | serdes_2_pcs_lane3
| 0x0008 8080 |  | serdes_1_pcs_lane3
| 0x0004 2080 |  | serdes_0_pcs_lane1
| 0x0004 8080 |  | serdes_0_pcs_lane3
| 0x0008 1080 |  | serdes_1_pcs_lane0
| 0x0010 2080 |  | serdes_2_pcs_lane1
| 0x0020 8080 |  | serdes_3_pcs_lane3
| 0x0010 1080 |  | serdes_2_pcs_lane0
| 0x0020 2080 |  | serdes_3_pcs_lane1
| 0x0020 1080 |  | serdes_3_pcs_lane0
| 0x0008 4080 |  | serdes_1_pcs_lane2
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | TXOOB_PROG_DATA_L32B | Programmable TX OOB Burst Data[31:0] | RW | 0x0000 0000

### PCSLANE : OOB_R3

Address offset | 0x084
Physical address | 0x0004 1084 | Instance | serdes_0_pcs_lane0
| 0x0004 4084 |  | serdes_0_pcs_lane2
| 0x0008 2084 |  | serdes_1_pcs_lane1
| 0x0010 4084 |  | serdes_2_pcs_lane2
| 0x0020 4084 |  | serdes_3_pcs_lane2
| 0x0010 8084 |  | serdes_2_pcs_lane3
| 0x0008 8084 |  | serdes_1_pcs_lane3
| 0x0004 2084 |  | serdes_0_pcs_lane1
| 0x0004 8084 |  | serdes_0_pcs_lane3
| 0x0008 1084 |  | serdes_1_pcs_lane0
| 0x0010 2084 |  | serdes_2_pcs_lane1
| 0x0020 8084 |  | serdes_3_pcs_lane3
| 0x0010 1084 |  | serdes_2_pcs_lane0
| 0x0020 2084 |  | serdes_3_pcs_lane1
| 0x0020 1084 |  | serdes_3_pcs_lane0
| 0x0008 4084 |  | serdes_1_pcs_lane2
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | TXOOB_PROG_DATA_H8B | Programmable TX OOB Burst Data[39:32] | RW | 0x00

### PCSLANE : PMA_CTRL_R0

Address offset | 0x088
Physical address | 0x0004 1088 | Instance | serdes_0_pcs_lane0
| 0x0004 4088 |  | serdes_0_pcs_lane2
| 0x0008 2088 |  | serdes_1_pcs_lane1
| 0x0010 4088 |  | serdes_2_pcs_lane2
| 0x0020 4088 |  | serdes_3_pcs_lane2
| 0x0010 8088 |  | serdes_2_pcs_lane3
| 0x0008 8088 |  | serdes_1_pcs_lane3
| 0x0004 2088 |  | serdes_0_pcs_lane1
| 0x0004 8088 |  | serdes_0_pcs_lane3
| 0x0008 1088 |  | serdes_1_pcs_lane0
| 0x0010 2088 |  | serdes_2_pcs_lane1
| 0x0020 8088 |  | serdes_3_pcs_lane3
| 0x0010 1088 |  | serdes_2_pcs_lane0
| 0x0020 2088 |  | serdes_3_pcs_lane1
| 0x0020 1088 |  | serdes_3_pcs_lane0
| 0x0008 4088 |  | serdes_1_pcs_lane2
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:29 | Reserved |  | RO Rreturns0s | 0x0
28 | PMA_TXPLL_LOCK_STATUS | Status of PMA lane TX PLL lock state. 1 : PMA lane TX PLL is locked. 0 : PMA lane TX PLL is not locked. | RO | 0
|  | Read 0 | [pma_txpll_lock_false] |  |
|  | Read 1 | [pma_txpll_lock_true] |  |
27 | PMA_TXPLL_UNLOCK_INT | Interrupt signal for indication of PMA lane TX PLL unlock. | RW W1toClr | 0
|  | 0 | [pma_txpll_unlock_int_deasserted] Interrrupt signal for PMA TX PLL unlock is deasserted. |  |
|  | 1 | [pma_txpll_unlock_int_asserted] Interrrupt signal for PMA TX PLL unlock is asserted. |  |
26 | PMA_TXPLL_LOCK_INT | Interrupt signal for indication of PMA lane TX PLL lock. | RW W1toClr | 0
|  | 0 | [pma_txpll_lock_int_deasserted] Interrrupt signal for PMA TX PLL lock is deasserted. |  |
|  | 1 | [pma_txpll_lock_int_asserted] Interrrupt signal for PMA TX PLL lock is asserted. |  |
25 | PMA_TXPLL_UNLOCK_INT_MASK | Masking interrupt signal generation for indication of PMA lane TX PLL unlock. | RW | 1
|  | 0 | [pma_txpll_unlock_int_mask_disabled] Disables Masking bit of the interrupt signal generated when PMA TX PLL is unlocked. |  |
|  | 1 | [pma_txpll_unlock_int_mask_enabled] Enables Masking bit of the interrupt signal generated when PMA TX PLL is unlocked. |  |
24 | PMA_TXPLL_LOCK_INT_MASK | Masking interrupt signal generation for indication of PMA lane TX PLL lock. | RW | 1
|  | 0 | [pma_txpll_lock_int_mask_disabled] Disables Masking bit of the interrupt signal generated when PMA TX PLL is locked. |  |
|  | 1 | [pma_txpll_lock_int_mask_enabled] Enables Masking bit of the interrupt signal generated when PMA TX PLL is locked. |  |
23:22 | Reserved |  | RO Rreturns0s | 0x0
21 | PMA_RXPLL_LOCK_STATUS | Status of PMA lane RX PLL lock state. 1 : PMA lane RX PLL is locked. 0 : PMA lane RX PLL is not locked. | RO | 0
|  | Read 0 | [pma_rxpll_lock_false] |  |
|  | Read 1 | [pma_rxpll_lock_true] |  |
20 | PMA_RXPLL_FLOCK_SEL | Select RXPLL LOCK status vs. RXPLL FLOCK status | RW | 0
|  | 0 | [pma_rxpll_lock_sel] Select RXPLL LOCK |  |
|  | 1 | [pma_rxpll_flock_sel] Select RXPLL FLOCK |  |
19 | PMA_RXPLL_UNLOCK_INT | Interrupt signal for indication of PMA lane RX PLL unlock. | RW W1toClr | 0
|  | 0 | [pma_rxpll_unlock_int_deasserted] Interrrupt signal for PMA RX PLL unlock is deasserted. |  |
|  | 1 | [pma_rxpll_unlock_int_asserted] Interrrupt signal for PMA RX PLL unlock is asserted. |  |
18 | PMA_RXPLL_LOCK_INT | Interrupt signal for indication of PMA lane RX PLL lock. | RW W1toClr | 0
|  | 0 | [pma_rxpll_lock_int_deasserted] Interrrupt signal for PMA RX PLL lock is deasserted. |  |
|  | 1 | [pma_rxpll_lock_int_asserted] Interrrupt signal for PMA RX PLL lock is asserted. |  |
17 | PMA_RXPLL_UNLOCK_INT_MASK | Masking interrupt signal generation for indication of PMA lane RX PLL unlock. | RW | 1
|  | 0 | [pma_rxpll_unlock_int_mask_disabled] Disables Masking bit of the interrupt signal generated when PMA RX PLL is unlocked. |  |
|  | 1 | [pma_rxpll_unlock_int_mask_enabled] Enables Masking bit of the interrupt signal generated when PMA RX PLL is unlocked. |  |
16 | PMA_RXPLL_LOCK_INT_MASK | Masking interrupt signal generation for indication of PMA lane RX PLL lock. | RW | 1
|  | 0 | [pma_rxpll_lock_int_mask_disabled] Disables Masking bit of the interrupt signal generated when PMA RX PLL is locked. |  |
|  | 1 | [pma_rxpll_lock_int_mask_enabled] Enables Masking bit of the interrupt signal generated when PMA RX PLL is locked. |  |
15:13 | Reserved |  | RO Rreturns0s | 0x0
12 | PMA_P2_STATUS | Status of PMA lane P2 state. 1 : PMA is in P2 state. 0 : PMA is not in P2 state. | RO | 0
|  | Read 0 | [pma_P2_false] |  |
|  | Read 1 | [pma_P2_true] |  |
11 | PMA_P2_EXIT_INT | Interrupt signal for indication of PMA lane exiting from P2 states. | RW W1toClr | 0
|  | 0 | [pma_p2_exit_int_deasserted] Interrrupt signal for PMA lane exiting from P2 state is deasserted. |  |
|  | 1 | [pma_p2_exit_int_asserted] Interrrupt signal for PMA lane exiting from P2 state is asserted. |  |
10 | PMA_P2_ENTER_INT | Interrupt signal for indication of PMA lane entering into P2 states. | RW W1toClr | 0
|  | 0 | [pma_p2_enter_int_deasserted] Interrrupt signal for PMA lane entering into P2 state is deasserted. |  |
|  | 1 | [pma_p2_enter_int_asserted] Interrrupt signal for PMA lane entering into P2 state is asserted. |  |
9 | PMA_P2_EXIT_INT_MASK | Masking interrupt signal generation for indication of PMA lane exiting from P2 state. | RW | 1
|  | 0 | [pma_p2_exit_int_mask_disabled] Disables Masking bit of the interrupt signal generation for PMA lane exiting from P2 state. |  |
|  | 1 | [pma_p2_exit_int_mask_enabled] Enables Masking bit of the interrupt signal generation for PMA lane exiting from P2 state. |  |
8 | PMA_P2_ENTER_INT_MASK | Masking interrupt signal generation for indication of PMA lane entering into P2 state. | RW | 1
|  | 0 | [pma_p2_enter_int_mask_disabled] Disables Masking bit of the interrupt signal generation for PMA lane entering into P2 state. |  |
|  | 1 | [pma_p2_enter_int_mask_enabled] Enables Masking bit of the interrupt signal generation for PMA lane entering into P2 state. |  |
7 | Reserved |  | RO Rreturns0s | 0
6 | FAB_EPCS_PMA_RESET_B_EN | PMA active low reset from Fabric enable | RW | 1
|  | 0 | [fabric_ pma_reset_b_disabled] PMA active low reset controlled by Fabric disabled |  |
|  | 1 | [fabric_ pma_reset_b_enabled] PMA active low reset controlled by Fabric enabled |  |
5 | FLASH_FREEZE_P2_EN | Flash freeze P2 powerdown enable | RW | 0
|  | 0 | [flash_freeze_p2_pd_disabled] Flash Freeze P2 powerdown disabled |  |
|  | 1 | [flash_freeze_p2_pd_enabled] Flash Freeze P2 powerdown enabled |  |
4 | FLASH_FREEZE_P1_EN | Flash freeze P1 powerdown enable | RW | 0
|  | 0 | [flash_freeze_p1_pd_disabled] Flash Freeze P1 powerdown disabled |  |
|  | 1 | [flash_freeze_p1_pd_enabled] Flash Freeze P1 powerdown enabled |  |
3 | FLASH_FREEZE_P0S_EN | Flash freeze P0s powerdown enable | RW | 0
|  | 0 | [flash_freeze_p0s_pd_disabled] Flash Freeze P0s powerdown disabled |  |
|  | 1 | [flash_freeze_p0s_pd_enabled] Flash Freeze P0s powerdown enabled |  |
2 | PIPE_P2_EN | PIPE P2 powerdown enable | RW | 1
|  | 0 | [pipe_p2_pd_disabled] PIPE P2 powerdown disabled |  |
|  | 1 | [pipe_p2_pd_enabled] PIPE P2 powerdown enabled |  |
1 | PIPE_P1_EN | PIPE P1 powerdown enable | RW | 1
|  | 0 | [pipe_p1_pd_disabled] PIPE P1 powerdown disabled |  |
|  | 1 | [pipe_p1_pd_enabled] PIPE P1 powerdown enabled |  |
0 | PIPE_P0S_EN | PIPE P0s powerdown enable | RW | 1
|  | 0 | [pipe_p0s_pd_disabled] PIPE P0s powerdown disabled |  |
|  | 1 | [pipe_p0s_pd_enabled] PIPE P0s powerdown enabled |  |

### PCSLANE : PMA_CTRL_R1

Address offset | 0x08C
Physical address | 0x0004 108C | Instance | serdes_0_pcs_lane0
| 0x0004 408C |  | serdes_0_pcs_lane2
| 0x0008 208C |  | serdes_1_pcs_lane1
| 0x0010 408C |  | serdes_2_pcs_lane2
| 0x0020 408C |  | serdes_3_pcs_lane2
| 0x0010 808C |  | serdes_2_pcs_lane3
| 0x0008 808C |  | serdes_1_pcs_lane3
| 0x0004 208C |  | serdes_0_pcs_lane1
| 0x0004 808C |  | serdes_0_pcs_lane3
| 0x0008 108C |  | serdes_1_pcs_lane0
| 0x0010 208C |  | serdes_2_pcs_lane1
| 0x0020 808C |  | serdes_3_pcs_lane3
| 0x0010 108C |  | serdes_2_pcs_lane0
| 0x0020 208C |  | serdes_3_pcs_lane1
| 0x0020 108C |  | serdes_3_pcs_lane0
| 0x0008 408C |  | serdes_1_pcs_lane2
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | Reserved |  | RO Rreturns0s | 0x0
27:16 | TXBEACON_PULSE_WIDTH | TX Beacon pulse width in terms of TX PLL reference clock cycles. | RW | 0x00A
15:12 | Reserved |  | RO Rreturns0s | 0x0
11:0 | RXBEACON_MAX_PULSE_WIDTH | The maximum pulse width (16 us) allowed for RX Beacon in terms of TX PLL reference clock cycles. | RW | 0x640

### PCSLANE : PMA_CTRL_R2

Address offset | 0x090
Physical address | 0x0004 1090 | Instance | serdes_0_pcs_lane0
| 0x0004 4090 |  | serdes_0_pcs_lane2
| 0x0008 2090 |  | serdes_1_pcs_lane1
| 0x0010 4090 |  | serdes_2_pcs_lane2
| 0x0020 4090 |  | serdes_3_pcs_lane2
| 0x0010 8090 |  | serdes_2_pcs_lane3
| 0x0008 8090 |  | serdes_1_pcs_lane3
| 0x0004 2090 |  | serdes_0_pcs_lane1
| 0x0004 8090 |  | serdes_0_pcs_lane3
| 0x0008 1090 |  | serdes_1_pcs_lane0
| 0x0010 2090 |  | serdes_2_pcs_lane1
| 0x0020 8090 |  | serdes_3_pcs_lane3
| 0x0010 1090 |  | serdes_2_pcs_lane0
| 0x0020 2090 |  | serdes_3_pcs_lane1
| 0x0020 1090 |  | serdes_3_pcs_lane0
| 0x0008 4090 |  | serdes_1_pcs_lane2
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | Reserved |  | RO Rreturns0s | 0x00 0000
10 | FAB_DRIVES_TXPADS | Enables transmitting data from Fabric to PMA Serializer Output. | RW | 0
|  | 0 | [fab_drives_txpads_disabled] Disables transmitting data from Fabric to PMA Serializer output. |  |
|  | 1 | [fab_drives_txpads_enabled] Enables transmitting data from Fabric to PMA Serializer output. |  |
9:8 | PIPE_RATE_INIT | Initial PIPE rate setting | RW | 0x0
|  | 0x0 | [pipe_init_rate_pcie1_or_sata1_sel] Select PCIe Gen1 (2.5 GT/s) or SATA 1.0 Mode (1.5 Gb/s) rate for the PIPE initial rate. |  |
|  | 0x1 | [pipe_init_rate_pcie2_or_sata2_sel] Select PCIe Gen2 (5.0 GT/s) or SATA 2.0 Mode (3.0 Gb/s) rate for the PIPE initial rate. |  |
|  | 0x2 | [pipe_init_rate_sata3_sel] Select SATA 3.0 Mode (6.0 Gb/s) rate for the PIPE initial rate. |  |
|  | 0x3 | [pipe_init_rate_default_register_sel] Select default register values of the TXPOSTDIV, TXPOSTDIVEN, RXPLL_FBDIV, RXPLL_REFDIV and RXPLL_RANGE for the PIPE initial rate. |  |
7:0 | PD_PLL_CNT | The minimum time (1 us) required for PMA PLL powerdown during PIPE rate change in terms of TX PLL reference clock cycles. | RW | 0xA6

### PCSLANE : MSTR_CTRL

Address offset | 0x094
Physical address | 0x0004 1094 | Instance | serdes_0_pcs_lane0
| 0x0004 4094 |  | serdes_0_pcs_lane2
| 0x0008 2094 |  | serdes_1_pcs_lane1
| 0x0010 4094 |  | serdes_2_pcs_lane2
| 0x0020 4094 |  | serdes_3_pcs_lane2
| 0x0010 8094 |  | serdes_2_pcs_lane3
| 0x0008 8094 |  | serdes_1_pcs_lane3
| 0x0004 2094 |  | serdes_0_pcs_lane1
| 0x0004 8094 |  | serdes_0_pcs_lane3
| 0x0008 1094 |  | serdes_1_pcs_lane0
| 0x0010 2094 |  | serdes_2_pcs_lane1
| 0x0020 8094 |  | serdes_3_pcs_lane3
| 0x0010 1094 |  | serdes_2_pcs_lane0
| 0x0020 2094 |  | serdes_3_pcs_lane1
| 0x0020 1094 |  | serdes_3_pcs_lane0
| 0x0008 4094 |  | serdes_1_pcs_lane2
Description | Master source control for this lane.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | Reserved |  | RO Rreturns0s | 0x0000 0000
1:0 | LANE_MSTR | Determines the source master lane of a control wire in cases where lanes operate together in a multi-lane link. An example of a control wire which needs to be the same across multiple lanes is ratechange_req_quad_sync This is the rate-change captured onto the shared reference clock for a multi-lane PCI-Express application. | RW | 0x0
|  | 0x0 | [master_is_lane_0] Selection of master control lane |  |
|  | 0x1 | [master_is_lane_1] |  |
|  | 0x2 | [master_is_lane_2] |  |
|  | 0x3 | [master_is_lane_3] |  |

PCSLANE has no common memories.