## QSPIXIP

This section provides information on the QSPIXIP Module Instance. Each of the module registers is described below.

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## QSPIXIP Register Mapping Summary

### QSPIXIP Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CONTROL | RW | 32 | 0x0100 0402 | 0x000 | 0x0702 0100
FRAMES | RW | 32 | 0x0000 0000 | 0x004 | 0x0702 0104
RESERVED | RW | 32 | 0x0000 0000 | 0x008 | 0x0702 0108
INTERRUPTENABLEREGISTER | RW | 32 | 0x0000 0000 | 0x00C | 0x0702 010C
STATUSREGISTER | RO | 32 | 0x0000 0000 | 0x010 | 0x0702 0110
DIRECTACCESS | RW | 32 | 0x0080 0000 | 0x014 | 0x0702 0114
UPPERADDRESS | RW | 32 | 0x0000 0000 | 0x018 | 0x0702 0118
RECEIVEDATA | RO | 32 | 0x0000 0000 | 0x040 | 0x0702 0140
TRANSMITDATA | RW | 32 | 0x0000 0000 | 0x044 | 0x0702 0144
X4RECEIVEDATA | RO | 32 | 0x0000 0000 | 0x048 | 0x0702 0148
X4TRANSMITDATA | WO | 32 | 0x0000 0000 | 0x04C | 0x0702 014C
FRAMESUP | RW | 32 | 0x0000 0000 | 0x050 | 0x0702 0150

## QSPIXIP Register Descriptions

### QSPIXIP : CONTROL

Address offset | 0x000
Physical address | 0x0702 0100 | Instance | QSPIXIP
Description | Control register
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | Reserved |  | RO Rreturns0s | 0x0
27:24 | CLKRATE | Sets the SPI clock rate (master mode) 0: Not Supported N: SPICLK = HCLK/(2*N) No. can vary from 1-15 allowing rates from HCLK/2 to HCLK/30.(HCLK=250 8.3MHz-125MHz; HCLK=400 13.3MHz to 200MHz) | RW | 0x1
23:17 | Reserved |  | RO Rreturns0s | 0x00
16 | FLAGSX4 | This register bits should be set before x4 are used to read and write data. It modifies the FIFO status signals to indicate that four bytes may be read or written. | RW | 0
15:14 | QSPIMODE21 | Sets whether multiple bit SPI operates in normal extended or full modes: 00: Normal (single DQ0 TX and single DQ1 RX lines) 01: Extended RO (command and address bytes on DQ0 only) 10: Extended RW (command byte on DQ0 only) 11: Full. (command and address bytes are on all DQ lines) | RW | 0x0
13 | QSPIMODE0 | Sets whether multiple bit SPI uses 2 or 4 bits of data 0: 2-bits (BSPI) 1: 4-bits (QSPI) | RW | 0
12:11 | SAMPLE | Sets when the core samples SDI in master mode 00: At the rising edge off SPI CLOCK allowing half a SPI clock period round trip delay 01: On the last falling HCLK edge in the SPI clock period at HCLK/2 allows 75% of the SPICLK period for the round trip delay plus 25% hold time 10: At the rising HCLK edge as SPICLK falls allowing a full clock period round trip delay hold time must be positive. | RW | 0x0
10 | CLKIDLE | Sets the clock IDLE to low (0) or high (1).Allows the core to support SPI memory operation in mode 0 or mode 3. When CLKRATE=0 this bit has no effect; the clock IDLE state will always be 1 | RW | 1
9:4 | Reserved |  | RO Rreturns0s | 0x00
3 | XIPADDR | Sets the number of bytes used for the address in XIP mode (1'b0 = 3 bytes 1'b1 = 4 Bytes) | RW | 0
2 | XIP | 0: Normal operation 1: XIP mode | RW | 0
1 | Reserved | 1: Master (Allows slave selection in PFC SPI) | RO Rreturns0s | 1
0 | ENABLE | 0: Core will not respond to external signals until this bit enabled 1: Core is active | RW | 0

### QSPIXIP : FRAMES

Address offset | 0x004
Physical address | 0x0702 0104 | Instance | QSPIXIP
Description | This register is only functional in master mode. It is used to start a master transfer.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | FLAGWORD | If set then the FIFO flags are set to word mode.This sets the FLAGX4 bit in the control register.This bit always reads as zero | RW | 0
30 | FLAGBYTE | If set then the FIFO flags are set to byte mode This clears the FLAGX4 bit in the control register.This bit always reads as zero | RW | 0
29:26 | IDLE | This sets the number of IDLE cycles to be inserted between the TX and RX SPI phases 0 to 15 | RW | 0x0
25 | QSPI | 0: Normal Operation 1: QSPI Mode (2 or 4-bits data as set in control register) | RW | 0
24:16 | CMDBYTES | Sets the number of bytes that create the SPI command 0- 511. When zero the SPI simply transmits a byte when written to the transmit FIFO and writes the received byte to the receive FIFO. When non zero the logic will transmit data from the receive FIFO and discard receive data until CMDBYTES have been transmitted It will the automatically transmit the remaining number of bytes (TOTLABYTES) writing the received data into the receive FIFO | RW | 0x000
15:0 | TOTALBYTES | Number of bytes to be sent/received, 1 to 65535. This register once set will not change an internal counter counts until it reaches the limit set by this register When this register is written the internal counter is also reset. When that counter reaches TOTALBYTES interrupts are generated and idle cycles inserted on the SPI bus (SSEL deactivated). The core will transmit data whenever the transmit FIFO is loaded the counter is used to count bytes terminate bursts and generate interrupts | RW | 0x0000

### QSPIXIP : RESERVED

Address offset | 0x008
Physical address | 0x0702 0108 | Instance | QSPIXIP
Description | Reserved register
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | Reserved |  | RW | 0x0000 0000

### QSPIXIP : INTERRUPTENABLEREGISTER

Address offset | 0x00C
Physical address | 0x0702 010C | Instance | QSPIXIP
Description | This is interrupt enable register for external register.
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved |  | RO Rreturns0s | 0x000 0000
5 | TXFIFOFUL |  | RW | 0
4 | RXFIFOEMPTY |  | RW | 0
3 | TXAVAILABLE |  | RW | 0
2 | RXAVAILABLE |  | RW | 0
1 | RXDONE |  | RW | 0
0 | TXDONE | Enables the external interrupt for the corresponding interrupt. | RW | 0

### QSPIXIP : STATUSREGISTER

Address offset | 0x010
Physical address | 0x0702 0110 | Instance | QSPIXIP
Description | Indicates the status of the SPI core.
Type | RO

Bits | Field Name | Description | Type | Reset
31:9 | Reserved |  | RO Rreturns0s | 0x00 0000
8 | FLAGSX4 | Read of CONTROL registers FLAGSX4. Allows Firmware to check the value at the same time as the status. | RO | 0
7 | READY | Indicates that the SPI master is IDLE and a new transmission may be started. | RO | 0
6 | Reserved |  | RO Rreturns0s | 0
5 | TXFIFOFULL | Indicates that the TX Fifo is full or contains less than 4-empty locations when FLAGSX4 set. | RO | 0
4 | RXFIFOEMPTY | Indicates that the RX Fifo is empty or contains less than 4-bytes when FLAGSX4 set. | RO | 0
3 | TXAVAILABLE | Indicates that there is room for at least one or four (FLAGSX4 set) bytes in the transmit FIFO. | RO | 0
2 | RXAVAILABLE | Indicates that there is at least one or four (FLAGSX4 set) received bytes available in the receive FIFO. | RO | 0
1 | RXDONE | Indicates that all the frames have been received and the RX FIFO is empty Is cleared by writing 1 or when the FRAMES register is written. | RO | 0
0 | TXDONE | Indicates that all the frames have been transmitted.Is cleared by writing 1 or when the FRAMES register is written. | RO | 0

### QSPIXIP : DIRECTACCESS

Address offset | 0x014
Physical address | 0x0702 0114 | Instance | QSPIXIP
Description | This register allows direct access to the QSPI interface pins to support access to non-standard SPI devices via direct CPU control.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | Reserved |  | RO Rreturns0s | 0x00
23 | IDLE | Master SPI FSM is stalled/idle | RO | 1
22 | IP_SSEL | Current SSEL value | RO | 0
21 | IP_SCLK | Current SCLK value | RO | 0
20 | Reserved1 | Reads as Zero | RO | 0
19:16 | IP_SDI | Input data on SDI | RO | 0x0
15:12 | OP_SDOE | Output enables for SDATA | RW | 0x0
11:8 | OP_SDO | Output value for SDATA | RW | 0x0
7:4 | EN_SDO | Enable this register to drive SDATA data and output enable | RW | 0x0
3 | OP_SCLK | Value driven on SCLK | RW | 0
2 | EN_SCLK | Enable this register to drive SCLK | RW | 0
1 | OP_SSEL | Value driven on SSEL | RW | 0
0 | EN_SSEL | Enable this register to drive SSEL | RW | 0

### QSPIXIP : UPPERADDRESS

Address offset | 0x018
Physical address | 0x0702 0118 | Instance | QSPIXIP
Description | This register set the upper 8-bits of the address [31:24] when four byte addressing is being used in XIP mode.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | ADDRUP | Sets the upper address bits [31:24] in XIP mode. | RW | 0x00

### QSPIXIP : RECEIVEDATA

Address offset | 0x040
Physical address | 0x0702 0140 | Instance | QSPIXIP
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | RXDATA | Received data - single byte | RO | 0x00

### QSPIXIP : TRANSMITDATA

Address offset | 0x044
Physical address | 0x0702 0144 | Instance | QSPIXIP
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | TXDATA | Data to send - single byte | WO | 0x00

### QSPIXIP : X4RECEIVEDATA

Address offset | 0x048
Physical address | 0x0702 0148 | Instance | QSPIXIP
Description | Allows the processor to read 4-bytes from the SPI FIFO in a single transaction. Reads will return 4-bytes as APB reads are always words (PSTRB only used on writes)
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | RXDATA4 | Returns 4-bytes off receive data | RO | 0x0000 0000

### QSPIXIP : X4TRANSMITDATA

Address offset | 0x04C
Physical address | 0x0702 014C | Instance | QSPIXIP
Description | Allows the processor to write 4-bytes from the SPI FIFO in a single transaction. Writes to this register must use word operations i.e. write 4-bytes at a time.
Type | WO

Bits | Field Name | Description | Type | Reset
31:0 | TXDATA4 | Writes 4-bytes of data to send; | WO | 0x0000 0000

### QSPIXIP : FRAMESUP

Address offset | 0x050
Physical address | 0x0702 0150 | Instance | QSPIXIP
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | BYTESUPPER |  | RW | 0x0000
15:0 | BYTESLOWER | W: NO operation R: Return the lower 16 - bits of the byte count from the FRAMES register | RW | 0x0000

QSPIXIP has no common memories.