## DDR_CSR_APB

This section provides information on the DDR_CSR_APB Module Instance. Each of the module registers is described below.

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## DDR_CSR_APB Register Mapping Summary

### DDRCFG Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CFG_MANUAL_ADDRESS_MAP | RW | 32 | 0x0000 0000 | 0x0 2400 | 0x2008 2400
CFG_CHIPADDR_MAP | RW | 32 | 0x0000 0000 | 0x0 2404 | 0x2008 2404
CFG_CIDADDR_MAP | RW | 32 | 0x0000 0000 | 0x0 2408 | 0x2008 2408
CFG_MB_AUTOPCH_COL_BIT_POS_LOW | RW | 32 | 0x0000 0004 | 0x0 240C | 0x2008 240C
CFG_MB_AUTOPCH_COL_BIT_POS_HIGH | RW | 32 | 0x0000 000A | 0x0 2410 | 0x2008 2410
CFG_BANKADDR_MAP_0 | RW | 32 | 0x0000 0000 | 0x0 2414 | 0x2008 2414
CFG_BANKADDR_MAP_1 | RW | 32 | 0x0000 0000 | 0x0 2418 | 0x2008 2418
CFG_ROWADDR_MAP_0 | RW | 32 | 0x0000 0000 | 0x0 241C | 0x2008 241C
CFG_ROWADDR_MAP_1 | RW | 32 | 0x0000 0000 | 0x0 2420 | 0x2008 2420
CFG_ROWADDR_MAP_2 | RW | 32 | 0x0000 0000 | 0x0 2424 | 0x2008 2424
CFG_ROWADDR_MAP_3 | RW | 32 | 0x0000 0000 | 0x0 2428 | 0x2008 2428
CFG_COLADDR_MAP_0 | RW | 32 | 0x0000 0000 | 0x0 242C | 0x2008 242C
CFG_COLADDR_MAP_1 | RW | 32 | 0x0000 0000 | 0x0 2430 | 0x2008 2430
CFG_COLADDR_MAP_2 | RW | 32 | 0x0000 0000 | 0x0 2434 | 0x2008 2434
CFG_VRCG_ENABLE | RW | 32 | 0x0000 0140 | 0x0 2800 | 0x2008 2800
CFG_VRCG_DISABLE | RW | 32 | 0x0000 00A0 | 0x0 2804 | 0x2008 2804
CFG_WRITE_LATENCY_SET | RW | 32 | 0x0000 0000 | 0x0 2808 | 0x2008 2808
CFG_THERMAL_OFFSET | RW | 32 | 0x0000 0000 | 0x0 280C | 0x2008 280C
CFG_SOC_ODT | RW | 32 | 0x0000 0000 | 0x0 2810 | 0x2008 2810
CFG_ODTE_CK | RW | 32 | 0x0000 0000 | 0x0 2814 | 0x2008 2814
CFG_ODTE_CS | RW | 32 | 0x0000 0000 | 0x0 2818 | 0x2008 2818
CFG_ODTD_CA | RW | 32 | 0x0000 0000 | 0x0 281C | 0x2008 281C
CFG_LPDDR4_FSP_OP | RW | 32 | 0x0000 0000 | 0x0 2820 | 0x2008 2820
CFG_GENERATE_REFRESH_ON_SRX | RW | 32 | 0x0000 0001 | 0x0 2824 | 0x2008 2824
CFG_DBI_CL | RW | 32 | 0x0000 0016 | 0x0 2828 | 0x2008 2828
CFG_NON_DBI_CL | RW | 32 | 0x0000 0016 | 0x0 282C | 0x2008 282C
INIT_FORCE_WRITE_DATA_0 | RW | 32 | 0x0000 0000 | 0x0 2830 | 0x2008 2830
CFG_WRITE_CRC | RW | 32 | 0x0000 0000 | 0x0 3C00 | 0x2008 3C00
CFG_MPR_READ_FORMAT | RW | 32 | 0x0000 0000 | 0x0 3C04 | 0x2008 3C04
CFG_WR_CMD_LAT_CRC_DM | RW | 32 | 0x0000 0000 | 0x0 3C08 | 0x2008 3C08
CFG_FINE_GRAN_REF_MODE | RW | 32 | 0x0000 0000 | 0x0 3C0C | 0x2008 3C0C
CFG_TEMP_SENSOR_READOUT | RW | 32 | 0x0000 0000 | 0x0 3C10 | 0x2008 3C10
CFG_PER_DRAM_ADDR_EN | RW | 32 | 0x0000 0000 | 0x0 3C14 | 0x2008 3C14
CFG_GEARDOWN_MODE | RW | 32 | 0x0000 0000 | 0x0 3C18 | 0x2008 3C18
CFG_WR_PREAMBLE | RW | 32 | 0x0000 0000 | 0x0 3C1C | 0x2008 3C1C
CFG_RD_PREAMBLE | RW | 32 | 0x0000 0000 | 0x0 3C20 | 0x2008 3C20
CFG_RD_PREAMB_TRN_MODE | RW | 32 | 0x0000 0000 | 0x0 3C24 | 0x2008 3C24
CFG_SR_ABORT | RW | 32 | 0x0000 0000 | 0x0 3C28 | 0x2008 3C28
CFG_CS_TO_CMDADDR_LATENCY | RW | 32 | 0x0000 0000 | 0x0 3C2C | 0x2008 3C2C
CFG_INT_VREF_MON | RW | 32 | 0x0000 0000 | 0x0 3C30 | 0x2008 3C30
CFG_TEMP_CTRL_REF_MODE | RW | 32 | 0x0000 0000 | 0x0 3C34 | 0x2008 3C34
CFG_TEMP_CTRL_REF_RANGE | RW | 32 | 0x0000 0000 | 0x0 3C38 | 0x2008 3C38
CFG_MAX_PWR_DOWN_MODE | RW | 32 | 0x0000 0000 | 0x0 3C3C | 0x2008 3C3C
CFG_READ_DBI | RW | 32 | 0x0000 0000 | 0x0 3C40 | 0x2008 3C40
CFG_WRITE_DBI | RW | 32 | 0x0000 0000 | 0x0 3C44 | 0x2008 3C44
CFG_DATA_MASK | RW | 32 | 0x0000 0001 | 0x0 3C48 | 0x2008 3C48
CFG_CA_PARITY_PERSIST_ERR | RW | 32 | 0x0000 0000 | 0x0 3C4C | 0x2008 3C4C
CFG_RTT_PARK | RW | 32 | 0x0000 0000 | 0x0 3C50 | 0x2008 3C50
CFG_ODT_INBUF_4_PD | RW | 32 | 0x0000 0000 | 0x0 3C54 | 0x2008 3C54
CFG_CA_PARITY_ERR_STATUS | RW | 32 | 0x0000 0000 | 0x0 3C58 | 0x2008 3C58
CFG_CRC_ERROR_CLEAR | RW | 32 | 0x0000 0000 | 0x0 3C5C | 0x2008 3C5C
CFG_CA_PARITY_LATENCY | RW | 32 | 0x0000 0000 | 0x0 3C60 | 0x2008 3C60
CFG_CCD_S | RW | 32 | 0x0000 0000 | 0x0 3C64 | 0x2008 3C64
CFG_CCD_L | RW | 32 | 0x0000 0000 | 0x0 3C68 | 0x2008 3C68
CFG_VREFDQ_TRN_ENABLE | RW | 32 | 0x0000 0000 | 0x0 3C6C | 0x2008 3C6C
CFG_VREFDQ_TRN_RANGE | RW | 32 | 0x0000 0000 | 0x0 3C70 | 0x2008 3C70
CFG_VREFDQ_TRN_VALUE | RW | 32 | 0x0000 0000 | 0x0 3C74 | 0x2008 3C74
CFG_RRD_S | RW | 32 | 0x0000 0003 | 0x0 3C78 | 0x2008 3C78
CFG_RRD_L | RW | 32 | 0x0000 0003 | 0x0 3C7C | 0x2008 3C7C
CFG_WTR_S | RW | 32 | 0x0000 0002 | 0x0 3C80 | 0x2008 3C80
CFG_WTR_L | RW | 32 | 0x0000 0002 | 0x0 3C84 | 0x2008 3C84
CFG_WTR_S_CRC_DM | RW | 32 | 0x0000 0002 | 0x0 3C88 | 0x2008 3C88
CFG_WTR_L_CRC_DM | RW | 32 | 0x0000 0002 | 0x0 3C8C | 0x2008 3C8C
CFG_WR_CRC_DM | RW | 32 | 0x0000 0004 | 0x0 3C90 | 0x2008 3C90
CFG_RFC1 | RW | 32 | 0x0000 0022 | 0x0 3C94 | 0x2008 3C94
CFG_RFC2 | RW | 32 | 0x0000 0022 | 0x0 3C98 | 0x2008 3C98
CFG_RFC4 | RW | 32 | 0x0000 0022 | 0x0 3C9C | 0x2008 3C9C
CFG_NIBBLE_DEVICES | RW | 32 | 0x0000 0000 | 0x0 3CC4 | 0x2008 3CC4
CFG_BIT_MAP_INDEX_CS0_0 | RW | 32 | 0x0000 0000 | 0x0 3CE0 | 0x2008 3CE0
CFG_BIT_MAP_INDEX_CS0_1 | RW | 32 | 0x0000 0000 | 0x0 3CE4 | 0x2008 3CE4
CFG_BIT_MAP_INDEX_CS1_0 | RW | 32 | 0x0000 0000 | 0x0 3CE8 | 0x2008 3CE8
CFG_BIT_MAP_INDEX_CS1_1 | RW | 32 | 0x0000 0000 | 0x0 3CEC | 0x2008 3CEC
CFG_BIT_MAP_INDEX_CS2_0 | RW | 32 | 0x0000 0000 | 0x0 3CF0 | 0x2008 3CF0
CFG_BIT_MAP_INDEX_CS2_1 | RW | 32 | 0x0000 0000 | 0x0 3CF4 | 0x2008 3CF4
CFG_BIT_MAP_INDEX_CS3_0 | RW | 32 | 0x0000 0000 | 0x0 3CF8 | 0x2008 3CF8
CFG_BIT_MAP_INDEX_CS3_1 | RW | 32 | 0x0000 0000 | 0x0 3CFC | 0x2008 3CFC
CFG_BIT_MAP_INDEX_CS4_0 | RW | 32 | 0x0000 0000 | 0x0 3D00 | 0x2008 3D00
CFG_BIT_MAP_INDEX_CS4_1 | RW | 32 | 0x0000 0000 | 0x0 3D04 | 0x2008 3D04
CFG_BIT_MAP_INDEX_CS5_0 | RW | 32 | 0x0000 0000 | 0x0 3D08 | 0x2008 3D08
CFG_BIT_MAP_INDEX_CS5_1 | RW | 32 | 0x0000 0000 | 0x0 3D0C | 0x2008 3D0C
CFG_BIT_MAP_INDEX_CS6_0 | RW | 32 | 0x0000 0000 | 0x0 3D10 | 0x2008 3D10
CFG_BIT_MAP_INDEX_CS6_1 | RW | 32 | 0x0000 0000 | 0x0 3D14 | 0x2008 3D14
CFG_BIT_MAP_INDEX_CS7_0 | RW | 32 | 0x0000 0000 | 0x0 3D18 | 0x2008 3D18
CFG_BIT_MAP_INDEX_CS7_1 | RW | 32 | 0x0000 0000 | 0x0 3D1C | 0x2008 3D1C
CFG_BIT_MAP_INDEX_CS8_0 | RW | 32 | 0x0000 0000 | 0x0 3D20 | 0x2008 3D20
CFG_BIT_MAP_INDEX_CS8_1 | RW | 32 | 0x0000 0000 | 0x0 3D24 | 0x2008 3D24
CFG_BIT_MAP_INDEX_CS9_0 | RW | 32 | 0x0000 0000 | 0x0 3D28 | 0x2008 3D28
CFG_BIT_MAP_INDEX_CS9_1 | RW | 32 | 0x0000 0000 | 0x0 3D2C | 0x2008 3D2C
CFG_BIT_MAP_INDEX_CS10_0 | RW | 32 | 0x0000 0000 | 0x0 3D30 | 0x2008 3D30
CFG_BIT_MAP_INDEX_CS10_1 | RW | 32 | 0x0000 0000 | 0x0 3D34 | 0x2008 3D34
CFG_BIT_MAP_INDEX_CS11_0 | RW | 32 | 0x0000 0000 | 0x0 3D38 | 0x2008 3D38
CFG_BIT_MAP_INDEX_CS11_1 | RW | 32 | 0x0000 0000 | 0x0 3D3C | 0x2008 3D3C
CFG_BIT_MAP_INDEX_CS12_0 | RW | 32 | 0x0000 0000 | 0x0 3D40 | 0x2008 3D40
CFG_BIT_MAP_INDEX_CS12_1 | RW | 32 | 0x0000 0000 | 0x0 3D44 | 0x2008 3D44
CFG_BIT_MAP_INDEX_CS13_0 | RW | 32 | 0x0000 0000 | 0x0 3D48 | 0x2008 3D48
CFG_BIT_MAP_INDEX_CS13_1 | RW | 32 | 0x0000 0000 | 0x0 3D4C | 0x2008 3D4C
CFG_BIT_MAP_INDEX_CS14_0 | RW | 32 | 0x0000 0000 | 0x0 3D50 | 0x2008 3D50
CFG_BIT_MAP_INDEX_CS14_1 | RW | 32 | 0x0000 0000 | 0x0 3D54 | 0x2008 3D54
CFG_BIT_MAP_INDEX_CS15_0 | RW | 32 | 0x0000 0000 | 0x0 3D58 | 0x2008 3D58
CFG_BIT_MAP_INDEX_CS15_1 | RW | 32 | 0x0000 0000 | 0x0 3D5C | 0x2008 3D5C
CFG_NUM_LOGICAL_RANKS_PER_3DS | RW | 32 | 0x0000 0000 | 0x0 3D60 | 0x2008 3D60
CFG_RFC_DLR1 | RW | 32 | 0x0000 0048 | 0x0 3D64 | 0x2008 3D64
CFG_RFC_DLR2 | RW | 32 | 0x0000 002C | 0x0 3D68 | 0x2008 3D68
CFG_RFC_DLR4 | RW | 32 | 0x0000 0020 | 0x0 3D6C | 0x2008 3D6C
CFG_RRD_DLR | RW | 32 | 0x0000 0004 | 0x0 3D70 | 0x2008 3D70
CFG_FAW_DLR | RW | 32 | 0x0000 0010 | 0x0 3D74 | 0x2008 3D74
CFG_ADVANCE_ACTIVATE_READY | RW | 32 | 0x0000 0000 | 0x0 3D98 | 0x2008 3D98
CTRLR_SOFT_RESET_N | RW | 32 | 0x0000 0000 | 0x0 4000 | 0x2008 4000
CFG_LOOKAHEAD_PCH | RW | 32 | 0x0000 0001 | 0x0 4008 | 0x2008 4008
CFG_LOOKAHEAD_ACT | RW | 32 | 0x0000 0001 | 0x0 400C | 0x2008 400C
INIT_AUTOINIT_DISABLE | RW | 32 | 0x0000 0000 | 0x0 4010 | 0x2008 4010
INIT_FORCE_RESET | RW | 32 | 0x0000 0000 | 0x0 4014 | 0x2008 4014
INIT_GEARDOWN_EN | RW | 32 | 0x0000 0000 | 0x0 4018 | 0x2008 4018
INIT_DISABLE_CKE | RW | 32 | 0x0000 0000 | 0x0 401C | 0x2008 401C
INIT_CS | RW | 32 | 0x0000 0000 | 0x0 4020 | 0x2008 4020
INIT_PRECHARGE_ALL | RW | 32 | 0x0000 0000 | 0x0 4024 | 0x2008 4024
INIT_REFRESH | RW | 32 | 0x0000 0000 | 0x0 4028 | 0x2008 4028
INIT_ZQ_CAL_REQ | RW | 32 | 0x0000 0000 | 0x0 402C | 0x2008 402C
INIT_ACK | RO | 32 | 0x0000 0000 | 0x0 4030 | 0x2008 4030
CFG_BL | RW | 32 | 0x0000 0000 | 0x0 4034 | 0x2008 4034
CTRLR_INIT | RW | 32 | 0x0000 0000 | 0x0 4038 | 0x2008 4038
CTRLR_INIT_DONE | RO | 32 | 0x0000 0000 | 0x0 403C | 0x2008 403C
CFG_AUTO_REF_EN | RW | 32 | 0x0000 0001 | 0x0 4040 | 0x2008 4040
CFG_RAS | RW | 32 | 0x0000 001C | 0x0 4044 | 0x2008 4044
CFG_RCD | RW | 32 | 0x0000 000B | 0x0 4048 | 0x2008 4048
CFG_RRD | RW | 32 | 0x0000 0005 | 0x0 404C | 0x2008 404C
CFG_RP | RW | 32 | 0x0000 000B | 0x0 4050 | 0x2008 4050
CFG_RC | RW | 32 | 0x0000 0027 | 0x0 4054 | 0x2008 4054
CFG_FAW | RW | 32 | 0x0000 0018 | 0x0 4058 | 0x2008 4058
CFG_RFC | RW | 32 | 0x0000 0118 | 0x0 405C | 0x2008 405C
CFG_RTP | RW | 32 | 0x0000 0006 | 0x0 4060 | 0x2008 4060
CFG_WR | RW | 32 | 0x0000 000C | 0x0 4064 | 0x2008 4064
CFG_WTR | RW | 32 | 0x0000 0006 | 0x0 4068 | 0x2008 4068
CFG_PASR | RW | 32 | 0x0000 0000 | 0x0 4070 | 0x2008 4070
CFG_XP | RW | 32 | 0x0000 0002 | 0x0 4074 | 0x2008 4074
CFG_XSR | RW | 32 | 0x0000 0002 | 0x0 4078 | 0x2008 4078
CFG_CL | RW | 32 | 0x0000 000B | 0x0 4080 | 0x2008 4080
CFG_READ_TO_WRITE | RW | 32 | 0x0000 0002 | 0x0 4088 | 0x2008 4088
CFG_WRITE_TO_WRITE | RW | 32 | 0x0000 0003 | 0x0 408C | 0x2008 408C
CFG_READ_TO_READ | RW | 32 | 0x0000 0003 | 0x0 4090 | 0x2008 4090
CFG_WRITE_TO_READ | RW | 32 | 0x0000 0002 | 0x0 4094 | 0x2008 4094
CFG_READ_TO_WRITE_ODT | RW | 32 | 0x0000 0002 | 0x0 4098 | 0x2008 4098
CFG_WRITE_TO_WRITE_ODT | RW | 32 | 0x0000 0003 | 0x0 409C | 0x2008 409C
CFG_READ_TO_READ_ODT | RW | 32 | 0x0000 0003 | 0x0 40A0 | 0x2008 40A0
CFG_WRITE_TO_READ_ODT | RW | 32 | 0x0000 0002 | 0x0 40A4 | 0x2008 40A4
CFG_MIN_READ_IDLE | RW | 32 | 0x0000 0000 | 0x0 40A8 | 0x2008 40A8
CFG_MRD | RW | 32 | 0x0000 000C | 0x0 40AC | 0x2008 40AC
CFG_BT | RW | 32 | 0x0000 0000 | 0x0 40B0 | 0x2008 40B0
CFG_DS | RW | 32 | 0x0000 0000 | 0x0 40B4 | 0x2008 40B4
CFG_QOFF | RW | 32 | 0x0000 0000 | 0x0 40B8 | 0x2008 40B8
CFG_RTT | RW | 32 | 0x0000 0001 | 0x0 40C4 | 0x2008 40C4
CFG_DLL_DISABLE | RW | 32 | 0x0000 0000 | 0x0 40C8 | 0x2008 40C8
CFG_REF_PER | RW | 32 | 0x0000 1860 | 0x0 40CC | 0x2008 40CC
CFG_STARTUP_DELAY | RW | 32 | 0x0002 7100 | 0x0 40D0 | 0x2008 40D0
CFG_MEM_COLBITS | RW | 32 | 0x0000 000B | 0x0 40D4 | 0x2008 40D4
CFG_MEM_ROWBITS | RW | 32 | 0x0000 0010 | 0x0 40D8 | 0x2008 40D8
CFG_MEM_BANKBITS | RW | 32 | 0x0000 0003 | 0x0 40DC | 0x2008 40DC
CFG_ODT_RD_MAP_CS0 | RW | 32 | 0x0000 0002 | 0x0 40E0 | 0x2008 40E0
CFG_ODT_RD_MAP_CS1 | RW | 32 | 0x0000 0001 | 0x0 40E4 | 0x2008 40E4
CFG_ODT_RD_MAP_CS2 | RW | 32 | 0x0000 0008 | 0x0 40E8 | 0x2008 40E8
CFG_ODT_RD_MAP_CS3 | RW | 32 | 0x0000 0004 | 0x0 40EC | 0x2008 40EC
CFG_ODT_RD_MAP_CS4 | RW | 32 | 0x0000 0020 | 0x0 40F0 | 0x2008 40F0
CFG_ODT_RD_MAP_CS5 | RW | 32 | 0x0000 0010 | 0x0 40F4 | 0x2008 40F4
CFG_ODT_RD_MAP_CS6 | RW | 32 | 0x0000 0080 | 0x0 40F8 | 0x2008 40F8
CFG_ODT_RD_MAP_CS7 | RW | 32 | 0x0000 0040 | 0x0 40FC | 0x2008 40FC
CFG_ODT_WR_MAP_CS0 | RW | 32 | 0x0000 0001 | 0x0 4120 | 0x2008 4120
CFG_ODT_WR_MAP_CS1 | RW | 32 | 0x0000 0002 | 0x0 4124 | 0x2008 4124
CFG_ODT_WR_MAP_CS2 | RW | 32 | 0x0000 0004 | 0x0 4128 | 0x2008 4128
CFG_ODT_WR_MAP_CS3 | RW | 32 | 0x0000 0008 | 0x0 412C | 0x2008 412C
CFG_ODT_WR_MAP_CS4 | RW | 32 | 0x0000 0010 | 0x0 4130 | 0x2008 4130
CFG_ODT_WR_MAP_CS5 | RW | 32 | 0x0000 0020 | 0x0 4134 | 0x2008 4134
CFG_ODT_WR_MAP_CS6 | RW | 32 | 0x0000 0040 | 0x0 4138 | 0x2008 4138
CFG_ODT_WR_MAP_CS7 | RW | 32 | 0x0000 0080 | 0x0 413C | 0x2008 413C
CFG_ODT_RD_TURN_ON | RW | 32 | 0x0000 0000 | 0x0 4160 | 0x2008 4160
CFG_ODT_WR_TURN_ON | RW | 32 | 0x0000 0000 | 0x0 4164 | 0x2008 4164
CFG_ODT_RD_TURN_OFF | RW | 32 | 0x0000 0000 | 0x0 4168 | 0x2008 4168
CFG_ODT_WR_TURN_OFF | RW | 32 | 0x0000 0000 | 0x0 416C | 0x2008 416C
CFG_EMR3 | RW | 32 | 0x0000 0000 | 0x0 4178 | 0x2008 4178
CFG_TWO_T | RW | 32 | 0x0000 0000 | 0x0 417C | 0x2008 417C
CFG_TWO_T_SEL_CYCLE | RW | 32 | 0x0000 0000 | 0x0 4180 | 0x2008 4180
CFG_REGDIMM | RW | 32 | 0x0000 0000 | 0x0 4184 | 0x2008 4184
CFG_MOD | RW | 32 | 0x0000 000C | 0x0 4188 | 0x2008 4188
CFG_XS | RW | 32 | 0x0000 0120 | 0x0 418C | 0x2008 418C
CFG_XSDLL | RW | 32 | 0x0000 0200 | 0x0 4190 | 0x2008 4190
CFG_XPR | RW | 32 | 0x0000 0120 | 0x0 4194 | 0x2008 4194
CFG_AL_MODE | RW | 32 | 0x0000 0000 | 0x0 4198 | 0x2008 4198
CFG_CWL | RW | 32 | 0x0000 0008 | 0x0 419C | 0x2008 419C
CFG_BL_MODE | RW | 32 | 0x0000 0000 | 0x0 41A0 | 0x2008 41A0
CFG_TDQS | RW | 32 | 0x0000 0000 | 0x0 41A4 | 0x2008 41A4
CFG_RTT_WR | RW | 32 | 0x0000 0000 | 0x0 41A8 | 0x2008 41A8
CFG_LP_ASR | RW | 32 | 0x0000 0000 | 0x0 41AC | 0x2008 41AC
CFG_AUTO_SR | RW | 32 | 0x0000 0000 | 0x0 41B0 | 0x2008 41B0
CFG_SRT | RW | 32 | 0x0000 0000 | 0x0 41B4 | 0x2008 41B4
CFG_ADDR_MIRROR | RW | 32 | 0x0000 0000 | 0x0 41B8 | 0x2008 41B8
CFG_ZQ_CAL_TYPE | RW | 32 | 0x0000 0000 | 0x0 41BC | 0x2008 41BC
CFG_ZQ_CAL_PER | RW | 32 | 0x0000 3F40 | 0x0 41C0 | 0x2008 41C0
CFG_AUTO_ZQ_CAL_EN | RW | 32 | 0x0000 0001 | 0x0 41C4 | 0x2008 41C4
CFG_MEMORY_TYPE | RW | 32 | 0x0000 0008 | 0x0 41C8 | 0x2008 41C8
CFG_ONLY_SRANK_CMDS | RW | 32 | 0x0000 0000 | 0x0 41CC | 0x2008 41CC
CFG_NUM_RANKS | RW | 32 | 0x0000 0002 | 0x0 41D0 | 0x2008 41D0
CFG_QUAD_RANK | RW | 32 | 0x0000 0000 | 0x0 41D4 | 0x2008 41D4
CFG_EARLY_RANK_TO_WR_START | RW | 32 | 0x0000 0000 | 0x0 41DC | 0x2008 41DC
CFG_EARLY_RANK_TO_RD_START | RW | 32 | 0x0000 0000 | 0x0 41E0 | 0x2008 41E0
CFG_PASR_BANK | RW | 32 | 0x0000 0000 | 0x0 41E4 | 0x2008 41E4
CFG_PASR_SEG | RW | 32 | 0x0000 0000 | 0x0 41E8 | 0x2008 41E8
INIT_MRR_MODE | RW | 32 | 0x0000 0000 | 0x0 41EC | 0x2008 41EC
INIT_MR_W_REQ | RW | 32 | 0x0000 0000 | 0x0 41F0 | 0x2008 41F0
INIT_MR_ADDR | RW | 32 | 0x0000 0000 | 0x0 41F4 | 0x2008 41F4
INIT_MR_WR_DATA | RW | 32 | 0x0000 0000 | 0x0 41F8 | 0x2008 41F8
INIT_MR_WR_MASK | RW | 32 | 0x0000 0000 | 0x0 41FC | 0x2008 41FC
INIT_NOP | RW | 32 | 0x0000 0000 | 0x0 4200 | 0x2008 4200
CFG_INIT_DURATION | RW | 32 | 0x0000 29B0 | 0x0 4204 | 0x2008 4204
CFG_ZQINIT_CAL_DURATION | RW | 32 | 0x0000 0200 | 0x0 4208 | 0x2008 4208
CFG_ZQ_CAL_L_DURATION | RW | 32 | 0x0000 0100 | 0x0 420C | 0x2008 420C
CFG_ZQ_CAL_S_DURATION | RW | 32 | 0x0000 0040 | 0x0 4210 | 0x2008 4210
CFG_ZQ_CAL_R_DURATION | RW | 32 | 0x0000 0035 | 0x0 4214 | 0x2008 4214
CFG_MRR | RW | 32 | 0x0000 0002 | 0x0 4218 | 0x2008 4218
CFG_MRW | RW | 32 | 0x0000 000C | 0x0 421C | 0x2008 421C
CFG_ODT_POWERDOWN | RW | 32 | 0x0000 0000 | 0x0 4220 | 0x2008 4220
CFG_WL | RW | 32 | 0x0000 0008 | 0x0 4224 | 0x2008 4224
CFG_RL | RW | 32 | 0x0000 000B | 0x0 4228 | 0x2008 4228
CFG_CAL_READ_PERIOD | RW | 32 | 0x0000 0000 | 0x0 422C | 0x2008 422C
CFG_NUM_CAL_READS | RW | 32 | 0x0000 0000 | 0x0 4230 | 0x2008 4230
INIT_SELF_REFRESH | RW | 32 | 0x0000 0000 | 0x0 4234 | 0x2008 4234
INIT_SELF_REFRESH_STATUS | RO | 32 | 0x0000 0000 | 0x0 4238 | 0x2008 4238
INIT_POWER_DOWN | RW | 32 | 0x0000 0000 | 0x0 423C | 0x2008 423C
INIT_POWER_DOWN_STATUS | RO | 32 | 0x0000 0000 | 0x0 4240 | 0x2008 4240
INIT_FORCE_WRITE | RW | 32 | 0x0000 0000 | 0x0 4244 | 0x2008 4244
INIT_FORCE_WRITE_CS | RW | 32 | 0x0000 0000 | 0x0 4248 | 0x2008 4248
CFG_CTRLR_INIT_DISABLE | RW | 32 | 0x0000 0000 | 0x0 424C | 0x2008 424C
CTRLR_READY | RO | 32 | 0x0000 0000 | 0x0 4250 | 0x2008 4250
INIT_RDIMM_READY | RO | 32 | 0x0000 0000 | 0x0 4254 | 0x2008 4254
INIT_RDIMM_COMPLETE | RW | 32 | 0x0000 0000 | 0x0 4258 | 0x2008 4258
CFG_RDIMM_LAT | RW | 32 | 0x0000 0000 | 0x0 425C | 0x2008 425C
CFG_RDIMM_BSIDE_INVERT | RW | 32 | 0x0000 0001 | 0x0 4260 | 0x2008 4260
CFG_LRDIMM | RW | 32 | 0x0000 0000 | 0x0 4264 | 0x2008 4264
INIT_MEMORY_RESET_MASK | RW | 32 | 0x0000 0000 | 0x0 4268 | 0x2008 4268
CFG_RD_PREAMB_TOGGLE | RW | 32 | 0x0000 0000 | 0x0 426C | 0x2008 426C
CFG_RD_POSTAMBLE | RW | 32 | 0x0000 0000 | 0x0 4270 | 0x2008 4270
CFG_PU_CAL | RW | 32 | 0x0000 0000 | 0x0 4274 | 0x2008 4274
CFG_DQ_ODT | RW | 32 | 0x0000 0000 | 0x0 4278 | 0x2008 4278
CFG_CA_ODT | RW | 32 | 0x0000 0000 | 0x0 427C | 0x2008 427C
CFG_ZQLATCH_DURATION | RW | 32 | 0x0000 0030 | 0x0 4280 | 0x2008 4280
INIT_CAL_SELECT | RW | 32 | 0x0000 0000 | 0x0 4284 | 0x2008 4284
INIT_CAL_L_R_REQ | RW | 32 | 0x0000 0000 | 0x0 4288 | 0x2008 4288
INIT_CAL_L_B_SIZE | RW | 32 | 0x0000 0000 | 0x0 428C | 0x2008 428C
INIT_CAL_L_R_ACK | RO | 32 | 0x0000 0000 | 0x0 4290 | 0x2008 4290
INIT_CAL_L_READ_COMPLETE | RO | 32 | 0x0000 0000 | 0x0 4294 | 0x2008 4294
INIT_RWFIFO | RW | 32 | 0x0000 0000 | 0x0 42A0 | 0x2008 42A0
INIT_RD_DQCAL | RW | 32 | 0x0000 0000 | 0x0 42A4 | 0x2008 42A4
INIT_START_DQSOSC | RW | 32 | 0x0000 0000 | 0x0 42A8 | 0x2008 42A8
INIT_STOP_DQSOSC | RW | 32 | 0x0000 0000 | 0x0 42AC | 0x2008 42AC
INIT_ZQ_CAL_START | RW | 32 | 0x0000 0000 | 0x0 42B0 | 0x2008 42B0
CFG_WR_POSTAMBLE | RW | 32 | 0x0000 0000 | 0x0 42B4 | 0x2008 42B4
INIT_CAL_L_ADDR_0 | RW | 32 | 0x0000 0000 | 0x0 42BC | 0x2008 42BC
INIT_CAL_L_ADDR_1 | RW | 32 | 0x0000 0000 | 0x0 42C0 | 0x2008 42C0
CFG_CTRLUPD_TRIG | RW | 32 | 0x0000 0001 | 0x0 42C4 | 0x2008 42C4
CFG_CTRLUPD_START_DELAY | RW | 32 | 0x0000 0016 | 0x0 42C8 | 0x2008 42C8
CFG_DFI_T_CTRLUPD_MAX | RW | 32 | 0x0000 00C8 | 0x0 42CC | 0x2008 42CC
CFG_CTRLR_BUSY_SEL | RW | 32 | 0x0000 0000 | 0x0 42D0 | 0x2008 42D0
CFG_CTRLR_BUSY_VALUE | RW | 32 | 0x0000 0000 | 0x0 42D4 | 0x2008 42D4
CFG_CTRLR_BUSY_TURN_OFF_DELAY | RW | 32 | 0x0000 0000 | 0x0 42D8 | 0x2008 42D8
CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW | RW | 32 | 0x0000 0000 | 0x0 42DC | 0x2008 42DC
CFG_CTRLR_BUSY_RESTART_HOLDOFF | RW | 32 | 0x0000 0000 | 0x0 42E0 | 0x2008 42E0
CFG_PARITY_RDIMM_DELAY | RW | 32 | 0x0000 0001 | 0x0 42E4 | 0x2008 42E4
CFG_CTRLR_BUSY_ENABLE | RW | 32 | 0x0000 0000 | 0x0 42E8 | 0x2008 42E8
CFG_ASYNC_ODT | RW | 32 | 0x0000 0000 | 0x0 42EC | 0x2008 42EC
CFG_ZQ_CAL_DURATION | RW | 32 | 0x0000 0640 | 0x0 42F0 | 0x2008 42F0
CFG_MRRI | RW | 32 | 0x0000 0000 | 0x0 42F4 | 0x2008 42F4
INIT_ODT_FORCE_EN | RW | 32 | 0x0000 0000 | 0x0 42F8 | 0x2008 42F8
INIT_ODT_FORCE_RANK | RW | 32 | 0x0000 0000 | 0x0 42FC | 0x2008 42FC
CFG_PHYUPD_ACK_DELAY | RW | 32 | 0x0000 0000 | 0x0 4300 | 0x2008 4300
CFG_MIRROR_X16_BG0_BG1 | RW | 32 | 0x0000 0000 | 0x0 4304 | 0x2008 4304
INIT_PDA_MR_W_REQ | RW | 32 | 0x0000 0000 | 0x0 4308 | 0x2008 4308
INIT_PDA_NIBBLE_SELECT | RW | 32 | 0x0000 0000 | 0x0 430C | 0x2008 430C
CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH | RW | 32 | 0x0000 0000 | 0x0 4310 | 0x2008 4310
CFG_CKSRE | RW | 32 | 0x0000 0008 | 0x0 4314 | 0x2008 4314
CFG_CKSRX | RW | 32 | 0x0000 0008 | 0x0 4318 | 0x2008 4318
CFG_RCD_STAB | RW | 32 | 0x0000 0000 | 0x0 431C | 0x2008 431C
CFG_DFI_T_CTRL_DELAY | RW | 32 | 0x0000 0000 | 0x0 4320 | 0x2008 4320
CFG_DFI_T_DRAM_CLK_ENABLE | RW | 32 | 0x0000 0000 | 0x0 4324 | 0x2008 4324
CFG_IDLE_TIME_TO_SELF_REFRESH | RW | 32 | 0x0000 0000 | 0x0 4328 | 0x2008 4328
CFG_IDLE_TIME_TO_POWER_DOWN | RW | 32 | 0x0000 0000 | 0x0 432C | 0x2008 432C
CFG_BURST_RW_REFRESH_HOLDOFF | RW | 32 | 0x0000 0000 | 0x0 4330 | 0x2008 4330
INIT_REFRESH_COUNT | RO | 32 | 0x0000 0000 | 0x0 4334 | 0x2008 4334
CFG_BG_INTERLEAVE | RW | 32 | 0x0000 0001 | 0x0 4384 | 0x2008 4384
CFG_REFRESH_DURING_PHY_TRAINING | RW | 32 | 0x0000 0000 | 0x0 43FC | 0x2008 43FC
MT_EN | RW | 32 | 0x0000 0000 | 0x0 4400 | 0x2008 4400
MT_EN_SINGLE | RW | 32 | 0x0000 0000 | 0x0 4404 | 0x2008 4404
MT_STOP_ON_ERROR | RW | 32 | 0x0000 0000 | 0x0 4408 | 0x2008 4408
MT_RD_ONLY | RW | 32 | 0x0000 0000 | 0x0 440C | 0x2008 440C
MT_WR_ONLY | RW | 32 | 0x0000 0000 | 0x0 4410 | 0x2008 4410
MT_DATA_PATTERN | RW | 32 | 0x0000 0000 | 0x0 4414 | 0x2008 4414
MT_ADDR_PATTERN | RW | 32 | 0x0000 0000 | 0x0 4418 | 0x2008 4418
MT_DATA_INVERT | RW | 32 | 0x0000 0000 | 0x0 441C | 0x2008 441C
MT_ADDR_BITS | RW | 32 | 0x0000 0008 | 0x0 4420 | 0x2008 4420
MT_ERROR_STS | RO | 32 | 0x0000 0000 | 0x0 4424 | 0x2008 4424
MT_DONE_ACK | RO | 32 | 0x0000 0000 | 0x0 4428 | 0x2008 4428
MT_START_ADDR_0 | RW | 32 | 0x0000 0000 | 0x0 44B4 | 0x2008 44B4
MT_START_ADDR_1 | RW | 32 | 0x0000 0000 | 0x0 44B8 | 0x2008 44B8
MT_ERROR_MASK_0 | RW | 32 | 0x0000 0000 | 0x0 44BC | 0x2008 44BC
MT_ERROR_MASK_1 | RW | 32 | 0x0000 0000 | 0x0 44C0 | 0x2008 44C0
MT_ERROR_MASK_2 | RW | 32 | 0x0000 0000 | 0x0 44C4 | 0x2008 44C4
MT_ERROR_MASK_3 | RW | 32 | 0x0000 0000 | 0x0 44C8 | 0x2008 44C8
MT_ERROR_MASK_4 | RW | 32 | 0x0000 0000 | 0x0 44CC | 0x2008 44CC
MT_USER_DATA_PATTERN | RW | 32 | 0x0000 0000 | 0x0 4670 | 0x2008 4670
MT_ALG_AUTO_PCH | RW | 32 | 0x0000 0000 | 0x0 467C | 0x2008 467C
CFG_STARVE_TIMEOUT_P0 | RW | 32 | 0x0000 0000 | 0x0 4C00 | 0x2008 4C00
CFG_STARVE_TIMEOUT_P1 | RW | 32 | 0x0000 0000 | 0x0 4C04 | 0x2008 4C04
CFG_STARVE_TIMEOUT_P2 | RW | 32 | 0x0000 0000 | 0x0 4C08 | 0x2008 4C08
CFG_STARVE_TIMEOUT_P3 | RW | 32 | 0x0000 0000 | 0x0 4C0C | 0x2008 4C0C
CFG_STARVE_TIMEOUT_P4 | RW | 32 | 0x0000 0000 | 0x0 4C10 | 0x2008 4C10
CFG_STARVE_TIMEOUT_P5 | RW | 32 | 0x0000 0000 | 0x0 4C14 | 0x2008 4C14
CFG_STARVE_TIMEOUT_P6 | RW | 32 | 0x0000 0000 | 0x0 4C18 | 0x2008 4C18
CFG_STARVE_TIMEOUT_P7 | RW | 32 | 0x0000 0000 | 0x0 4C1C | 0x2008 4C1C
CFG_REORDER_EN | RW | 32 | 0x0000 0001 | 0x0 5000 | 0x2008 5000
CFG_REORDER_QUEUE_EN | RW | 32 | 0x0000 0001 | 0x0 5004 | 0x2008 5004
CFG_INTRAPORT_REORDER_EN | RW | 32 | 0x0000 0001 | 0x0 5008 | 0x2008 5008
CFG_MAINTAIN_COHERENCY | RW | 32 | 0x0000 0001 | 0x0 500C | 0x2008 500C
CFG_Q_AGE_LIMIT | RW | 32 | 0x0000 00FF | 0x0 5010 | 0x2008 5010
CFG_RO_CLOSED_PAGE_POLICY | RW | 32 | 0x0000 0000 | 0x0 5018 | 0x2008 5018
CFG_REORDER_RW_ONLY | RW | 32 | 0x0000 0000 | 0x0 501C | 0x2008 501C
CFG_RO_PRIORITY_EN | RW | 32 | 0x0000 0000 | 0x0 5020 | 0x2008 5020
CFG_DM_EN | RW | 32 | 0x0000 0001 | 0x0 5400 | 0x2008 5400
CFG_RMW_EN | RW | 32 | 0x0000 0001 | 0x0 5404 | 0x2008 5404
CFG_ECC_CORRECTION_EN | RW | 32 | 0x0000 0001 | 0x0 5800 | 0x2008 5800
CFG_ECC_BYPASS | RW | 32 | 0x0000 0000 | 0x0 5840 | 0x2008 5840
INIT_WRITE_DATA_1B_ECC_ERROR_GEN | RW | 32 | 0x0000 0000 | 0x0 5844 | 0x2008 5844
INIT_WRITE_DATA_2B_ECC_ERROR_GEN | RW | 32 | 0x0000 0000 | 0x0 5848 | 0x2008 5848
CFG_ECC_1BIT_INT_THRESH | RW | 32 | 0x0000 0000 | 0x0 585C | 0x2008 585C
STAT_INT_ECC_1BIT_THRESH | RO | 32 | 0x0000 0000 | 0x0 5860 | 0x2008 5860
INIT_READ_CAPTURE_ADDR | RW | 32 | 0x0000 0000 | 0x0 5C00 | 0x2008 5C00
INIT_READ_CAPTURE_DATA_0 | RO | 32 | 0x0000 0000 | 0x0 5C04 | 0x2008 5C04
INIT_READ_CAPTURE_DATA_1 | RO | 32 | 0x0000 0000 | 0x0 5C08 | 0x2008 5C08
INIT_READ_CAPTURE_DATA_2 | RO | 32 | 0x0000 0000 | 0x0 5C0C | 0x2008 5C0C
INIT_READ_CAPTURE_DATA_3 | RO | 32 | 0x0000 0000 | 0x0 5C10 | 0x2008 5C10
INIT_READ_CAPTURE_DATA_4 | RO | 32 | 0x0000 0000 | 0x0 5C14 | 0x2008 5C14
CFG_ERROR_GROUP_SEL | RW | 32 | 0x0000 0000 | 0x0 6400 | 0x2008 6400
CFG_DATA_SEL | RW | 32 | 0x0000 0000 | 0x0 6404 | 0x2008 6404
CFG_TRIG_MODE | RW | 32 | 0x0000 0000 | 0x0 6408 | 0x2008 6408
CFG_POST_TRIG_CYCS | RW | 32 | 0x0000 0000 | 0x0 640C | 0x2008 640C
CFG_TRIG_MASK | RW | 32 | 0x0000 0000 | 0x0 6410 | 0x2008 6410
CFG_EN_MASK | RW | 32 | 0x0000 0000 | 0x0 6414 | 0x2008 6414
MTC_ACQ_ADDR | RW | 32 | 0x0000 0000 | 0x0 6418 | 0x2008 6418
MTC_ACQ_CYCS_STORED | RO | 32 | 0x0000 0000 | 0x0 641C | 0x2008 641C
MTC_ACQ_TRIG_DETECT | RO | 32 | 0x0000 0000 | 0x0 6420 | 0x2008 6420
MTC_ACQ_MEM_TRIG_ADDR | RO | 32 | 0x0000 0000 | 0x0 6424 | 0x2008 6424
MTC_ACQ_MEM_LAST_ADDR | RO | 32 | 0x0000 0000 | 0x0 6428 | 0x2008 6428
MTC_ACK | RO | 32 | 0x0000 0000 | 0x0 642C | 0x2008 642C
CFG_TRIG_MT_ADDR_0 | RW | 32 | 0x0000 0000 | 0x0 6430 | 0x2008 6430
CFG_TRIG_MT_ADDR_1 | RW | 32 | 0x0000 0000 | 0x0 6434 | 0x2008 6434
CFG_TRIG_ERR_MASK_0 | RW | 32 | 0x0000 0000 | 0x0 6438 | 0x2008 6438
CFG_TRIG_ERR_MASK_1 | RW | 32 | 0x0000 0000 | 0x0 643C | 0x2008 643C
CFG_TRIG_ERR_MASK_2 | RW | 32 | 0x0000 0000 | 0x0 6440 | 0x2008 6440
CFG_TRIG_ERR_MASK_3 | RW | 32 | 0x0000 0000 | 0x0 6444 | 0x2008 6444
CFG_TRIG_ERR_MASK_4 | RW | 32 | 0x0000 0000 | 0x0 6448 | 0x2008 6448
MTC_ACQ_WR_DATA_0 | RW | 32 | 0x0000 0000 | 0x0 644C | 0x2008 644C
MTC_ACQ_WR_DATA_1 | RW | 32 | 0x0000 0000 | 0x0 6450 | 0x2008 6450
MTC_ACQ_WR_DATA_2 | RW | 32 | 0x0000 0000 | 0x0 6454 | 0x2008 6454
MTC_ACQ_RD_DATA_0 | RO | 32 | 0x0000 0000 | 0x0 6458 | 0x2008 6458
MTC_ACQ_RD_DATA_1 | RO | 32 | 0x0000 0000 | 0x0 645C | 0x2008 645C
MTC_ACQ_RD_DATA_2 | RO | 32 | 0x0000 0000 | 0x0 6460 | 0x2008 6460
CFG_PRE_TRIG_CYCS | RW | 32 | 0x0000 0000 | 0x0 652C | 0x2008 652C
MTC_ACQ_ERROR_CNT | RO | 32 | 0x0000 0000 | 0x0 6538 | 0x2008 6538
MTC_ACQ_ERROR_CNT_OVFL | RO | 32 | 0x0000 0000 | 0x0 6544 | 0x2008 6544
CFG_DATA_SEL_FIRST_ERROR | RW | 32 | 0x0000 0000 | 0x0 6550 | 0x2008 6550
CFG_DQ_WIDTH | RW | 32 | 0x0000 0000 | 0x0 7C00 | 0x2008 7C00
CFG_ACTIVE_DQ_SEL | RW | 32 | 0x0000 0000 | 0x0 7C04 | 0x2008 7C04
STAT_CA_PARITY_ERROR | RO | 32 | 0x0000 0000 | 0x0 8000 | 0x2008 8000
INIT_CA_PARITY_ERROR_GEN_REQ | RW | 32 | 0x0000 0000 | 0x0 800C | 0x2008 800C
INIT_CA_PARITY_ERROR_GEN_CMD | RW | 32 | 0x0000 0000 | 0x0 8010 | 0x2008 8010
INIT_CA_PARITY_ERROR_GEN_ACK | RO | 32 | 0x0000 0000 | 0x0 8014 | 0x2008 8014
CFG_DFI_T_RDDATA_EN | RW | 32 | 0x0000 0014 | 0x1 0000 | 0x2009 0000
CFG_DFI_T_PHY_RDLAT | RW | 32 | 0x0000 0005 | 0x1 0004 | 0x2009 0004
CFG_DFI_T_PHY_WRLAT | RW | 32 | 0x0000 0005 | 0x1 0008 | 0x2009 0008
CFG_DFI_PHYUPD_EN | RW | 32 | 0x0000 0001 | 0x1 000C | 0x2009 000C
INIT_DFI_LP_DATA_REQ | RW | 32 | 0x0000 0000 | 0x1 0010 | 0x2009 0010
INIT_DFI_LP_CTRL_REQ | RW | 32 | 0x0000 0000 | 0x1 0014 | 0x2009 0014
STAT_DFI_LP_ACK | RO | 32 | 0x0000 0000 | 0x1 0018 | 0x2009 0018
INIT_DFI_LP_WAKEUP | RW | 32 | 0x0000 0000 | 0x1 001C | 0x2009 001C
INIT_DFI_DRAM_CLK_DISABLE | RW | 32 | 0x0000 0000 | 0x1 0020 | 0x2009 0020
STAT_DFI_TRAINING_ERROR | RO | 32 | 0x0000 0000 | 0x1 0024 | 0x2009 0024
STAT_DFI_ERROR | RO | 32 | 0x0000 0000 | 0x1 0028 | 0x2009 0028
STAT_DFI_ERROR_INFO | RO | 32 | 0x0000 0000 | 0x1 002C | 0x2009 002C
CFG_DFI_DATA_BYTE_DISABLE | RW | 32 | 0x0000 0000 | 0x1 0030 | 0x2009 0030
STAT_DFI_INIT_COMPLETE | RO | 32 | 0x0000 0000 | 0x1 0034 | 0x2009 0034
STAT_DFI_TRAINING_COMPLETE | RO | 32 | 0x0000 0000 | 0x1 0038 | 0x2009 0038
CFG_DFI_LVL_SEL | RW | 32 | 0x0000 0000 | 0x1 003C | 0x2009 003C
CFG_DFI_LVL_PERIODIC | RW | 32 | 0x0000 0000 | 0x1 0040 | 0x2009 0040
CFG_DFI_LVL_PATTERN | RW | 32 | 0x0000 0000 | 0x1 0044 | 0x2009 0044
PHY_DFI_INIT_START | RW | 32 | 0x0000 0000 | 0x1 0050 | 0x2009 0050
CFG_AXI_START_ADDRESS_AXI1_0 | RW | 32 | 0x0000 0000 | 0x1 2C18 | 0x2009 2C18
CFG_AXI_START_ADDRESS_AXI1_1 | RW | 32 | 0x0000 0000 | 0x1 2C1C | 0x2009 2C1C
CFG_AXI_START_ADDRESS_AXI2_0 | RW | 32 | 0x0000 0000 | 0x1 2C20 | 0x2009 2C20
CFG_AXI_START_ADDRESS_AXI2_1 | RW | 32 | 0x0000 0000 | 0x1 2C24 | 0x2009 2C24
CFG_AXI_END_ADDRESS_AXI1_0 | RW | 32 | 0xFFFF FFFF | 0x1 2F18 | 0x2009 2F18
CFG_AXI_END_ADDRESS_AXI1_1 | RW | 32 | 0x0000 0003 | 0x1 2F1C | 0x2009 2F1C
CFG_AXI_END_ADDRESS_AXI2_0 | RW | 32 | 0xFFFF FFFF | 0x1 2F20 | 0x2009 2F20
CFG_AXI_END_ADDRESS_AXI2_1 | RW | 32 | 0x0000 0003 | 0x1 2F24 | 0x2009 2F24
CFG_MEM_START_ADDRESS_AXI1_0 | RW | 32 | 0x0000 0000 | 0x1 3218 | 0x2009 3218
CFG_MEM_START_ADDRESS_AXI1_1 | RW | 32 | 0x0000 0000 | 0x1 321C | 0x2009 321C
CFG_MEM_START_ADDRESS_AXI2_0 | RW | 32 | 0x0000 0000 | 0x1 3220 | 0x2009 3220
CFG_MEM_START_ADDRESS_AXI2_1 | RW | 32 | 0x0000 0000 | 0x1 3224 | 0x2009 3224
CFG_ENABLE_BUS_HOLD_AXI1 | RW | 32 | 0x0000 0000 | 0x1 3514 | 0x2009 3514
CFG_ENABLE_BUS_HOLD_AXI2 | RW | 32 | 0x0000 0000 | 0x1 3518 | 0x2009 3518
CFG_AXI_AUTO_PCH | RW | 32 | 0x0000 0000 | 0x1 3690 | 0x2009 3690
PHY_RESET_CONTROL | RW | 32 | 0x0000 000D | 0x3 C000 | 0x200B C000
PHY_PC_RANK | RW | 32 | 0x0000 0000 | 0x3 C004 | 0x200B C004
PHY_RANKS_TO_TRAIN | RW | 32 | 0x0000 0000 | 0x3 C008 | 0x200B C008
PHY_WRITE_REQUEST | RW | 32 | 0x0000 0000 | 0x3 C00C | 0x200B C00C
PHY_WRITE_REQUEST_DONE | RO | 32 | 0x0000 0000 | 0x3 C010 | 0x200B C010
PHY_READ_REQUEST | RW | 32 | 0x0000 0000 | 0x3 C014 | 0x200B C014
PHY_READ_REQUEST_DONE | RO | 32 | 0x0000 0000 | 0x3 C018 | 0x200B C018
PHY_WRITE_LEVEL_DELAY | RW | 32 | 0x0000 0000 | 0x3 C01C | 0x200B C01C
PHY_GATE_TRAIN_DELAY | RW | 32 | 0x0000 0000 | 0x3 C020 | 0x200B C020
PHY_EYE_TRAIN_DELAY | RW | 32 | 0x0000 0000 | 0x3 C024 | 0x200B C024
PHY_EYE_PAT | RW | 32 | 0x0000 0000 | 0x3 C028 | 0x200B C028
PHY_START_RECAL | RW | 32 | 0x0000 0000 | 0x3 C02C | 0x200B C02C
PHY_CLR_DFI_LVL_PERIODIC | RW | 32 | 0x0000 0000 | 0x3 C030 | 0x200B C030
PHY_TRAIN_STEP_ENABLE | RW | 32 | 0x0000 0000 | 0x3 C034 | 0x200B C034
PHY_LPDDR_DQ_CAL_PAT | RW | 32 | 0x0000 0000 | 0x3 C038 | 0x200B C038
PHY_INDPNDT_TRAINING | RW | 32 | 0x0000 0000 | 0x3 C03C | 0x200B C03C
PHY_ENCODED_QUAD_CS | RW | 32 | 0x0000 0000 | 0x3 C040 | 0x200B C040
PHY_HALF_CLK_DLY_ENABLE | RW | 32 | 0x0000 0000 | 0x3 C044 | 0x200B C044

## DDR_CSR_APB Register Descriptions

### DDR_CSR_APB : CFG_MANUAL_ADDRESS_MAP

Address offset | 0x0 2400
Physical address | 0x2008 2400 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_manual_address_map | Enables user selection of address mapping 0 - Default address mapping. Address mapping from l_addr based on settings of cfg_mem_rowbits, cfg_mem_colbits, as described in the SDRAM Controller User Guide. 1 - User selected address mapping. Address mapping from l_addr based on settings of cfg_chipaddr_map, cfg_rowaddr_map, cfg_bankaddr_map, cfg_coladdr_map, and cfg_cidaddr_map (DDR4 3DS) | RW | 0

### DDR_CSR_APB : CFG_CHIPADDR_MAP

Address offset | 0x0 2404
Physical address | 0x2008 2404 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | reserved |  | RO | 0x00
23:0 | cfg_chipaddr_map | Four 6-bit quantities specifying how to map address bits from l_addr into the rank (chip select bits, sd_cs_n). bits 0-5 - Specify which bit of l_addr maps to chip address bit 0 bits 6-11 - Specifies which bit of l_addr maps to chip address bit 1 bits 12-17 - Specifies which bit of l_addr maps to chip address bit 2 bits 18-23 - Specifies which bit of l_addr maps to chip address bit 3 | RW | 0x00 0000

### DDR_CSR_APB : CFG_CIDADDR_MAP

Address offset | 0x0 2408
Physical address | 0x2008 2408 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:18 | reserved |  | RO | 0x0000
17:0 | cfg_cidaddr_map | Three 6-bit quantities specifying how to map address bits from l_addr into 3DS chip ID bits (sd_cid[2:0]). bits 0-5 - Specify which bit of l_addr maps to chip ID bit 0 bits 6-11 - Specifies which bit of l_addr maps to chip ID bit 1 bits 12-17 - Specifies which bit of l_addr maps to chip ID bit 2 | RW | 0x0 0000

### DDR_CSR_APB : CFG_MB_AUTOPCH_COL_BIT_POS_LOW

Address offset | 0x0 240C
Physical address | 0x2008 240C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_mb_autopch_col_bit_pos_low | This field together with the cfg_mb_autopch_col_bit_pos_high field set a contiguous column address region that allows customization of when auto precharge occurs within multiburst accesses. cfg_mb_autopch_col_bit_pos_low sets the low bit position of l_addr and cfg_mb_autopch_col_bit_pos_high sets the high bit position of l_addr bits that are used to define the last column address in an open bank. When the multiburst internal l_addr bits in the l_addr range defined by these two configuration fields are all one, an auto_precharge will be issued by the multiburst module internally for the sub-access. This field is unused if cfg_manual_address_map is set to 0. Setting this field to 0 disables this auto-precharge functionality. When it is used, the only valid values are a function of the memory technology being used as follows: DDR3 - 3 or 4. (3 is normal default) DDR4 - 3 or 4. (4 is normal default) HBM - 2,3,or 4 (4 is normal default) | RW | 0x4

### DDR_CSR_APB : CFG_MB_AUTOPCH_COL_BIT_POS_HIGH

Address offset | 0x0 2410
Physical address | 0x2008 2410 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_mb_autopch_col_bit_pos_high | This field together with the cfg_mb_autopch_col_bit_pos_low field set a contiguous column address region that allows customization of when auto precharge occurs within multiburst accesses. cfg_mb_autopch_col_bit_pos_low sets the low bit position of l_addr and cfg_mb_autopch_col_bit_pos_high sets the high bit position of l_addr bits that are used to define the last column address in an open bank. When the multiburst internal l_addr bits in the l_addr range defined by these two configuration fields are all one, an auto_precharge will be issued by the multiburst module internally for the sub-access. This field is unused if if cfg_manual_address_map is set to 0. When it is used, the only valid values are a function of the memory technology being used as follows: DDR3 - cfg_mem_colbits-1 to 4. (cfg_mem_colbits-1 is the normal default) DDR4 - 10 to 4. (10 is the normal default) HBM - 8 to 4. (8 is the normal default) | RW | 0xA

### DDR_CSR_APB : CFG_BANKADDR_MAP_0

Address offset | 0x0 2414
Physical address | 0x2008 2414 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bankaddr_map_0 | Six 6-bit quantities specifying how to map address bits from l_addr into bank bits (sd_ba). bits 0-5 - Specify which bit of l_addr maps to bank address bit 0 (sd_ba[0]) bits 6-11 - Specifies which bit of l_addr maps to bank address bit 1 (sd_ba[1]) bits 12-17 - Specifies which bit of l_addr maps to bank address bit 2/group bit 0 (sd_ba[2], for HBM pseudo channel memory this is also the pseudo channel select bit) bits 18-23 - Specifies which bit of l_addr maps to bank address bit 3/group bit 1 (sd_ba[3]) bits 24-29 - Specifies which bit of l_addr maps to bank address bit 4/group bit 2 (sd_ba[4]) bits 30-35 - Specifies which bit of l_addr maps to bank address bit 5/group bit 3 (sd_ba[5], for HBM pseudo channel memory this is also the SID bank selection bit) | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BANKADDR_MAP_1

Address offset | 0x0 2418
Physical address | 0x2008 2418 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_bankaddr_map_1 | Six 6-bit quantities specifying how to map address bits from l_addr into bank bits (sd_ba). bits 0-5 - Specify which bit of l_addr maps to bank address bit 0 (sd_ba[0]) bits 6-11 - Specifies which bit of l_addr maps to bank address bit 1 (sd_ba[1]) bits 12-17 - Specifies which bit of l_addr maps to bank address bit 2/group bit 0 (sd_ba[2], for HBM pseudo channel memory this is also the pseudo channel select bit) bits 18-23 - Specifies which bit of l_addr maps to bank address bit 3/group bit 1 (sd_ba[3]) bits 24-29 - Specifies which bit of l_addr maps to bank address bit 4/group bit 2 (sd_ba[4]) bits 30-35 - Specifies which bit of l_addr maps to bank address bit 5/group bit 3 (sd_ba[5], for HBM pseudo channel memory this is also the SID bank selection bit) | RW | 0x0

### DDR_CSR_APB : CFG_ROWADDR_MAP_0

Address offset | 0x0 241C
Physical address | 0x2008 241C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_rowaddr_map_0 | Eighteen 6-bit quantities specifying how to map address bits from l_addr into row bits (sd_a, during activate command). bits 0-5 - Specify which bit of l_addr maps to row address bit 0 bits 6-11 - Specifies which bit of l_addr maps to row address bit 1 ... bits 6*x-6*x+5 - Specifies which bit of l_addr maps to row address bit x Note: When 6'd00 is used, it means a hard-coded zero (not l_addr[0]) except in the case where zero is used in the lower 9 rowaddr bit selections, in which case it refers to l_addr[0]. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_ROWADDR_MAP_1

Address offset | 0x0 2420
Physical address | 0x2008 2420 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_rowaddr_map_1 | Eighteen 6-bit quantities specifying how to map address bits from l_addr into row bits (sd_a, during activate command). bits 0-5 - Specify which bit of l_addr maps to row address bit 0 bits 6-11 - Specifies which bit of l_addr maps to row address bit 1 ... bits 6*x-6*x+5 - Specifies which bit of l_addr maps to row address bit x Note: When 6'd00 is used, it means a hard-coded zero (not l_addr[0]) except in the case where zero is used in the lower 9 rowaddr bit selections, in which case it refers to l_addr[0]. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_ROWADDR_MAP_2

Address offset | 0x0 2424
Physical address | 0x2008 2424 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_rowaddr_map_2 | Eighteen 6-bit quantities specifying how to map address bits from l_addr into row bits (sd_a, during activate command). bits 0-5 - Specify which bit of l_addr maps to row address bit 0 bits 6-11 - Specifies which bit of l_addr maps to row address bit 1 ... bits 6*x-6*x+5 - Specifies which bit of l_addr maps to row address bit x Note: When 6'd00 is used, it means a hard-coded zero (not l_addr[0]) except in the case where zero is used in the lower 9 rowaddr bit selections, in which case it refers to l_addr[0]. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_ROWADDR_MAP_3

Address offset | 0x0 2428
Physical address | 0x2008 2428 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved |  | RO | 0x0 0000
11:0 | cfg_rowaddr_map_3 | Eighteen 6-bit quantities specifying how to map address bits from l_addr into row bits (sd_a, during activate command). bits 0-5 - Specify which bit of l_addr maps to row address bit 0 bits 6-11 - Specifies which bit of l_addr maps to row address bit 1 ... bits 6*x-6*x+5 - Specifies which bit of l_addr maps to row address bit x Note: When 6'd00 is used, it means a hard-coded zero (not l_addr[0]) except in the case where zero is used in the lower 9 rowaddr bit selections, in which case it refers to l_addr[0]. | RW | 0x000

### DDR_CSR_APB : CFG_COLADDR_MAP_0

Address offset | 0x0 242C
Physical address | 0x2008 242C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_coladdr_map_0 | Sixteen 6-bit quantities specifying how to map address bits from l_addr into row bits (sd_a, during read/write commands). bits 0-5 - Specify which bit of l_addr maps to column address bit 0 bits 6-11 - Specifies which bit of l_addr maps to column address bit 1 ... bits 6*x-6*x+5 - Specifies which bit of l_addr maps to column address bit x Note: When 6'd00 is used, it means a hard-coded zero (not l_addr[0]) except in the case where zero is used in the lower 3 coladdr selections, in which case it refers to l_addr[0]. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_COLADDR_MAP_1

Address offset | 0x0 2430
Physical address | 0x2008 2430 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_coladdr_map_1 | Sixteen 6-bit quantities specifying how to map address bits from l_addr into row bits (sd_a, during read/write commands). bits 0-5 - Specify which bit of l_addr maps to column address bit 0 bits 6-11 - Specifies which bit of l_addr maps to column address bit 1 ... bits 6*x-6*x+5 - Specifies which bit of l_addr maps to column address bit x Note: When 6'd00 is used, it means a hard-coded zero (not l_addr[0]) except in the case where zero is used in the lower 3 coladdr selections, in which case it refers to l_addr[0]. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_COLADDR_MAP_2

Address offset | 0x0 2434
Physical address | 0x2008 2434 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_coladdr_map_2 | Sixteen 6-bit quantities specifying how to map address bits from l_addr into row bits (sd_a, during read/write commands). bits 0-5 - Specify which bit of l_addr maps to column address bit 0 bits 6-11 - Specifies which bit of l_addr maps to column address bit 1 ... bits 6*x-6*x+5 - Specifies which bit of l_addr maps to column address bit x Note: When 6'd00 is used, it means a hard-coded zero (not l_addr[0]) except in the case where zero is used in the lower 3 coladdr selections, in which case it refers to l_addr[0]. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_VRCG_ENABLE

Address offset | 0x0 2800
Physical address | 0x2008 2800 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_vrcg_enable | LPDDR4 Vref high current mode enable time tVRCG_ENABLE, expressed in terms of memory clocks. | RW | 0x140

### DDR_CSR_APB : CFG_VRCG_DISABLE

Address offset | 0x0 2804
Physical address | 0x2008 2804 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_vrcg_disable | LPDDR4 Vref high current mode disable time tVRCG_DISABLE, expressed in terms of memory clocks. | RW | 0x0A0

### DDR_CSR_APB : CFG_WRITE_LATENCY_SET

Address offset | 0x0 2808
Physical address | 0x2008 2808 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_write_latency_set | LPDDR4 Write Latency Set A/B selection (MR2[6]). | RW | 0

### DDR_CSR_APB : CFG_THERMAL_OFFSET

Address offset | 0x0 280C
Physical address | 0x2008 280C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_thermal_offset | LPDDR4 Thermal Offset (MR4[6:5]). | RW | 0x0

### DDR_CSR_APB : CFG_SOC_ODT

Address offset | 0x0 2810
Physical address | 0x2008 2810 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_soc_odt | LPDDR4 SOC ODT (MR22[2:0]) | RW | 0x0

### DDR_CSR_APB : CFG_ODTE_CK

Address offset | 0x0 2814
Physical address | 0x2008 2814 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_odte_ck | LPDDR4 ODTE-CK (MR22[3]) | RW | 0

### DDR_CSR_APB : CFG_ODTE_CS

Address offset | 0x0 2818
Physical address | 0x2008 2818 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_odte_cs | LPDDR4 ODTE-CS (MR22[4]) | RW | 0

### DDR_CSR_APB : CFG_ODTD_CA

Address offset | 0x0 281C
Physical address | 0x2008 281C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_odtd_ca | LPDDR4 ODTD-CA (MR22[5]) | RW | 0

### DDR_CSR_APB : CFG_LPDDR4_FSP_OP

Address offset | 0x0 2820
Physical address | 0x2008 2820 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_lpddr4_fsp_op | User-selection for the operating frequency setpoint following LPDDR4 DRAM initialization. This value is written to MR13[7] at the end of the automatic initialization sequence. This value should typically be set to 0 to allow the PHY to perform Command Bus Training (CBT) prior to switching to the faster FSP. | RW | 0

### DDR_CSR_APB : CFG_GENERATE_REFRESH_ON_SRX

Address offset | 0x0 2824
Physical address | 0x2008 2824 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_generate_refresh_on_srx | When exiting self-refresh the controller will wait for a refresh to occur before allowing normal memory requests to resume. The controller can either generate the refresh request immediately or it can wait for the refresh timer to generate the refresh request naturally. In typical systems the controller should be programmed to generate the refresh immediately (cfg_generate_refresh_on_srx=1) for low latency following self-refresh exit. In some dual-controller systems it is advantageous to maintain synchronization in refresh requests and the cfg_generate_refresh_on_srx should be disabled (cfg_generate_refresh_on_srx=0) to allow the synchronized refresh timers to maintain refresh request synchronization. | RW | 1

### DDR_CSR_APB : CFG_DBI_CL

Address offset | 0x0 2828
Physical address | 0x2008 2828 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | cfg_dbi_cl | DDR4 SDRAM DBI CAS read latency, specified in clocks. Refer to SDRAM datasheet for list of supported values. | RW | 0x16

### DDR_CSR_APB : CFG_NON_DBI_CL

Address offset | 0x0 282C
Physical address | 0x2008 282C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | cfg_non_dbi_cl | DDR4 SDRAM non-DBI CAS read latency, specified in clocks. Refer to SDRAM datasheet for list of supported values. | RW | 0x16

### DDR_CSR_APB : INIT_FORCE_WRITE_DATA_0

Address offset | 0x0 2830
Physical address | 0x2008 2830 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | reserved |  | RO | 0x00 0000
8:0 | init_force_write_data_0 | Data driven to memory device nibble lanes when init_force_write is asserted and a regular write is not being driven. Each bit corresponds to one nibble of the memory interface and drives all 4 bits of the corresponding nibble. Bit 0 - driven to DQ nibble [3:0] Bit 1 - driven to DQ nibble [7:4] ... Bit n-1 - driven to DQ nibble [n*4+3:n*4] | RW | 0x000

### DDR_CSR_APB : CFG_WRITE_CRC

Address offset | 0x0 3C00
Physical address | 0x2008 3C00 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_write_crc | Enables DDR4 write CRC mode, where controller automatically generates CRC in transfer 8 for x8 and x16 devices. The CRC is transmitted in transfers 8 and 9 in x4 devices. | RW | 0

### DDR_CSR_APB : CFG_MPR_READ_FORMAT

Address offset | 0x0 3C04
Physical address | 0x2008 3C04 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_mpr_read_format | Defines read format during DDR4 MPR reads: 0 - Serial 1 - Parallel (only valid for Page 0 MPR reads) 2 - Staggered (only valid for Page 0 MPR reads) | RW | 0x0

### DDR_CSR_APB : CFG_WR_CMD_LAT_CRC_DM

Address offset | 0x0 3C08
Physical address | 0x2008 3C08 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_wr_cmd_lat_crc_dm | DDR4 extra write command latency when CRC and DM are both enabled. This value is programmed into MR3(10:9). Memory devices use this value to determine the write recovery time required after write with auto-precharge command is issued. 0 - 4 clocks (1600 speed bin) 1 - 5 clocks (1866, 2133, 2400 speed bins) 2 - 6 clocks (TBD speed bin) 3 - RFU | RW | 0x0

### DDR_CSR_APB : CFG_FINE_GRAN_REF_MODE

Address offset | 0x0 3C0C
Physical address | 0x2008 3C0C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_fine_gran_ref_mode | DDR4 fine granularity refresh mode: 0 - Normal (fixed 1x) 1 - Fixed 2x 2 - Fixed 4x 3 - Reserved 4 - Reserved 5 - On the fly 2x (not supported) 6 - On the fly 4x (not supported) 7 - Reserved When using either Fixed 2x or Fixed 4x fine granularity refresh mode, the refresh period specified by cfg_ref_per is divided internally by 2 or 4, respectively, to produce REFRESH commands at the proper interval. | RW | 0x0

### DDR_CSR_APB : CFG_TEMP_SENSOR_READOUT

Address offset | 0x0 3C10
Physical address | 0x2008 3C10 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_temp_sensor_readout | Enables DDR4 device temperature sensor | RW | 0

### DDR_CSR_APB : CFG_PER_DRAM_ADDR_EN

Address offset | 0x0 3C14
Physical address | 0x2008 3C14 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_per_dram_addr_en | Maps to bit 4 of Mode Register 3 during mode register programming. Must be set to 0 for automatic initialization ('init_autoinit_disable' = 0). Typically set to 0 for manual initialization also ('init_autoinit_disable' = 1), even when per-DRAM addressability mode is used. To enable per-DRAM addressability the mode register should be programmed directly using the 'init_mr_*' signaling. This process is described in Section 9.15 of the DDR4 SDRAM Controller User Guide. | RW | 0

### DDR_CSR_APB : CFG_GEARDOWN_MODE

Address offset | 0x0 3C18
Physical address | 0x2008 3C18 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_geardown_mode | DDR4 geardown mode select: 0 - rate geardown mode 1 - rate geardown mode. Controller will switch to rate geardown mode during initialization sequence. | RW | 0

### DDR_CSR_APB : CFG_WR_PREAMBLE

Address offset | 0x0 3C1C
Physical address | 0x2008 3C1C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_wr_preamble | Write preamble select: 0 - 1 clock write preamble 1 - 2 clock write preamble Note that it may also be necessary to program the PHY for the desired write preamble mode. | RW | 0

### DDR_CSR_APB : CFG_RD_PREAMBLE

Address offset | 0x0 3C20
Physical address | 0x2008 3C20 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_rd_preamble | DDR4 read preamble select: 0 - 1 clock read preamble 1 - 2 clock read preamble | RW | 0

### DDR_CSR_APB : CFG_RD_PREAMB_TRN_MODE

Address offset | 0x0 3C24
Physical address | 0x2008 3C24 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_rd_preamb_trn_mode | DDR4 read preamble training mode. Must be set to 0 for automatic initialization ('init_autoinit_disable' = 0). | RW | 0

### DDR_CSR_APB : CFG_SR_ABORT

Address offset | 0x0 3C28
Physical address | 0x2008 3C28 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_sr_abort | Self refresh abort mode select, setting the appropriate mode register bit: 0 - Disable self-refresh abort mode 1 - Enable self-refresh abort mode Note: The controller does not perform operations any sooner after self-refresh exit when self-refresh abort mode is enabled. | RW | 0

### DDR_CSR_APB : CFG_CS_TO_CMDADDR_LATENCY

Address offset | 0x0 3C2C
Physical address | 0x2008 3C2C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_cs_to_cmdaddr_latency | DDR4 command/address latency mode setting: 0 - Disable command/address latency mode 1 - 3 clock command address latency 2 - 4 clock command address latency 3 - 5 clock command address latency 4 - 6 clock command address latency 5 - 8 clock command address latency 6 - Reserved 7 - Reserved Note: DDR4 command/address latency must be disabled in RDIMM/LRDIMM applications, as the RCD does not support this mode. | RW | 0x0

### DDR_CSR_APB : CFG_INT_VREF_MON

Address offset | 0x0 3C30
Physical address | 0x2008 3C30 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_int_vref_mon | DDR4 internal Vref monitor: 0 - Disable Vref monitor 1 - Enable Vref monitor | RW | 0

### DDR_CSR_APB : CFG_TEMP_CTRL_REF_MODE

Address offset | 0x0 3C34
Physical address | 0x2008 3C34 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_temp_ctrl_ref_mode | Used to control refresh for DDR4 and self-refresh for HBM. For DDR4 temperature controlled refresh mode: 0 - Disable temperature controlled refresh mode 1 - Enable temperature controlled refresh mode For HBM temperature controlled self-refresh mode: 0 - Disable temperature compensated self-refresh mode 1 - Enable temperature compensated self-refresh mode This bit is loaded into bit 2 (TCSR) of Mode register 0. | RW | 0

### DDR_CSR_APB : CFG_TEMP_CTRL_REF_RANGE

Address offset | 0x0 3C38
Physical address | 0x2008 3C38 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_temp_ctrl_ref_range | DDR4 temperature controlled refresh range. Only used when 'cfg_temp_ctrl_ref_mode' is set to 1: 0 - Normal temperature mode. Below 45 degrees Celsius, DDR4 SDRAM may adjust internal refresh period to be longer than tREFI of the normal temperature range by skipping external refresh commands 1 - Extended temperature mode. In this mode it is expected that the cfg_ref_period is set for the extended temperature range tREFI. In the normal temperature range (0C - 85C), the DDR4 SDRAM adjusts its internal refresh period to tREFI of the normal temperature range. Below 45C, the DDR4 SDRAM may further adjust internal refresh period to be longer than tREFI of the normal temperature range. | RW | 0

### DDR_CSR_APB : CFG_MAX_PWR_DOWN_MODE

Address offset | 0x0 3C3C
Physical address | 0x2008 3C3C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_max_pwr_down_mode | Enables DDR4 maximum power savings mode. Must be set to 0 for automatic initialization ('init_autoinit_disable' = 0). | RW | 0

### DDR_CSR_APB : CFG_READ_DBI

Address offset | 0x0 3C40
Physical address | 0x2008 3C40 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_read_dbi | Read data bus inversion (DBI): 0 - Read DBI disabled 1 - Read DBI enabled | RW | 0

### DDR_CSR_APB : CFG_WRITE_DBI

Address offset | 0x0 3C44
Physical address | 0x2008 3C44 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_write_dbi | Write data bus inversion (DBI): 0 - Write DBI disabled 1 - Write DBI enabled | RW | 0

### DDR_CSR_APB : CFG_DATA_MASK

Address offset | 0x0 3C48
Physical address | 0x2008 3C48 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_data_mask | Write data mask: 0 - Write data mask disabled 1 - Write data mask enabled For GDDR6 this enables the use of the write-with-single-byte-mask (WSM/A) and write-with-double-byte-mask (WDM/A) commands. | RW | 1

### DDR_CSR_APB : CFG_CA_PARITY_PERSIST_ERR

Address offset | 0x0 3C4C
Physical address | 0x2008 3C4C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_ca_parity_persist_err | Persistent parity error mode. 0 - DRAM stops checking command/address parity until Parity Error Status bit is cleared 1 - DRAM resumes checking command/address parity after the alert_n is deasserted, even if Parity Error Status bit remains high | RW | 0

### DDR_CSR_APB : CFG_RTT_PARK

Address offset | 0x0 3C50
Physical address | 0x2008 3C50 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_rtt_park | RTT_PARK termination value 0 - RTT_PARK disable 1 - RZQ/4 2 - RZQ/2 3 - RZQ/6 4 - RZQ/1 5 - RZQ/5 6 - RZQ/3 7 - RZQ/7 | RW | 0x0

### DDR_CSR_APB : CFG_ODT_INBUF_4_PD

Address offset | 0x0 3C54
Physical address | 0x2008 3C54 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_odt_inbuf_4_pd | ODT input buffer during power down mode. 0 - ODT input buffer is activated 1 - ODT input buffer is deactivated | RW | 0

### DDR_CSR_APB : CFG_CA_PARITY_ERR_STATUS

Address offset | 0x0 3C58
Physical address | 0x2008 3C58 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_ca_parity_err_status | When the controller does a write to MR5 this signal becomes MR5 bit 4 and clears the parity error status in the DDR4 SDRAM. It should always be set to 0 because the DDR4 spec says to only program it to 0.(C/A Parity error status)" | RW | 0

### DDR_CSR_APB : CFG_CRC_ERROR_CLEAR

Address offset | 0x0 3C5C
Physical address | 0x2008 3C5C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_crc_error_clear | CRC Error clear. Must be set to 0. | RW | 0

### DDR_CSR_APB : CFG_CA_PARITY_LATENCY

Address offset | 0x0 3C60
Physical address | 0x2008 3C60 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_ca_parity_latency | Command / Address Parity setting: 0 - Command / Address Parity disabled 1 - 4 clock parity latency (1600, 1866, 2133 speed bins) 2 - 5 clock parity latency (2400 speed bin) 3 - 6 clock parity latency (TBD speed bin) 4 - 8 clock parity latency (TBD speed bin) | RW | 0x0

### DDR_CSR_APB : CFG_CCD_S

Address offset | 0x0 3C64
Physical address | 0x2008 3C64 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_ccd_s | SDRAM CAS_n-to-CAS_n delay for different bank group (tCCD_S), specified in clocks. For HBM pseudo channel mode memory, this is tracked for each pseudo channel. | RW | 0x0

### DDR_CSR_APB : CFG_CCD_L

Address offset | 0x0 3C68
Physical address | 0x2008 3C68 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_ccd_l | SDRAM CAS_n-to-CAS_n delay for same bank group (tCCD_L), specified in clocks. For HBM pseudo channel mode memory, this is tracked for each pseudo channel. Note that when issuing back to back read commands within a pseudo channel that are destined to different SID banks (i.e. SID = 0 in one command and SID = 1 in the other command), the second read will be delayed by cfg_ccd_l (to meet the worst case tCCDR read specification). For back to back writes with SID bit changing within a pseudo channel, the second command is only delayed by cfg_ccd_s l_clks from the first write command (meeting the tCCDR write requirements). | RW | 0x0

### DDR_CSR_APB : CFG_VREFDQ_TRN_ENABLE

Address offset | 0x0 3C6C
Physical address | 0x2008 3C6C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_vrefdq_trn_enable | Enables Vref training mode. Must be set to 0 for automatic initialization ('init_autoinit_disable' = 0). | RW | 0

### DDR_CSR_APB : CFG_VREFDQ_TRN_RANGE

Address offset | 0x0 3C70
Physical address | 0x2008 3C70 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_vrefdq_trn_range | VrefDQ training range selection: 0 - VrefDQ Range 1 1 - VrefDQ Range 2 | RW | 0

### DDR_CSR_APB : CFG_VREFDQ_TRN_VALUE

Address offset | 0x0 3C74
Physical address | 0x2008 3C74 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | cfg_vrefdq_trn_value | Vref training value. Not used during automatic initialization ('init_autoinit_disable'=0). | RW | 0x00

### DDR_CSR_APB : CFG_RRD_S

Address offset | 0x0 3C78
Physical address | 0x2008 3C78 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_rrd_s | SDRAM ACTIVATE-to-ACTIVATE command period for different bank group (tRRD_S), specified in clocks. | RW | 0x03

### DDR_CSR_APB : CFG_RRD_L

Address offset | 0x0 3C7C
Physical address | 0x2008 3C7C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_rrd_l | SDRAM ACTIVATE-to-ACTIVATE command period for same group (tRRD_L), specified in clocks. | RW | 0x03

### DDR_CSR_APB : CFG_WTR_S

Address offset | 0x0 3C80
Physical address | 0x2008 3C80 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_wtr_s | SDRAM write to read command delay for different bank group (tWTR_S), specified in clocks. | RW | 0x2

### DDR_CSR_APB : CFG_WTR_L

Address offset | 0x0 3C84
Physical address | 0x2008 3C84 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_wtr_l | SDRAM write to read command delay for same bank group (tWTR_L), specified in clocks. | RW | 0x2

### DDR_CSR_APB : CFG_WTR_S_CRC_DM

Address offset | 0x0 3C88
Physical address | 0x2008 3C88 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_wtr_s_crc_dm | SDRAM write to read command delay for different bank group, when both CRC and DM are enabled (tWTR_S_CRC_DM), specified in clocks. | RW | 0x2

### DDR_CSR_APB : CFG_WTR_L_CRC_DM

Address offset | 0x0 3C8C
Physical address | 0x2008 3C8C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_wtr_l_crc_dm | SDRAM write to read command delay for same bank group, when both CRC and DM are enabled (tWTR_L_CRC_DM), specified in clocks. | RW | 0x02

### DDR_CSR_APB : CFG_WR_CRC_DM

Address offset | 0x0 3C90
Physical address | 0x2008 3C90 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | cfg_wr_crc_dm | SDRAM write recovery time when both CRC and DM are enabled (tWR_CRC_DM), specified in clocks | RW | 0x04

### DDR_CSR_APB : CFG_RFC1

Address offset | 0x0 3C94
Physical address | 0x2008 3C94 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_rfc1 | SDRAM refresh to activate or refresh command period when in 1x fine granularity refresh mode (tRFC1). | RW | 0x022

### DDR_CSR_APB : CFG_RFC2

Address offset | 0x0 3C98
Physical address | 0x2008 3C98 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_rfc2 | SDRAM refresh to activate or refresh command period when in 2x fine granularity refresh mode (tRFC2). | RW | 0x022

### DDR_CSR_APB : CFG_RFC4

Address offset | 0x0 3C9C
Physical address | 0x2008 3C9C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_rfc4 | SDRAM refresh to activate or refresh command period when in 4x fine granularity refresh mode (tRFC4). | RW | 0x022

### DDR_CSR_APB : CFG_NIBBLE_DEVICES

Address offset | 0x0 3CC4
Physical address | 0x2008 3CC4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_nibble_devices | Indicates memory configuration is composed of x4 memory devices or x8/x16 devices. CRC data for writes is generated differently for x4 devices then x8/x16 devices. | RW | 0

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS0_0

Address offset | 0x0 3CE0
Physical address | 0x2008 3CE0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs0_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS0_1

Address offset | 0x0 3CE4
Physical address | 0x2008 3CE4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs0_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS1_0

Address offset | 0x0 3CE8
Physical address | 0x2008 3CE8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs1_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS1_1

Address offset | 0x0 3CEC
Physical address | 0x2008 3CEC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs1_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS2_0

Address offset | 0x0 3CF0
Physical address | 0x2008 3CF0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs2_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS2_1

Address offset | 0x0 3CF4
Physical address | 0x2008 3CF4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs2_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS3_0

Address offset | 0x0 3CF8
Physical address | 0x2008 3CF8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs3_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS3_1

Address offset | 0x0 3CFC
Physical address | 0x2008 3CFC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs3_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS4_0

Address offset | 0x0 3D00
Physical address | 0x2008 3D00 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs4_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS4_1

Address offset | 0x0 3D04
Physical address | 0x2008 3D04 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs4_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS5_0

Address offset | 0x0 3D08
Physical address | 0x2008 3D08 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs5_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS5_1

Address offset | 0x0 3D0C
Physical address | 0x2008 3D0C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs5_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS6_0

Address offset | 0x0 3D10
Physical address | 0x2008 3D10 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs6_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS6_1

Address offset | 0x0 3D14
Physical address | 0x2008 3D14 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs6_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS7_0

Address offset | 0x0 3D18
Physical address | 0x2008 3D18 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs7_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS7_1

Address offset | 0x0 3D1C
Physical address | 0x2008 3D1C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs7_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS8_0

Address offset | 0x0 3D20
Physical address | 0x2008 3D20 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs8_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS8_1

Address offset | 0x0 3D24
Physical address | 0x2008 3D24 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs8_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS9_0

Address offset | 0x0 3D28
Physical address | 0x2008 3D28 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs9_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS9_1

Address offset | 0x0 3D2C
Physical address | 0x2008 3D2C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs9_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS10_0

Address offset | 0x0 3D30
Physical address | 0x2008 3D30 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs10_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS10_1

Address offset | 0x0 3D34
Physical address | 0x2008 3D34 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs10_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS11_0

Address offset | 0x0 3D38
Physical address | 0x2008 3D38 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs11_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS11_1

Address offset | 0x0 3D3C
Physical address | 0x2008 3D3C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs11_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS12_0

Address offset | 0x0 3D40
Physical address | 0x2008 3D40 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs12_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS12_1

Address offset | 0x0 3D44
Physical address | 0x2008 3D44 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs12_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS13_0

Address offset | 0x0 3D48
Physical address | 0x2008 3D48 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs13_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS13_1

Address offset | 0x0 3D4C
Physical address | 0x2008 3D4C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs13_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS14_0

Address offset | 0x0 3D50
Physical address | 0x2008 3D50 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs14_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS14_1

Address offset | 0x0 3D54
Physical address | 0x2008 3D54 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs14_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS15_0

Address offset | 0x0 3D58
Physical address | 0x2008 3D58 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_bit_map_index_cs15_0 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BIT_MAP_INDEX_CS15_1

Address offset | 0x0 3D5C
Physical address | 0x2008 3D5C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_bit_map_index_cs15_1 | Specifies mapping of DQ pins between memory controller and DRAM devices. When DQ pins are swizzled on circuit board or DIMM modules, the memory controller needs to take this into account when computing CRC values. This is typically done to simplify printed circuit board trace routing. Each 4 bit nibble may be swizzled in a different way. A 6 bit index specifies the swizzle mapping for each DQ nibble. The number of nibbles (n) is equal to the total number of DQ pins divided by 4. The index value specifies the swizzle mapping according to the JEDEC JC-45 SPD contents specification. In addition to index values 1-48 defined there, a value of 0 can be used to specify 1-to-1 mapping. | RW | 0x00 0000

### DDR_CSR_APB : CFG_NUM_LOGICAL_RANKS_PER_3DS

Address offset | 0x0 3D60
Physical address | 0x2008 3D60 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_num_logical_ranks_per_3ds | Indicates the number of logical ranks for each physical rank of DDR4 3DS devices. 0x0 Not DDR4 3DS devices 0x2 2H Stacked DDR4 devices 0x4 4H Stacked DDR4 devices 0x8 8H Stacked DDR4 devices | RW | 0x0

### DDR_CSR_APB : CFG_RFC_DLR1

Address offset | 0x0 3D64
Physical address | 0x2008 3D64 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_rfc_dlr1 | SDRAM refresh to activate or refresh command period between different logical ranks when in 1x fine granularity mode (tRFC_dlr1), specified in clocks. Only used for DDR4 3DS configurations. | RW | 0x048

### DDR_CSR_APB : CFG_RFC_DLR2

Address offset | 0x0 3D68
Physical address | 0x2008 3D68 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_rfc_dlr2 | SDRAM refresh to activate or refresh command period between different logical ranks when in 2x fine granularity mode (tRFC_dlr2), specified in clocks. Only used for DDR4 3DS configurations. | RW | 0x02C

### DDR_CSR_APB : CFG_RFC_DLR4

Address offset | 0x0 3D6C
Physical address | 0x2008 3D6C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_rfc_dlr4 | SDRAM refresh to activate or refresh command period between different logical ranks when in 4x fine granularity mode (tRFC_dlr4), specified in clocks. Only used for DDR4 3DS configurations. | RW | 0x020

### DDR_CSR_APB : CFG_RRD_DLR

Address offset | 0x0 3D70
Physical address | 0x2008 3D70 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_rrd_dlr | SDRAM ACTIVATE-to-ACTIVATE command period when activate following another activate is to a different 3DS logical rank (tRRD_dlr), specified in clocks. Only used for DDR4 3DS configurations. | RW | 0x4

### DDR_CSR_APB : CFG_FAW_DLR

Address offset | 0x0 3D74
Physical address | 0x2008 3D74 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved |  | RO | 0x000 0000
6:0 | cfg_faw_dlr | Four bank activate period to different logical ranks (tFAW_dlr), specified in clocks. Only used for DDR4 3DS configurations. | RW | 0x10

### DDR_CSR_APB : CFG_ADVANCE_ACTIVATE_READY

Address offset | 0x0 3D98
Physical address | 0x2008 3D98 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_advance_activate_ready | Number of DFI clocks to advance the assertion of the l_activate_ready. A value of 0 will cause the assertion of the l_activate_ready to occur on the clock cycle that the controller determines that a bank can be activated. Increasing values of cfg_advance_activate_ready will cause l_activate_ready signals to assert earlier. Deassertion of l_activate_ready will always occur 1 clocks after a request is placed into the queue for that bank, regardless of the cfg_advance_activate_ready setting. | RW | 0x0

### DDR_CSR_APB : CTRLR_SOFT_RESET_N

Address offset | 0x0 4000
Physical address | 0x2008 4000 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | ctrlr_soft_reset_n | Memory controller soft reset. Controller is in reset when this is set to 0. | RW | 0

### DDR_CSR_APB : CFG_LOOKAHEAD_PCH

Address offset | 0x0 4008
Physical address | 0x2008 4008 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_lookahead_pch | Look-ahead precharge enable. When enabled the controller will look ahead into the command queue and perform precharge and auto-precharge operations as early as possible in order to maximize command bus efficiency and reduce latency. It is recommended that this feature be disabled by hard connection of the port to '0' if the targeting the controller to FPGA running high internal timing frequencies. 0 - disable 1 - enable | RW | 1

### DDR_CSR_APB : CFG_LOOKAHEAD_ACT

Address offset | 0x0 400C
Physical address | 0x2008 400C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_lookahead_act | Look-ahead activate enable. When enabled, the controller will look ahead into the command queue and analyze the queued requests and perform activate operations as soon as possible in order to maximize bandwidth efficiency. It is recommended that this feature be disabled by hard connection of the port to '0' if the targeting the controller to FPGA running high internal timing frequencies. 0 - disable 1 - enable | RW | 1

### DDR_CSR_APB : INIT_AUTOINIT_DISABLE

Address offset | 0x0 4010
Physical address | 0x2008 4010 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_autoinit_disable | When set to '1', prevents the controller from generating the memory device initialization sequence. The user can then manually generate the initialization sequence using the remaining init_* controls. After the user has completed the initialization sequence, this signal must be set to '0'. This enables the controller to proceed to training and/or normal operation. | RW | 0

### DDR_CSR_APB : INIT_FORCE_RESET

Address offset | 0x0 4014
Physical address | 0x2008 4014 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_force_reset | Forces assertion of reset control signal (sd_reset_n) going to SDRAM. | RW | 0

### DDR_CSR_APB : INIT_GEARDOWN_EN

Address offset | 0x0 4018
Physical address | 0x2008 4018 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_geardown_en | When set, causes controller to use geardown command timing. Only applies to DDR4, and is ignored for all other memory types. | RW | 0

### DDR_CSR_APB : INIT_DISABLE_CKE

Address offset | 0x0 401C
Physical address | 0x2008 401C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_disable_cke | Forces de-assertion of clock enable signal going to SDRAM. | RW | 0

### DDR_CSR_APB : INIT_CS

Address offset | 0x0 4020
Physical address | 0x2008 4020 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | init_cs | Rank selection for mode register programming requests (using init_mr*), precharge-all requests (using init_precharge_all), refresh (using init_refresh), and ZQ calibration requests (using init_zq_cal_req) | RW | 0x00

### DDR_CSR_APB : INIT_PRECHARGE_ALL

Address offset | 0x0 4024
Physical address | 0x2008 4024 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_precharge_all | Issue Precharge-all command to memory devices on the ranks selected by init_cs. | RW | 0

### DDR_CSR_APB : INIT_REFRESH

Address offset | 0x0 4028
Physical address | 0x2008 4028 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_refresh | Issue Refresh command to memory devices on the ranks selected by init_cs. It is illegal to assert init_refresh when cfg_auto_ref_en is asserted and init_autoinit_disable is deasserted. | RW | 0

### DDR_CSR_APB : INIT_ZQ_CAL_REQ

Address offset | 0x0 402C
Physical address | 0x2008 402C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_zq_cal_req | User-initiated ZQ calibration request. Causes ZQ calibration to be issued at the next opportunity to the ranks specified by init_cs. The ZQ calibration will be issued to the ranks corresponding to the asserted bits. The function of this signal is similar to 'l_zq_cal_req'. The port is included here for purposes of user control during initialization (perhaps under software control), whereas 'l_zq_cal_req' is intended to be used after initialization by high-speed synchronous user logic. For those memory types that support it (such as DDR4) the type of ZQ calibration that is performed when this signal is asserted (ZQCL or ZQCS) is determined by 'cfg_zq_cal_type'. It is illegal to assert init_zq_cal_req when cfg_auto_zq_cal_en is asserted and init_autoinit_disable is deasserted. | RW | 0

### DDR_CSR_APB : INIT_ACK

Address offset | 0x0 4030
Physical address | 0x2008 4030 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_ack | Acknowledge for init_refresh, init_precharge_all, init_mr_w_req, init_zq_cal_req, init_zq_cal_start (LPDDR4) and init_nop. Cleared on read. | RO RtoClr | 0

### DDR_CSR_APB : CFG_BL

Address offset | 0x0 4034
Physical address | 0x2008 4034 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_bl | SDRAM maximum burst length (encoded). For "full-rate" configurations of the controller operating in DDR2, LPDDR2, LPDDR3 and HBM modes, values are decoded as follows: cfg_bl = 0x0 - 1 local side transfers / burst (2 DDR transfers) cfg_bl = 0x1 - 2 local side transfers / burst (4 DDR transfers) cfg_bl = 0x2 - 4 local side transfers / burst (8 DDR transfers) cfg_bl = 0x3 - 8 local side transfers / burst (16 DDR transfers) For "half-rate" configurations of the controller operating in DDR2, LPDDR2, LPDDR3 and HBM modes, values are decoded as follows: cfg_bl = 0x0 - Invalid cfg_bl = 0x1 - 1 local side transfer / burst (4 DDR transfers) cfg_bl = 0x2 - 2 local side transfers / burst (8 DDR transfers) cfg_bl = 0x3 - 4 local side transfers / burst (16 DDR transfers) For "quarter-rate" configurations of the controller operating in DDR2, LPDDR2, and LPDDR3, values are decoded as follows: cfg_bl = 0x0 - Invalid cfg_bl = 0x1 - Invalid cfg_bl = 0x2 - 2 local side transfers / burst (8 DDR transfers) cfg_bl = 0x3 - 4 local side transfers / burst (16 DDR transfers) For LPDDR2 memory types, only settings of 0x1 and 0x2 are allowed. For DDR2 memory type, only settings of 0x1 and 0x2 are allowed. For LPDDR3 memory type, only setting of 0x2 is allowed. For HBM memory type, only setting of 0x1 is allowed when operating in the half-rate configuration or when using an HBM Pseudo channel device. Settings of 0x0 and 0x1 are allowed when operating at full-rate with an HBM legacy device. | RW | 0x0

### DDR_CSR_APB : CTRLR_INIT

Address offset | 0x0 4038
Physical address | 0x2008 4038 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | ctrlr_init | Causes the SDRAM Controller Core to re-issue the initialization sequence to SDRAM devices. The initialization will begin when a 0-1 transition is detected on this signal. Note: The SDRAM Controller Core will always issue the initialization sequence (including the startup delay) after reset regardless of the 'ctrlr_init' state. This signal can be tied low if run-time re-initialization is not required. | RW | 0

### DDR_CSR_APB : CTRLR_INIT_DONE

Address offset | 0x0 403C
Physical address | 0x2008 403C | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | ctrlr_init_done | Deasserted when in reset or after ctrlr_init is asserted, then asserts when initialization sequence has completed. If manual initialization is performed (init_autoinit_disable asserted at startup), this signal will not assert until init_autoinit_disable is deasserted by the user, indicating that the manual initialization sequence has completed. | RO | 0

### DDR_CSR_APB : CFG_AUTO_REF_EN

Address offset | 0x0 4040
Physical address | 0x2008 4040 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_auto_ref_en | Enables controller initiated refresh cycles at a periodic rate determined by 'cfg_ref_per'. When this is set to '0', the user logic must take control of refresh by using special addressing techniques or by using the 'l_ref_req' input to manually generate refresh cycles. Controller will postpone a refresh if the memory bus is busy at the end of a 'cfg_ref_per' and will initiate the refresh when the memory bus is available. Up to 8 refresh requests can be postponed. If the 'cfg_auto_ref_en' is disabled, any postponed refresh requests will be cleared. | RW | 1

### DDR_CSR_APB : CFG_RAS

Address offset | 0x0 4044
Physical address | 0x2008 4044 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved |  | RO | 0x000 0000
6:0 | cfg_ras | SDRAM active to precharge (tRAS), specified in clocks. | RW | 0x1C

### DDR_CSR_APB : CFG_RCD

Address offset | 0x0 4048
Physical address | 0x2008 4048 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved |  | RO | 0x000 0000
6:0 | cfg_rcd | SDRAM active to read or write delay (tRCD), specified in memory clocks. For HBM2 and GDDR6 memory see cfg_rcd_rd, cfg_rcd_wr. | RW | 0x0B

### DDR_CSR_APB : CFG_RRD

Address offset | 0x0 404C
Physical address | 0x2008 404C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_rrd | SDRAM active bank A to active bank B (tRRD), specified in clocks. 'cfg_rp' must be greater than or equal to 'cfg_rrd'. | RW | 0x05

### DDR_CSR_APB : CFG_RP

Address offset | 0x0 4050
Physical address | 0x2008 4050 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | cfg_rp | SDRAM precharge command period (tRP), specified in clocks. 'cfg_rp' must be greater than or equal to 'cfg_rrd'. | RW | 0x0B

### DDR_CSR_APB : CFG_RC

Address offset | 0x0 4054
Physical address | 0x2008 4054 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_rc | SDRAM active to active / refresh command period (tRC), specified in clocks. | RW | 0x27

### DDR_CSR_APB : CFG_FAW

Address offset | 0x0 4058
Physical address | 0x2008 4058 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | reserved |  | RO | 0x00 0000
8:0 | cfg_faw | Four bank activate period (tFAW), specified in clocks | RW | 0x018

### DDR_CSR_APB : CFG_RFC

Address offset | 0x0 405C
Physical address | 0x2008 405C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_rfc | SDRAM refresh to active / refresh command period (tRFC) specified in clocks. | RW | 0x118

### DDR_CSR_APB : CFG_RTP

Address offset | 0x0 4060
Physical address | 0x2008 4060 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_rtp | SDRAM read to precharge delay (tRTP), specified in clocks | RW | 0x06

### DDR_CSR_APB : CFG_WR

Address offset | 0x0 4064
Physical address | 0x2008 4064 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | cfg_wr | SDRAM write recovery time (tWR), specified in clocks. If the calculated value is not available then the next higher value should be chosen. | RW | 0x0C

### DDR_CSR_APB : CFG_WTR

Address offset | 0x0 4068
Physical address | 0x2008 4068 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_wtr | SDRAM write to read command delay (tWTR), specified in clocks. | RW | 0x06

### DDR_CSR_APB : CFG_PASR

Address offset | 0x0 4070
Physical address | 0x2008 4070 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_pasr | Partial-Array Self Refresh (PASR) setting that written into PASR field of mode register during initialization. | RW | 0x0

### DDR_CSR_APB : CFG_XP

Address offset | 0x0 4074
Physical address | 0x2008 4074 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_xp | SDRAM exit power-down mode to first valid command (tXP), specified in clocks. | RW | 0x02

### DDR_CSR_APB : CFG_XSR

Address offset | 0x0 4078
Physical address | 0x2008 4078 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_xsr | SDRAM exit SELF REFRESH to next valid command delay (tXSR), specified in clocks. | RW | 0x002

### DDR_CSR_APB : CFG_CL

Address offset | 0x0 4080
Physical address | 0x2008 4080 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | cfg_cl | SDRAM CAS read latency, specified in clocks. Refer to SDRAM datasheet for list of supported values. | RW | 0x0B

### DDR_CSR_APB : CFG_READ_TO_WRITE

Address offset | 0x0 4088
Physical address | 0x2008 4088 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_read_to_write | Delay between the end of a read DQS postamble to the start of a write preamble, specified in memory clocks. The controller will delay issuing any write command immediately following a read command to achieve the turnaround time specified by this port. If 2 clock write preamble is being used, this value is specified relative to the middle of the 2 clock preamble. | RW | 0x2

### DDR_CSR_APB : CFG_WRITE_TO_WRITE

Address offset | 0x0 408C
Physical address | 0x2008 408C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_write_to_write | Delay between back-to-back writes which address different ranks of memory, specified in memory clocks. Specifically, this value is the minimum number of clocks between the end of the last data phase on the DQ bus of a write to one rank to the beginning of the first data phase on the DQ bus of a write to another rank. If SDRAM ODT is not used, this can be set to 0 since bus turnaround is not required between back-to-back writes which are switching ranks. | RW | 0x3

### DDR_CSR_APB : CFG_READ_TO_READ

Address offset | 0x0 4090
Physical address | 0x2008 4090 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_read_to_read | Bus turnaround delay between back-to-back reads which address different ranks of memory. Specifically, this value is the minimum number of memory clocks between the end of the last data phase on the DQ bus of a read to one rank to the beginning of the first data phase on the DQ bus of a read to another rank. A minimum value of 1 is required or else the DQS preamble of a read to a new rank will contend with the DQS postamble of the read from the previous rank. | RW | 0x3

### DDR_CSR_APB : CFG_WRITE_TO_READ

Address offset | 0x0 4094
Physical address | 0x2008 4094 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_write_to_read | For DDR2, DDR3, DDR4, LPDDR2, LPDDR3, LPDDR4 and HBM memory types, this is the delay between the end of a write DQS postamble to the start of a read preamble when the read and write commands are to different ranks. If 2 clock read preamble is being used (for memory types that support it) this value is specified relative to the middle of the 2 clock preamble. Value is specified in memory clocks. The controller will delay issuing any read command immediately following a write command to achieve the turnaround time specified by this port. When a read follows a write and the read and write commands are to the same rank, the turnaround is specified by cfg_wtr. | RW | 0x02

### DDR_CSR_APB : CFG_READ_TO_WRITE_ODT

Address offset | 0x0 4098
Physical address | 0x2008 4098 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_read_to_write_odt | Delay between the end of a read DQS postamble to the start of a write preamble, specified in memory clocks, when the ODT signals need to change as dictated by the settings of cfg_odt_wr_map_csN and cfg_odt_rd_map_csN. The controller will delay issuing any write command immediately following a read command to achieve the turnaround time specified by this port. If 2 clock write preamble is being used, this value is specified relative to the middle of the 2 clock preamble. | RW | 0x2

### DDR_CSR_APB : CFG_WRITE_TO_WRITE_ODT

Address offset | 0x0 409C
Physical address | 0x2008 409C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_write_to_write_odt | Delay between back-to-back writes which address different ranks of memory, specified in memory clocks, when the ODT signals need to change as dictated by the settings of cfg_odt_wr_map_csN. Specifically, this value is the minimum number of clocks between the end of the last data phase on the DQ bus of a write to one rank to the beginning of the first data phase on the DQ bus of a write to another rank, where the write ODT settings are different between the two ranks. If SDRAM ODT is not used, this can be set to 0 since bus turnaround is not required between back-to-back writes which are switching ranks. Larger values are required to allow ODT to be properly established (as specified by the cfg_odt_wr_map_csN termination matrix) before the write to the new rank begins. | RW | 0x3

### DDR_CSR_APB : CFG_READ_TO_READ_ODT

Address offset | 0x0 40A0
Physical address | 0x2008 40A0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_read_to_read_odt | Bus turnaround delay between back-to-back reads which address different ranks of memory, when the ODT signals need to change as dictated by the settings of cfg_odt_rd_map_csN. Specifically, this value is the minimum number of memory clocks between the end of the last data phase on the DQ bus of a read to one rank to the beginning of the first data phase on the DQ bus of a read to another rank, where the read ODT settings are different between the two ranks. A minimum value of 1 is required or else the DQS preamble of a read to a new rank will contend with the DQS postamble of the read from the previous rank. Larger values are desired when SDRAM ODT is used to allow ODT to be properly established (as specified by the cfg_odt_rd_map_csN termination matrix) before the read to the new rank begins. | RW | 0x3

### DDR_CSR_APB : CFG_WRITE_TO_READ_ODT

Address offset | 0x0 40A4
Physical address | 0x2008 40A4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_write_to_read_odt | Delay between the end of a write DQS postamble to the start of a read preamble when the read and write commands are to different ranks and the ODT signals need to change as dictated by the settings of cfg_odt_wr_map_csN and cfg_odt_rd_map_csN. Value is specified in memory clocks. The controller will delay issuing any read command immediately following a write command to achieve the turnaround time specified by this port. When a read follows a write and the read and write commands are to the same rank, the turnaround is specified by cfg_wtr. If 2 clock read preamble is being used, this value is specified relative to the middle of the 2 clock preamble. | RW | 0x02

### DDR_CSR_APB : CFG_MIN_READ_IDLE

Address offset | 0x0 40A8
Physical address | 0x2008 40A8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_min_read_idle | Minimum number of clocks of idle time on the bus between non-consecutive read commands. If any two reads are not back-to-back, this is the minimum idle time (in clocks) on the data bus between the reads. Values of 0 and 1 cause no minimum bus idle time between non-consecutive reads to be enforced. There is no difference in behavior between the 0 and 1 settings. This setting is useful for interfacing with physical interfaces which require bus idle time to reset in between reads. | RW | 0x0

### DDR_CSR_APB : CFG_MRD

Address offset | 0x0 40AC
Physical address | 0x2008 40AC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved |  | RO | 0x000 0000
6:0 | cfg_mrd | SDRAM load mode register command to active or refresh command (tMRD), specified in clocks. | RW | 0x0C

### DDR_CSR_APB : CFG_BT

Address offset | 0x0 40B0
Physical address | 0x2008 40B0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_bt | SDRAM burst type written into "read burst type" field of mode register during initialization sequence. 0 - sequential (typical) 1 - interleaved | RW | 0

### DDR_CSR_APB : CFG_DS

Address offset | 0x0 40B4
Physical address | 0x2008 40B4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_ds | Output driver strength setting programmed into "Output Driver Impedance Control", "Pull-down Drive Strength" or "Driver Strength" field of mode register during initialization sequence. Refer to SDRAM datasheet for mapping to impedance values. Bits 2 and 3 are ignored for DDR4 and GDDR6 devices. Bit 3 ignored for LPDDR4 devices. | RW | 0x0

### DDR_CSR_APB : CFG_QOFF

Address offset | 0x0 40B8
Physical address | 0x2008 40B8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_qoff | SDRAM output enable function. This signal is written to output buffer mode (Qoff) mode register bit during initialization. Typically set to '0' to enable data and strobe outputs from the SDRAM devices. Can be set to '1' for IDD characterization of read current. | RW | 0

### DDR_CSR_APB : CFG_RTT

Address offset | 0x0 40C4
Physical address | 0x2008 40C4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_rtt | ODT effective resistance Rtt. On-Die Termination effective resistance setting programmed into "RTT_NOM" field of mode register during initialization sequence. Refer to SDRAM device datasheet for the mapping to impedance values. | RW | 0x1

### DDR_CSR_APB : CFG_DLL_DISABLE

Address offset | 0x0 40C8
Physical address | 0x2008 40C8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_dll_disable | Memory device DLL disable. Controls programming of "DLL Enable" field of mode register during initialization sequence. 0 - enable DLL 1 - disable DLL | RW | 0

### DDR_CSR_APB : CFG_REF_PER

Address offset | 0x0 40CC
Physical address | 0x2008 40CC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved |  | RO | 0x0000
15:0 | cfg_ref_per | Period between refresh commands issued by the controller, specified in clocks. This value is calculated as: cfg_ref_per = required refresh time interval / tCK If cfg_only_srank_cmds is set to 1 and cfg_quad_rank is set to 0, then the internal refresh interval calculated by the controller will be cfg_ref_per divided by the number of ranks in the system (cfg_num_ranks) since each refresh event will only be refreshing one rank. In this case the internal refresh interval is calculated as: refresh interval = cfg_ref_per / cfg_num_ranks With cfg_only_srank_cmds set to 1 and cfg_quad_rank set to 0, the controller supports cfg_num_ranks settings of 1, 2, 3, 4, 6, 8, or 16. If cfg_only_srank_cmds is set to 1 and cfg_quad_rank is set to 1, then the internal refresh interval calculated by the controller will be cfg_ref_per divided by one-half the number of ranks in the system (cfg_num_ranks) since each refresh event will refresh two ranks (due to cfg_quad_rank). In this case the internal refresh interval is calculated as: refresh interval = cfg_ref_per / ( cfg_num_ranks / 2 ) With cfg_only_srank_cmds set to 1 and cfg_quad_rank set to 1, the controller supports cfg_num_ranks settings of 4, 8, or 16. | RW | 0x1860

### DDR_CSR_APB : CFG_STARTUP_DELAY

Address offset | 0x0 40D0
Physical address | 0x2008 40D0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:19 | reserved |  | RO | 0x0000
18:0 | cfg_startup_delay | Delay after a reset event that the controller waits before initializing the SDRAM, specified in clocks. The NWL controller supports 4 initialization modes: (1) Phy does all of the DRAM initialization (cfg_startup_delay is a don't care and cfg_ctrlr_init_disable is set to 1) and the NWL controller just waits for dfi_init_complete/dfi_training_complete to be asserted before beginning normal operation (generating refresh requests, etc.) (2) Software does all of the DRAM initialization (cfg_startup delay is a don't care and init_autoinit_disable is set to 1) and the NWL controller just waits for dfi_init_complete/dfi_training_complete to be asserted before beginning normal operation (generating refresh requests, etc.) (3) NWL controller does all of the DRAM initialization (cfg_startup_delay != 0 and phy/software initialization modes are not defined) and then waits for dfi_init_complete/dfi_training_complete to be asserted before beginning normal operation (generating refresh requests, etc.) (4) The phy does all of the early CKE/memory reset initialization of the memory (cfg_startup_delay = 0 and phy/software initialization modes are not defined) and the NWL controller waits for dfi_init_complete/dfi_training_complete to be asserted before sequencing out the final mode registers settings and beginning normal operation (generating refresh requests, etc.) | RW | 0x2 7100

### DDR_CSR_APB : CFG_MEM_COLBITS

Address offset | 0x0 40D4
Physical address | 0x2008 40D4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_mem_colbits | Number of bits in the column address. | RW | 0xB

### DDR_CSR_APB : CFG_MEM_ROWBITS

Address offset | 0x0 40D8
Physical address | 0x2008 40D8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_mem_rowbits | Number of bits in the row address. | RW | 0x10

### DDR_CSR_APB : CFG_MEM_BANKBITS

Address offset | 0x0 40DC
Physical address | 0x2008 40DC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_mem_bankbits | Number of bits in the bank address (including DDR4/HBM bank group bits). For HBM pseudo channel memory, the pseudo channel select bit (BA4 in the JEDEC specification) does not count as a bank bit. If using an 8HI stack, the SID address bit counts as another bank group bit. Thus when using an HBM 8HI stack the cfg_mem_bankbits should be set to 5 (= 4 + 1) . | RW | 0x3

### DDR_CSR_APB : CFG_ODT_RD_MAP_CS0

Address offset | 0x0 40E0
Physical address | 0x2008 40E0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_rd_map_cs0 | ODT selection matrix for reads. Selects which ODT outputs are enabled when reading from each chip select. For example, if cfg_odt_rd_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a read from memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_rd_map_cs8 through cfg_odt_rd_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x02

### DDR_CSR_APB : CFG_ODT_RD_MAP_CS1

Address offset | 0x0 40E4
Physical address | 0x2008 40E4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_rd_map_cs1 | ODT selection matrix for reads. Selects which ODT outputs are enabled when reading from each chip select. For example, if cfg_odt_rd_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a read from memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_rd_map_cs8 through cfg_odt_rd_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x01

### DDR_CSR_APB : CFG_ODT_RD_MAP_CS2

Address offset | 0x0 40E8
Physical address | 0x2008 40E8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_rd_map_cs2 | ODT selection matrix for reads. Selects which ODT outputs are enabled when reading from each chip select. For example, if cfg_odt_rd_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a read from memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_rd_map_cs8 through cfg_odt_rd_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x08

### DDR_CSR_APB : CFG_ODT_RD_MAP_CS3

Address offset | 0x0 40EC
Physical address | 0x2008 40EC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_rd_map_cs3 | ODT selection matrix for reads. Selects which ODT outputs are enabled when reading from each chip select. For example, if cfg_odt_rd_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a read from memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_rd_map_cs8 through cfg_odt_rd_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x04

### DDR_CSR_APB : CFG_ODT_RD_MAP_CS4

Address offset | 0x0 40F0
Physical address | 0x2008 40F0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_rd_map_cs4 | ODT selection matrix for reads. Selects which ODT outputs are enabled when reading from each chip select. For example, if cfg_odt_rd_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a read from memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_rd_map_cs8 through cfg_odt_rd_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x20

### DDR_CSR_APB : CFG_ODT_RD_MAP_CS5

Address offset | 0x0 40F4
Physical address | 0x2008 40F4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_rd_map_cs5 | ODT selection matrix for reads. Selects which ODT outputs are enabled when reading from each chip select. For example, if cfg_odt_rd_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a read from memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_rd_map_cs8 through cfg_odt_rd_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x10

### DDR_CSR_APB : CFG_ODT_RD_MAP_CS6

Address offset | 0x0 40F8
Physical address | 0x2008 40F8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_rd_map_cs6 | ODT selection matrix for reads. Selects which ODT outputs are enabled when reading from each chip select. For example, if cfg_odt_rd_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a read from memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_rd_map_cs8 through cfg_odt_rd_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x80

### DDR_CSR_APB : CFG_ODT_RD_MAP_CS7

Address offset | 0x0 40FC
Physical address | 0x2008 40FC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_rd_map_cs7 | ODT selection matrix for reads. Selects which ODT outputs are enabled when reading from each chip select. For example, if cfg_odt_rd_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a read from memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_rd_map_cs8 through cfg_odt_rd_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x40

### DDR_CSR_APB : CFG_ODT_WR_MAP_CS0

Address offset | 0x0 4120
Physical address | 0x2008 4120 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_wr_map_cs0 | ODT selection matrix for writes. Selects which ODT outputs are enabled when writing to each chip select. For example, if cfg_odt_wr_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a write to memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_wr_map_cs8 through cfg_odt_wr_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x01

### DDR_CSR_APB : CFG_ODT_WR_MAP_CS1

Address offset | 0x0 4124
Physical address | 0x2008 4124 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_wr_map_cs1 | ODT selection matrix for writes. Selects which ODT outputs are enabled when writing to each chip select. For example, if cfg_odt_wr_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a write to memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_wr_map_cs8 through cfg_odt_wr_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x02

### DDR_CSR_APB : CFG_ODT_WR_MAP_CS2

Address offset | 0x0 4128
Physical address | 0x2008 4128 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_wr_map_cs2 | ODT selection matrix for writes. Selects which ODT outputs are enabled when writing to each chip select. For example, if cfg_odt_wr_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a write to memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_wr_map_cs8 through cfg_odt_wr_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x04

### DDR_CSR_APB : CFG_ODT_WR_MAP_CS3

Address offset | 0x0 412C
Physical address | 0x2008 412C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_wr_map_cs3 | ODT selection matrix for writes. Selects which ODT outputs are enabled when writing to each chip select. For example, if cfg_odt_wr_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a write to memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_wr_map_cs8 through cfg_odt_wr_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x08

### DDR_CSR_APB : CFG_ODT_WR_MAP_CS4

Address offset | 0x0 4130
Physical address | 0x2008 4130 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_wr_map_cs4 | ODT selection matrix for writes. Selects which ODT outputs are enabled when writing to each chip select. For example, if cfg_odt_wr_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a write to memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_wr_map_cs8 through cfg_odt_wr_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x10

### DDR_CSR_APB : CFG_ODT_WR_MAP_CS5

Address offset | 0x0 4134
Physical address | 0x2008 4134 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_wr_map_cs5 | ODT selection matrix for writes. Selects which ODT outputs are enabled when writing to each chip select. For example, if cfg_odt_wr_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a write to memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_wr_map_cs8 through cfg_odt_wr_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x20

### DDR_CSR_APB : CFG_ODT_WR_MAP_CS6

Address offset | 0x0 4138
Physical address | 0x2008 4138 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_wr_map_cs6 | ODT selection matrix for writes. Selects which ODT outputs are enabled when writing to each chip select. For example, if cfg_odt_wr_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a write to memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_wr_map_cs8 through cfg_odt_wr_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x40

### DDR_CSR_APB : CFG_ODT_WR_MAP_CS7

Address offset | 0x0 413C
Physical address | 0x2008 413C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_odt_wr_map_cs7 | ODT selection matrix for writes. Selects which ODT outputs are enabled when writing to each chip select. For example, if cfg_odt_wr_cs0 is set to '00001100', then sd_odt[2] and sd_odt[3] will be asserted during a write to memory devices on chip select 0. If the controller is configured to support 8 ranks, the width of each port will be 8 bits and cfg_odt_wr_map_cs8 through cfg_odt_wr_map_cs15 will be unused. If the controller is configured to support 16 ranks, the width of each port will be 16 bits. | RW | 0x80

### DDR_CSR_APB : CFG_ODT_RD_TURN_ON

Address offset | 0x0 4160
Physical address | 0x2008 4160 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_odt_rd_turn_on | Allows timing adjustments for the ODT signals during reads. Value is expressed in two's compliment form and represents the amount of shift from the nominal value of ODT turn-on and turn-off timing during reads. -8 ('b1000) - negative shift of 8 clocks ... -1 ('b1111) - negative shift of 1 clock 0 ('b0000) - use standard ODT timing 1 ('b0001) - positive shift of transition timing ... 7 ('b0111) - positive shift of 7 clocks Typically only a value of '0' will be used. However, negative values can be used to advance the turn-on relative to the nominal, while positive values will delay it. | RW | 0x0

### DDR_CSR_APB : CFG_ODT_WR_TURN_ON

Address offset | 0x0 4164
Physical address | 0x2008 4164 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_odt_wr_turn_on | Allows timing adjustments for the ODT signals during writes. Value is expressed in two's compliment form and represents the amount of shift from the nominal value of ODT turn-on and turn-off timing during writes. -8 ('b1000) - negative shift of 8 clocks ... -1 ('b1111) - negative shift of 1 clock 0 ('b0000) - use standard ODT timing 1 ('b0001) - positive shift of transition timing ... 7 ('b0111) - positive shift of 7 clocks Typically only a value of '0' will be used. However, negative values can be used to advance the turn-on relative to the nominal, while positive values will delay it. | RW | 0x0

### DDR_CSR_APB : CFG_ODT_RD_TURN_OFF

Address offset | 0x0 4168
Physical address | 0x2008 4168 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_odt_rd_turn_off | See description for cfg_odt_rd_turn_on. | RW | 0x0

### DDR_CSR_APB : CFG_ODT_WR_TURN_OFF

Address offset | 0x0 416C
Physical address | 0x2008 416C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_odt_wr_turn_off | See description for cfg_odt_wr_turn_on. | RW | 0x0

### DDR_CSR_APB : CFG_EMR3

Address offset | 0x0 4178
Physical address | 0x2008 4178 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved |  | RO | 0x0000
15:0 | cfg_emr3 | Value programmed into Extended Mode Register 3 during initialization for DDR2 and DDR3 memory types. Typically this is set to 0. This port is provided in case additional bits are defined in this mode register at a future time. This field is ignored for all memory types other than DDR2 and DDR3. | RW | 0x0000

### DDR_CSR_APB : CFG_TWO_T

Address offset | 0x0 417C
Physical address | 0x2008 417C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_two_t | Two cycle timing (2T) enable. When enabled, the controller extends the duration of all signals in the SDRAM address and control bus, except 'sd_cs_n' to be two clock cycles. 'sd_cs_n' is only asserted on either the first or second cycle, as specified by 'cfg_two_t_sel_cycle'. 2T timing is not supported when cfg_regdimm is set to '1'. 0 - disable 1 - enable For half-rate or quarter-rate memory controller configurations this must be set to 0. For half-rate configurations 2T timing is provided automatically. For quarter-rate configurations 4T timing is provided automatically. | RW | 0

### DDR_CSR_APB : CFG_TWO_T_SEL_CYCLE

Address offset | 0x0 4180
Physical address | 0x2008 4180 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_two_t_sel_cycle | Controls which memory clock cycle of a multi-cycle command that cs_n is asserted on. For full-rate configurations: 0 - cs_n asserted during the first cycle 1 - cs_n asserted during the second cycle This setting is ignored if 'cfg_two_t' is set to 0. For half-rate configurations: 0 - cs_n asserted during the first cycle. For DDR4, cs_n assertion may occur on the second cycle unless 'cfg_ccd_l' and 'cfg_ccd_s' settings are even numbers. Additionally, if write CRC is enabled 'cfg_ccd_s' must be set to 6. 1 - cs_n asserted during the second cycle. When this setting is used with DDR4, 'cfg_ccd_l' and 'cfg_ccd_s' settings must be even numbers. Additionally, if write CRC is enabled, 'cfg_ccd_s' must be set to 6. 'cfg_two_t' must be set to 0 for half-rate configurations. For quarter-rate configurations: 0 - cs_n asserted during the first cycle 1 - cs_n asserted during the third cycle 'cfg_two_t' must be set to 0 for quarter-rate configurations. | RW | 0

### DDR_CSR_APB : CFG_REGDIMM

Address offset | 0x0 4184
Physical address | 0x2008 4184 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_regdimm | Set when using Registered DIMMs (RDIMMs) and Load-Reduced DIMMs (LRDIMMs). When using RDIMMs or LRDIMMs, 'cfg_rdimm_lat' typically needs to be set to a value corresponding to the number of clocks the DIMM register device adds to the command/address path. For DDR3 RDIMMs and LRDIMMs, cfg_only_srank_cmds also needs to be set to prevent multiple chip selects from asserting simultaneously (which can be interpreted by DDR3 register devices as a control word write). | RW | 0

### DDR_CSR_APB : CFG_MOD

Address offset | 0x0 4188
Physical address | 0x2008 4188 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_mod | SDRAM Mode Register Set command to any command (tMOD), specified in clocks. Min=24 for DDR4, 15 for HBM | RW | 0x0C

### DDR_CSR_APB : CFG_XS

Address offset | 0x0 418C
Physical address | 0x2008 418C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_xs | SDRAM exit self-refresh to non-DLL command (tXS), specified in clocks. | RW | 0x120

### DDR_CSR_APB : CFG_XSDLL

Address offset | 0x0 4190
Physical address | 0x2008 4190 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved |  | RO | 0x00 0000
10:0 | cfg_xsdll | SDRAM exit self-refresh to any command requiring a locked DLL (tXSDLL), specified in clocks. Refer to memory device datasheet for the minimum required value based on the speed grade being used. If minimizing self-refresh exit time is not important to system performance (or if self-refresh is not being used) then a value that is larger than specified minimum can be used. For DDR3, a value of 512 exceeds the minimum required value for all speed grades. For DDR4, a value of 1024 exceeds the minimum required value for all speed grades. | RW | 0x200

### DDR_CSR_APB : CFG_XPR

Address offset | 0x0 4194
Physical address | 0x2008 4194 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_xpr | Delay from CKE high to valid command, after exiting reset (tXPR). Specified in clocks. | RW | 0x120

### DDR_CSR_APB : CFG_AL_MODE

Address offset | 0x0 4198
Physical address | 0x2008 4198 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_al_mode | Additive latency mode 0 - Additive Latency Disabled (AL = 0) 1 - AL = CL - 1 (not valid for 3DS DDR4 SDRAM) 2 - AL = CL - 2 3 - AL = CL - 3 (only valid for 3DS DDR4 SDRAM) | RW | 0x0

### DDR_CSR_APB : CFG_CWL

Address offset | 0x0 419C
Physical address | 0x2008 419C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_cwl | SDRAM CAS write latency, specified in clocks. Refer to SDRAM datasheet for list of supported values. | RW | 0x08

### DDR_CSR_APB : CFG_BL_MODE

Address offset | 0x0 41A0
Physical address | 0x2008 41A0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_bl_mode | SDRAM burst length mode. This value sets the DDR3 or DDR4 burst length mode. The burst length mode determines the number of DDR transfers per burst. For "full-rate" configurations of the controller, values are decoded as follows: cfg_bl_mode = 0x0 - Fixed BL8 mode. 8 DDR transfers, 4 local side transfers per request cfg_bl_mode = 0x1 - BL8 or BC4 with on-the-fly selection cfg_bl_mode = 0x2 - Fixed BC4 (chop) (NOT CURRENTLY SUPPORTED) For "half-rate" configurations of the controller, values are decoded as follows: cfg_bl_mode = 0x0 - Fixed BL8 mode. 8 DDR transfers, 2 local side transfers per request cfg_bl_mode = 0x1 - BL8 or BC4 with on-the-fly selection cfg_bl_mode = 0x2 - Fixed BC4 (chop) (NOT CURRENTLY SUPPORTED) For "quarter-rate" configurations of the controller, there is only 1 local side transfer per request. Therefore, only one mode is supported: cfg_bl_mode = 0x0 - Fixed BL8 mode. 8 DDR transfers, 1 local side transfers per request cfg_bl_mode = 0x1 - BL8 or BC4 with on-the-fly selection (NOT SUPPORTED) cfg_bl_mode = 0x2 - Fixed BC4 (chop) (NOT SUPPORTED) Note: Refer to the SDRAM Controller Core User Guide for information on using non-aligned starting addresses with each burst length setting. | RW | 0x0

### DDR_CSR_APB : CFG_TDQS

Address offset | 0x0 41A4
Physical address | 0x2008 41A4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_tdqs | Termination DQS enable. This signal is written into "TDQS enable" field of mode register during initialization sequence. Enables or disables the TDQS pin on all devices 0 - disable TDQS / enable data mask functionality 1 - enable TDQS / disable data mask functionality | RW | 0

### DDR_CSR_APB : CFG_RTT_WR

Address offset | 0x0 41A8
Physical address | 0x2008 41A8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_rtt_wr | Dynamic ODT effective resistance (Rtt_wr). On-Die Termination effective resistance setting programmed into "RTT_WR" field of mode register during initialization sequence. Refer to SDRAM device datasheet for the mapping to impedance values. | RW | 0x0

### DDR_CSR_APB : CFG_LP_ASR

Address offset | 0x0 41AC
Physical address | 0x2008 41AC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_lp_asr | Low Power Array Self Refresh (LP ASR) setting, DDR4 ONLY. Programmed into SDRAM device Mode Register during initialization sequence. Refer to SDRAM device datasheet for more information on LP_ASR. | RW | 0x0

### DDR_CSR_APB : CFG_AUTO_SR

Address offset | 0x0 41B0
Physical address | 0x2008 41B0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_auto_sr | Auto Self Refresh (ASR) setting, DDR3 ONLY. Programmed into SDRAM device Mode Register during initialization sequence. Refer to SDRAM device datasheet for more information on ASR. | RW | 0

### DDR_CSR_APB : CFG_SRT

Address offset | 0x0 41B4
Physical address | 0x2008 41B4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_srt | Self Refresh Temperature (SRT) setting, DDR3 ONLY. Programmed into SDRAM device Mode Register during initialization sequence. Refer to SDRAM device datasheet for more information on SRT. | RW | 0

### DDR_CSR_APB : CFG_ADDR_MIRROR

Address offset | 0x0 41B8
Physical address | 0x2008 41B8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_addr_mirror | Each bit is associated with the respective rank (bit 0 = rank 0, bit 7 = rank 7). If the bit is high, it indicates to the controller that that rank is using address mirroring on the DIMM layout. | RW | 0x00

### DDR_CSR_APB : CFG_ZQ_CAL_TYPE

Address offset | 0x0 41BC
Physical address | 0x2008 41BC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_zq_cal_type | Type of ZQ calibration to be performed during automatic periodic ZQ calibrations or when user asserts 'l_zq_cal_req' or 'init_zq_cal_req'. Only used for DDR3, DDR4, LPDDR2, and LPDDR3 memory types. 0 - Short ZQ calibration (DDR3/DDR4/LPDDR2/LPDDR3) - The controller issues short ZQ-cal command and holds off subsequent commands until the delay specified by 'cfg_zq_cal_s_duration' is satisfied. 1 - Long ZQ calibration (DDR3/DDR4/LPDDR2/LPDDR3) - The controller issues a long ZQ-cal command and holds off subsequent commands until the delay specified by 'cfg_zq_cal_l_duration' is satisfied. 2 - Reset ZQ calibration (LPDDR2/LPDDR3) - The controller issues a reset ZQ-cal command and holds off subsequent commands until the delay specified by 'cfg_zq_cal_r_duration' is satisfied. 3 - Initialization ZQ calibration (LPDDR2/LPDDR3/DDR3/DDR4) - The controller issues a ZQINIT command (LPDDR2/LPDDR3) or long ZQ-cal command (DDR3/DDR4) and holds off subsequent commands until the delay specified by 'cfg_zqinit_cal_duration' is satisfied. | RW | 0x0

### DDR_CSR_APB : CFG_ZQ_CAL_PER

Address offset | 0x0 41C0
Physical address | 0x2008 41C0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_zq_cal_per | Period between automatic ZQ calibration commands issued by the controller, specified in memory clocks. The ZQ calibration is performed on a single rank at a time. Therefore the period between ZQ calibration commands in the system is the period specified divided by the number of ranks in the system (cfg_num_ranks). In this way each rank receives a ZQ calibration once per cfg_zq_cal_per. | RW | 0x0000 3F40

### DDR_CSR_APB : CFG_AUTO_ZQ_CAL_EN

Address offset | 0x0 41C4
Physical address | 0x2008 41C4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_auto_zq_cal_en | Enables automatic generation of ZQ calibration commands at a periodic rate determined by 'cfg_zq_cal_per'. When this is set to '0', the user logic must initiate periodic ZQ calibrations manually using the 'l_zq_cal_req' input. | RW | 1

### DDR_CSR_APB : CFG_MEMORY_TYPE

Address offset | 0x0 41C8
Physical address | 0x2008 41C8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved |  | RO | 0x0000
15:0 | cfg_memory_type | Applies to multi-mode memory controller configurations only. Selects memory type being used. 0x0004 = DDR2 0x0008 = DDR3 0x0020 = LPDDR2 0x0040 = RL3 0x0080 = DDR4 0x0100 = LPDDR3 0x0400 = LPDDR4 0x0800 = HBM2 legacy emulation using Pseudo channel memory 0x1000 = HBM2 native Pseudo channel memory 0x2000 = LL-HBM2 Pseudo channel memory | RW | 0x0008

### DDR_CSR_APB : CFG_ONLY_SRANK_CMDS

Address offset | 0x0 41CC
Physical address | 0x2008 41CC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_only_srank_cmds | When set, controller only issues commands to one rank at a time (i.e. only one chip select is ever asserted). Reasons for setting this include: 1) Use of DDR3 RDIMMs and DDR3 LRDIMMs. This must be set for DDR3 RDIMMs and DDR3 LRDIMMs since they do not allow commands to be issued to multiple ranks simultaneously. 2) Staggered refresh commands to reduce instantaneous current draw. 3) Enable read/write commands while other ranks are being refreshed. To utilize this, the user logic must be aware of which rank is about to be refreshed and avoid requests to that rank. When this is set, the refresh period provided on 'cfg_ref_per' will be divided internally in the controller by the number of ranks in the system (as specified by 'cfg_num_ranks') since each refresh event is only refreshing one rank. See the cfg_ref_per register description for details. | RW | 0

### DDR_CSR_APB : CFG_NUM_RANKS

Address offset | 0x0 41D0
Physical address | 0x2008 41D0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_num_ranks | Number of ranks in system. Used by ZQ-calibration and when cfg_only_srank_cmds is set to determine which ranks to cycle through for refresh and ZQ-calibration commands. | RW | 0x02

### DDR_CSR_APB : CFG_QUAD_RANK

Address offset | 0x0 41D4
Physical address | 0x2008 41D4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_quad_rank | Set to indicate configuration with DIMMs that have four ranks. Quad-rank DIMMs expose two CKE pins, each driving two ranks. When this port is set to '1', ranks will only be put into power down and self-refresh in pairs which share CKE pins. | RW | 0

### DDR_CSR_APB : CFG_EARLY_RANK_TO_WR_START

Address offset | 0x0 41DC
Physical address | 0x2008 41DC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_early_rank_to_wr_start | Controls timing behavior of dfi_wrdata_cs_pN relative to dfi_wrdata_en_pN. When set to 0, dfi_wrdata_cs_pN is guaranteed to be valid only while dfi_wrdata_en_pN is asserted. When set to 1, dfi_wrdata_cs_pN will also be guaranteed valid 1 DFI clock cycle prior to dfi_wrdata_en_pN, and will remain valid while dfi_wrdata_en_pN is valid. A value of 1 may cause the controller to delay a write to a different rank from the previous write in order to guarantee this timing. Some PHYs require a setting of 1 so that there is time for rank-specific delay values to be switched in prior to the start of data transfer on the DRAM bus. Only values of 1 and 0 are permitted. | RW | 0x0

### DDR_CSR_APB : CFG_EARLY_RANK_TO_RD_START

Address offset | 0x0 41E0
Physical address | 0x2008 41E0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_early_rank_to_rd_start | Controls timing behavior of dfi_rddata_cs_pN relative to dfi_rddata_en_pN. When set to 0, dfi_rddata_cs_pN is guaranteed to be valid only while dfi_rddata_en_pN is asserted. When set to 1, dfi_rddata_cs_pN will also be guaranteed valid 1 DFI clock cycle prior to dfi_rddata_en_pN, and will remain valid while dfi_rddata_en_pN is valid. A value of 1 may cause the controller to delay a read to a different rank from the previous read in order to guarantee this timing. Some PHYs require a setting of 1 so that there is time for rank-specific delay values to be switched in prior to the start of data transfer on the DRAM bus. Only values of 1 and 0 are permitted. | RW | 0x0

### DDR_CSR_APB : CFG_PASR_BANK

Address offset | 0x0 41E4
Physical address | 0x2008 41E4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_pasr_bank | Partial-Array Self-Refresh Bank Mask settings programmed into the Mode Register. | RW | 0x00

### DDR_CSR_APB : CFG_PASR_SEG

Address offset | 0x0 41E8
Physical address | 0x2008 41E8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_pasr_seg | Partial-Array Self-Refresh Segment Mask settings programmed into the Mode Register. | RW | 0x00

### DDR_CSR_APB : INIT_MRR_MODE

Address offset | 0x0 41EC
Physical address | 0x2008 41EC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_mrr_mode | Set to direct SDRAM controller to issue mode register read commands for subsequent read accesses. It is recommended that this only be asserted when init_cal_select = 1'b1, or when the controller is idle (no other read/write activity in progress). | RW | 0

### DDR_CSR_APB : INIT_MR_W_REQ

Address offset | 0x0 41F0
Physical address | 0x2008 41F0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_mr_w_req | Mode register write request. Initiates a mode register program to the mode register specified by init_mr_addr and rank(s) specified by init_cs. Assertion of init_ack signals the completion of the operation. All banks must be closed prior to making this request. This may be done using the init_precharge register. | RW | 0

### DDR_CSR_APB : INIT_MR_ADDR

Address offset | 0x0 41F4
Physical address | 0x2008 41F4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | init_mr_addr | Mode register address to be written to when init_mr_w_req is asserted. | RW | 0x00

### DDR_CSR_APB : INIT_MR_WR_DATA

Address offset | 0x0 41F8
Physical address | 0x2008 41F8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:18 | reserved |  | RO | 0x0000
17:0 | init_mr_wr_data | Value to be programmed into mode register. For HBM only bits 7 to 0 are used (OP7 = init_mr_wrdata[7],... OP0 = init_mr_wrdata[0]). | RW | 0x0 0000

### DDR_CSR_APB : INIT_MR_WR_MASK

Address offset | 0x0 41FC
Physical address | 0x2008 41FC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:18 | reserved |  | RO | 0x0000
17:0 | init_mr_wr_mask | Mask for mode register writes. Mode register bits corresponding to bits asserted in this bus will be sourced from settings on cfg_* inputs to the controller rather than the init_mr_wr_data bus. | RW | 0x0 0000

### DDR_CSR_APB : INIT_NOP

Address offset | 0x0 4200
Physical address | 0x2008 4200 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_nop | Causes controller to issue NOP command. For DDR4, typically used for geardown mode. | RW | 0

### DDR_CSR_APB : CFG_INIT_DURATION

Address offset | 0x0 4204
Physical address | 0x2008 4204 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved |  | RO | 0x0000
15:0 | cfg_init_duration | Delay (tINIT5) after initialization RESET command that the controller waits before issuing ZQ initialization calibration (ZQINIT) command, specified in clocks. | RW | 0x29B0

### DDR_CSR_APB : CFG_ZQINIT_CAL_DURATION

Address offset | 0x0 4208
Physical address | 0x2008 4208 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved |  | RO | 0x0 0000
11:0 | cfg_zqinit_cal_duration | Delay from initialization ZQ calibration command to any subsequent command, specified in memory clocks. Based on tZQINIT timing specification. For DDR3, DDR4, LPDDR2 and LPDDR3 memory types this applies to the ZQ calibration command performed during the automatic initialization sequence. For DDR3 and DDR4 memory types, this also applies to any long ZQ calibration performed when 'cfg_zq_cal_type' is set to 3. | RW | 0x200

### DDR_CSR_APB : CFG_ZQ_CAL_L_DURATION

Address offset | 0x0 420C
Physical address | 0x2008 420C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved |  | RO | 0x00 0000
10:0 | cfg_zq_cal_l_duration | Delay from long ZQ-cal command to any subsequent command, specified in memory clocks. Based on tZQCL timing specification for DDR3, LPDDR2 and LPDDR3. Based on tZQOper timing specification for DDR4. | RW | 0x100

### DDR_CSR_APB : CFG_ZQ_CAL_S_DURATION

Address offset | 0x0 4210
Physical address | 0x2008 4210 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved |  | RO | 0x00 0000
10:0 | cfg_zq_cal_s_duration | Delay from short ZQ-cal command to any subsequent command, specified in memory clocks. Based on tZQCS timing specification. | RW | 0x040

### DDR_CSR_APB : CFG_ZQ_CAL_R_DURATION

Address offset | 0x0 4214
Physical address | 0x2008 4214 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | reserved |  | RO | 0x00 0000
10:0 | cfg_zq_cal_r_duration | Delay from ZQ-cal reset command to any subsequent command, specified in memory clocks. Based on tZQRESET timing specification. | RW | 0x035

### DDR_CSR_APB : CFG_MRR

Address offset | 0x0 4218
Physical address | 0x2008 4218 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_mrr | Mode register read command to valid mode read data (tMRR), specified in clocks. | RW | 0x2

### DDR_CSR_APB : CFG_MRW

Address offset | 0x0 421C
Physical address | 0x2008 421C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_mrw | Mode register write command period (tMRW), specified in clocks. | RW | 0x0C

### DDR_CSR_APB : CFG_ODT_POWERDOWN

Address offset | 0x0 4220
Physical address | 0x2008 4220 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_odt_powerdown | Set to enable ODT during powerdown. | RW | 0

### DDR_CSR_APB : CFG_WL

Address offset | 0x0 4224
Physical address | 0x2008 4224 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | cfg_wl | Write latency, specified in clocks. Valid values for HBM are 6 through 8. Valid values for LPDDR4 are 4 through 34. Valid values for GDDR6 are 5 through 8. | RW | 0x08

### DDR_CSR_APB : CFG_RL

Address offset | 0x0 4228
Physical address | 0x2008 4228 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | cfg_rl | Read latency, specified in clocks. | RW | 0x0B

### DDR_CSR_APB : CFG_CAL_READ_PERIOD

Address offset | 0x0 422C
Physical address | 0x2008 422C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | reserved |  | RO | 0x000
21:0 | cfg_cal_read_period | Period between calibration reads, specified in clocks. Set to 0 to disable periodic calibration reads. [This port only included in PHY configurations which require periodic calibration reads.] | RW | 0x00 0000

### DDR_CSR_APB : CFG_NUM_CAL_READS

Address offset | 0x0 4230
Physical address | 0x2008 4230 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_num_cal_reads | Number of calibration reads that are issued each time cfg_cal_read_period timer expires. [This port only included in PHY configurations which require periodic calibration reads.] | RW | 0x0

### DDR_CSR_APB : INIT_SELF_REFRESH

Address offset | 0x0 4234
Physical address | 0x2008 4234 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | init_self_refresh | Self-refresh control. Causes the controller to put the selected SDRAM rank (chip select) into self-refresh mode at the next refresh event. Each bit in init_self_refresh corresponds to the selected rank; asserting init_self_refresh[0] puts the devices connected to cs_n[0] into self refresh, init_self_refresh[1] for cs_n[1] and so on. This bus performs the same function as l_self_refresh, however this bus is first level-synchronized to the memory controller clock domain within the controller. This allows it to be controlled from a different clock domain, as is typically the case when driven from a control / status register (CSR) module. | RW | 0x00

### DDR_CSR_APB : INIT_SELF_REFRESH_STATUS

Address offset | 0x0 4238
Physical address | 0x2008 4238 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | init_self_refresh_status | Indicates which ranks are in self-refresh | RO | 0x00

### DDR_CSR_APB : INIT_POWER_DOWN

Address offset | 0x0 423C
Physical address | 0x2008 423C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | init_power_down | Power down control. Causes the controller to put the selected SDRAM rank (chip select) into power down mode. The core will automatically continue to refresh all devices so that data is retained. This bus performs the same function as l_power_down, however this bus is first level-synchronized to the memory controller clock domain within the controller. This allows it to be controlled from a different clock domain, as is typically the case when driven from a control / status register (CSR) module. | RW | 0x00

### DDR_CSR_APB : INIT_POWER_DOWN_STATUS

Address offset | 0x0 4240
Physical address | 0x2008 4240 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | init_power_down_status | Indicates which ranks are in power-down | RO | 0x00

### DDR_CSR_APB : INIT_FORCE_WRITE

Address offset | 0x0 4244
Physical address | 0x2008 4244 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_force_write | Forces assertion of 'dfi_wrdata_en' and 'dfi_odt' which will cause the PHY to drive its DQ, DQS and ODT outputs, regardless of whether a write command is issued or not. This feature can be used for software-driven write leveling as well as hardware debug of the write interface. When init_force_write is asserted and a regular write is not being driven by the controller, the data pattern is specified by 'init_force_write_data', and the rank driven to 'dfi_wrdata_cs' is specified by 'init_force_write_cs'. Whenever a regular write is being driven by the controller, the data pattern and rank come from the normal controller path, regardless of the state of 'init_force_write'. | RW | 0

### DDR_CSR_APB : INIT_FORCE_WRITE_CS

Address offset | 0x0 4248
Physical address | 0x2008 4248 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | init_force_write_cs | Rank passed to PHY on dfi_wrdata_cs when init_force_write is asserted and a regular write is not being driven. | RW | 0x00

### DDR_CSR_APB : CFG_CTRLR_INIT_DISABLE

Address offset | 0x0 424C
Physical address | 0x2008 424C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_ctrlr_init_disable | Controller initialization is bypassed when asserted, allowing PHY to perform initialization instead. | RW | 0

### DDR_CSR_APB : CTRLR_READY

Address offset | 0x0 4250
Physical address | 0x2008 4250 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | ctrlr_ready | Deasserted when in reset or after ctrlr_init is asserted, then asserts after initialization sequence and training sequences (if required) have completed | RO | 0

### DDR_CSR_APB : INIT_RDIMM_READY

Address offset | 0x0 4254
Physical address | 0x2008 4254 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_rdimm_ready | Signals to the application that the reset sequence has completed and that it may proceed with writing to the Register Control Words (RCW) and/or Buffer Control Words (BCW) of the RDIMM/LRDIMM, using the 'init_mr_w_req', 'init_mr_addr' and 'init_mr_wr_data' controls. | RO RtoClr | 0

### DDR_CSR_APB : INIT_RDIMM_COMPLETE

Address offset | 0x0 4258
Physical address | 0x2008 4258 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_rdimm_complete | Set by the application to indicate that it has completed writing to the Register Control Word (RCW) and/or Buffer Control Words (BCW) of the RDIMM/LRDIMM. This enables the controller to proceed with the device initialization. If the application does not need to write to the RCWs or BCWs, it may set this control high all the time. | RW | 0

### DDR_CSR_APB : CFG_RDIMM_LAT

Address offset | 0x0 425C
Physical address | 0x2008 425C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_rdimm_lat | Specifies the latency of the register device used in Registered DIMMs (RDIMMs) and Load-Reduced DIMMs (LRDIMMs). This value is used to delay data-path related signal timing going to the PHY to compensate for the extra latency in the DIMM. For DDR2 and DDR3 RDIMMs, as well as DDR3 LRDIMMs, the register device always introduces a latency of 1 clock on the command and address signals. For DDR4 RDIMMs and LRDIMMs, the register clock driver (RCD) introduces a latency of at least 1 clock on the command and address signals. It can introduce additional latency (up to 4 additional clocks) based on the "Command Latency Adder" control word setting in the RCD. In most cases, this setting should reflect the exact value of latency introduced by the RDIMM or LRDIMM register device. An exception is when the controller is integrated with a PHY that automatically compensates for the RDIMM or LRDIMM latency during its training sequence, and expects the same data-path related signal timing regardless of the amount of latency introduced by the register device. | RW | 0x0

### DDR_CSR_APB : CFG_RDIMM_BSIDE_INVERT

Address offset | 0x0 4260
Physical address | 0x2008 4260 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_rdimm_bside_invert | Set to 1 to indicate that the DDR4 RDIMM register clock driver (RCD) will invert the B-side addresses. | RW | 1

### DDR_CSR_APB : CFG_LRDIMM

Address offset | 0x0 4264
Physical address | 0x2008 4264 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_lrdimm | Set to 1 to indicate DDR4 LRDIMM is installed in the system. | RW | 0

### DDR_CSR_APB : INIT_MEMORY_RESET_MASK

Address offset | 0x0 4268
Physical address | 0x2008 4268 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_memory_reset_mask | When set, masks the reset output of the controller (dfi_reset_n_pN) so that it does not assert when the controller is in reset. This function can be useful in situations where the memory controller needs to be reset while holding the memory devices in the self-refresh state. This signal is connected to the reset_n pin of level synchronization flip-flops inside the memory controller. This guarantees synchronous assertion of the internal masking logic when the init_memory_reset_mask signal is not synchronized to the memory controller clock. However, this method does not guarantee synchronous de-assertion of the internal masking logic when init_memory_reset_mask transitions from 1 to 0. Therefore, 1 to 0 transitions should only happen while the memory controller is in reset (reset_n = 0). | RW | 0

### DDR_CSR_APB : CFG_RD_PREAMB_TOGGLE

Address offset | 0x0 426C
Physical address | 0x2008 426C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_rd_preamb_toggle | Sets read preamble toggle bit in the mode register. | RW | 0

### DDR_CSR_APB : CFG_RD_POSTAMBLE

Address offset | 0x0 4270
Physical address | 0x2008 4270 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_rd_postamble | Sets read postamble length bit in the mode register. | RW | 0

### DDR_CSR_APB : CFG_PU_CAL

Address offset | 0x0 4274
Physical address | 0x2008 4274 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_pu_cal | Sets pullup calibration point bit in the mode register. | RW | 0

### DDR_CSR_APB : CFG_DQ_ODT

Address offset | 0x0 4278
Physical address | 0x2008 4278 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_dq_odt | Sets DQ ODT value in the mode register. | RW | 0x0

### DDR_CSR_APB : CFG_CA_ODT

Address offset | 0x0 427C
Physical address | 0x2008 427C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_ca_odt | Sets CA ODT value in the mode register. | RW | 0x0

### DDR_CSR_APB : CFG_ZQLATCH_DURATION

Address offset | 0x0 4280
Physical address | 0x2008 4280 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_zqlatch_duration | Sets ZQ latch duration (tZQLAT) in memory clocks. Only applies to LPDDR4. This is the amount of time that the command bus must be in the deselect state after the ZQCAL latch command is issued by the controller. | RW | 0x30

### DDR_CSR_APB : INIT_CAL_SELECT

Address offset | 0x0 4284
Physical address | 0x2008 4284 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_cal_select | Calibration port select. Set to '1' prior to using init_cal_l_r_req to initiate a read on the memory bus. | RW | 0

### DDR_CSR_APB : INIT_CAL_L_R_REQ

Address offset | 0x0 4288
Physical address | 0x2008 4288 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_cal_l_r_req | A rising edge detected in this register setting causes a single read command to be issued by the controller. | RW | 0

### DDR_CSR_APB : INIT_CAL_L_B_SIZE

Address offset | 0x0 428C
Physical address | 0x2008 428C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | init_cal_l_b_size | Burst size for read requested using init_cal_l_r_req. | RW | 0x0

### DDR_CSR_APB : INIT_CAL_L_R_ACK

Address offset | 0x0 4290
Physical address | 0x2008 4290 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_cal_l_r_ack | Asserts to acknowledge read requested by init_cal_l_r_req. Asserted when the read command has been accepted. | RO RtoClr | 0

### DDR_CSR_APB : INIT_CAL_L_READ_COMPLETE

Address offset | 0x0 4294
Physical address | 0x2008 4294 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_cal_l_read_complete | Asserts to acknowledge read requested by init_cal_l_r_req. Asserted when the read command has occurred on the memory bus and the read data has been transferred. | RO RtoClr | 0

### DDR_CSR_APB : INIT_RWFIFO

Address offset | 0x0 42A0
Physical address | 0x2008 42A0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_rwfifo | Enables read/write access to the device FIFO. When set subsequent accesses are directed to FIFO rather than memory array until this bit is cleared. Rank is selected with init_cs register. | RW | 0

### DDR_CSR_APB : INIT_RD_DQCAL

Address offset | 0x0 42A4
Physical address | 0x2008 42A4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_rd_dqcal | Enables reading of DQ calibration pattern. When set any read will generate a DQ calibration read until this bit is cleared. Rank is selected with init_cs register. | RW | 0

### DDR_CSR_APB : INIT_START_DQSOSC

Address offset | 0x0 42A8
Physical address | 0x2008 42A8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_start_dqsosc | Issues a Start DQS Oscillator command to the memory device. Rank is selected with init_cs register. | RW | 0

### DDR_CSR_APB : INIT_STOP_DQSOSC

Address offset | 0x0 42AC
Physical address | 0x2008 42AC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_stop_dqsosc | Issues a Stop DQS Oscillator command to the memory device. Rank is selected with init_cs register. | RW | 0

### DDR_CSR_APB : INIT_ZQ_CAL_START

Address offset | 0x0 42B0
Physical address | 0x2008 42B0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_zq_cal_start | Issues a ZQ calibration start command to the memory device. Rank is selected with init_cs register. | RW | 0

### DDR_CSR_APB : CFG_WR_POSTAMBLE

Address offset | 0x0 42B4
Physical address | 0x2008 42B4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_wr_postamble | Sets write postamble bit in the mode register. | RW | 0

### DDR_CSR_APB : INIT_CAL_L_ADDR_0

Address offset | 0x0 42BC
Physical address | 0x2008 42BC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | init_cal_l_addr_0 | Address used for read requested using init_cal_l_r_req. | RW | 0x0000 0000

### DDR_CSR_APB : INIT_CAL_L_ADDR_1

Address offset | 0x0 42C0
Physical address | 0x2008 42C0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved |  | RO | 0x000 0000
6:0 | init_cal_l_addr_1 | Address used for read requested using init_cal_l_r_req. | RW | 0x00

### DDR_CSR_APB : CFG_CTRLUPD_TRIG

Address offset | 0x0 42C4
Physical address | 0x2008 42C4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_ctrlupd_trig | Specifies the trigger for the controller initiated update signal ('dfi_ctrlupd_req'). 0 - Disable 1 - Any refresh event triggers controller initiated update request 2 - Any ZQ-calibration event triggers controller initiated update request (for memory technologies that support it) | RW | 0x1

### DDR_CSR_APB : CFG_CTRLUPD_START_DELAY

Address offset | 0x0 42C8
Physical address | 0x2008 42C8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_ctrlupd_start_delay | Delay from the DFI MC-initiated update trigger event command (as specified by 'cfg_ctrlupd_trig') to when the controller asserts 'dfi_ctrlupd_req'. This delay is specified in DFI clocks and is measured at the DFI interface to the PHY and can take on values of 0 (not recommended) to 1023. When DDR4 Command-Address-Latency (CAL) mode is used, the delay is from the assertion of the command at the DFI interface (which occurs sometime after the associated chip-select assertion in CAL mode). Note that this register defaults to the minimum recommended value of 5; however it is possible that some phys that support dfi_ctrlupd_req will require a larger cfg_ctrlupd_start_delay value to guarantee that a previous read in progress has completed before the NWL controller asserts dfi_ctrlupd_req as determined by this value and the cfg_ctrlupd_trig CSR. | RW | 0x016

### DDR_CSR_APB : CFG_DFI_T_CTRLUPD_MAX

Address offset | 0x0 42CC
Physical address | 0x2008 42CC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_dfi_t_ctrlupd_max | Duration of 'dfi_ctrlupd_req' assertion. 0 - 'dfi_ctrlupd_req' will only de-assert after 'dfi_ctrlupd_ack' is asserted and then deasserted. 1-1023 - Duration of 'dfi_ctrlupd_req' assertion, specified in dfi clocks. 'dfi_ctrlupd_req' will deassert if 'dfi_ctrlupd_ack' asserts and deasserts before this time has elapsed. Otherwise 'dfi_ctrlupd_req' will deassert immediately after this time has elapsed. | RW | 0x0C8

### DDR_CSR_APB : CFG_CTRLR_BUSY_SEL

Address offset | 0x0 42D0
Physical address | 0x2008 42D0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_ctrlr_busy_sel | Selects source of dfi_ctrlr_busy signal going to PHY 0 - dfi_ctrlr_busy generated based on read/write traffic and delay timings specified by cfg_ctrlr_busy_turn_off_delay, cfg_ctrlr_busy_slow_restart_window, and cfg_ctrlr_busy_restart_holdoff 1 - dfi_ctrlr_busy driven by static value specified by cfg_ctrlr_busy_value. This mode is typically used only for debug or for disabling the dynamic ctrlr_busy functionality. | RW | 0

### DDR_CSR_APB : CFG_CTRLR_BUSY_VALUE

Address offset | 0x0 42D4
Physical address | 0x2008 42D4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_ctrlr_busy_value | Value driven on dfi_ctrlr_busy going to PHY if cfg_ctrlr_busy_sel = 1 | RW | 0

### DDR_CSR_APB : CFG_CTRLR_BUSY_TURN_OFF_DELAY

Address offset | 0x0 42D8
Physical address | 0x2008 42D8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | reserved |  | RO | 0x00 0000
8:0 | cfg_ctrlr_busy_turn_off_delay | Delay from last dfi_rddata_en or dfi_wrdata_en to deassertion of dfi_ctrlr_busy. | RW | 0x000

### DDR_CSR_APB : CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW

Address offset | 0x0 42DC
Physical address | 0x2008 42DC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved |  | RO | 0x000 0000
6:0 | cfg_ctrlr_busy_slow_restart_window | If a command is received while the window is active then assert busy and then wait for restart holdoff before sending commands to the controller. If a command is received after the window is closed then assert busy and allow commands to go to the controller immediately. If the window is programmed to 0 then always wait for the command holdoff. | RW | 0x00

### DDR_CSR_APB : CFG_CTRLR_BUSY_RESTART_HOLDOFF

Address offset | 0x0 42E0
Physical address | 0x2008 42E0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved |  | RO | 0x000 0000
6:0 | cfg_ctrlr_busy_restart_holdoff | The delay from asserting busy = 1 to allowing commands to go the controller. If this is 0 then dfi_ctrlr_busy is always 1 and commands are never held off. This delay is also used when init_force_write is asserted to assure that there is enough time between the assertion of dfi_ctrlr_busy and the assertion of dfi_wrdata_en. | RW | 0x00

### DDR_CSR_APB : CFG_PARITY_RDIMM_DELAY

Address offset | 0x0 42E4
Physical address | 0x2008 42E4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_parity_rdimm_delay | Delay the command address parity_in signal by 1 cycle. Typically needed to be set to 1 with regdimm configurations. Some PHYs provide this delay, in which case it should be set to 0. | RW | 1

### DDR_CSR_APB : CFG_CTRLR_BUSY_ENABLE

Address offset | 0x0 42E8
Physical address | 0x2008 42E8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_ctrlr_busy_enable | Enables the controller busy function. If cfg_ctrlr_busy_enable is set to 0 dfi_ctrlr_busy is always high. | RW | 0

### DDR_CSR_APB : CFG_ASYNC_ODT

Address offset | 0x0 42EC
Physical address | 0x2008 42EC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_async_odt | Enable asynchronous ODT operation for non-DLL mode of operation. 0 - disable asynchronous ODT operation 1 - enable asynchronous ODT operation | RW | 0

### DDR_CSR_APB : CFG_ZQ_CAL_DURATION

Address offset | 0x0 42F0
Physical address | 0x2008 42F0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved |  | RO | 0x0 0000
11:0 | cfg_zq_cal_duration | Delay from LPDDR4 ZQ-cal start command to ZQ-cal latch command, specified in memory clocks. Based on LPDDR4 tZQCAL timing specification. | RW | 0x640

### DDR_CSR_APB : CFG_MRRI

Address offset | 0x0 42F4
Physical address | 0x2008 42F4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | cfg_mrri | Additional time required following power-down state before issuing a command (tMRRI). Time from power-down exit to first command is tXP + tMRRI. | RW | 0x00

### DDR_CSR_APB : INIT_ODT_FORCE_EN

Address offset | 0x0 42F8
Physical address | 0x2008 42F8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_odt_force_en | Turn on ODT per write selection matrix specified by 'cfg_odt_wr_map_csN' ports. Rank is specified by 'init_odt_force_rank'. This port may be used to set up the ODT signals for user controlled write leveling. | RW | 0

### DDR_CSR_APB : INIT_ODT_FORCE_RANK

Address offset | 0x0 42FC
Physical address | 0x2008 42FC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | init_odt_force_rank | Rank selection when 'init_odt_force_en' is asserted. | RW | 0x0

### DDR_CSR_APB : CFG_PHYUPD_ACK_DELAY

Address offset | 0x0 4300
Physical address | 0x2008 4300 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | cfg_phyupd_ack_delay | Delay in DFI clocks before the dfi_phyupd_ack signal is asserted. The delay is measured from the time the DFI bus is idle after receiving a dfi_phyupd_req, providing additional margin between the request and acknowledge. | RW | 0x000

### DDR_CSR_APB : CFG_MIRROR_X16_BG0_BG1

Address offset | 0x0 4304
Physical address | 0x2008 4304 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_mirror_x16_bg0_bg1 | For DDR4 DIMMs populated with x16 devices, when set to 1'b1 will force mirroring of bank group bits BG0/1 when address mirroring is enabled for those ranks. Normally x16 devices do not have BG1 so the bank group bits are not mirrored. However, some PHY or DIMM applications may still require mirroring of the bank group bits. | RW | 0

### DDR_CSR_APB : INIT_PDA_MR_W_REQ

Address offset | 0x0 4308
Physical address | 0x2008 4308 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_pda_mr_w_req | Per-DRAM addressability mode register write request. Initiates mode register write to the mode register specified by init_mr_addr, rank specified by init_cs, and devices selected by init_pda_nibble_select. The data to be written to the mode register is specified using init_mr_wr_data and init_mr_wr_mask. Assertion of init_ack signals completion of the operation. | RW | 0

### DDR_CSR_APB : INIT_PDA_NIBBLE_SELECT

Address offset | 0x0 430C
Physical address | 0x2008 430C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:18 | reserved |  | RO | 0x0000
17:0 | init_pda_nibble_select | Selects nibbles for Per-DRAM addressability mode writes initiated using init_pda_mr_w_req. Each bit corresponds to one nibble of the memory interface and drives all 4 bits of the corresponding nibble during the PDA mode register write. If the interface consists of x8 or x16 devices, then it is recommended that both nibbles of each byte are set to the same select value, in case there is a nibble swap on the DIMM or PCB. Note that at the memory interface, devices are selected with a '0' value on DQ, so the values driven on the DQ bus are the invert of the corresponding init_pda_nibble_select bit setting. | RW | 0x0 0000

### DDR_CSR_APB : CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH

Address offset | 0x0 4310
Physical address | 0x2008 4310 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_dram_clk_disable_in_self_refresh | When set, all clock outputs to DRAM are disabled after all ranks are put into self-refresh. Clocks are automatically restarted before ranks exit self-refresh. Clocks are controlled using the dfi_dram_clk_disable port going to the PHY. It is expected that the DB in an LRDIMM application will need to be retrained after the clocks have been stopped. Therefore this feature is not used in an LRDIMM configuration. The init_dfi_dram_clk_disable port may be used to stop the DRAM clocks for an LRDIMM. | RW | 0

### DDR_CSR_APB : CFG_CKSRE

Address offset | 0x0 4314
Physical address | 0x2008 4314 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_cksre | Valid DRAM clock requirement after self-refresh entry (tCKSRE), specified in memory clocks. For DDR4 the controller automatically includes parity latency so that tCKSRE_PAR is satisfied as well. | RW | 0x08

### DDR_CSR_APB : CFG_CKSRX

Address offset | 0x0 4318
Physical address | 0x2008 4318 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_cksrx | Valid DRAM clock requirement before self-refresh exit (tCKSRX), specified in memory clocks. | RW | 0x08

### DDR_CSR_APB : CFG_RCD_STAB

Address offset | 0x0 431C
Physical address | 0x2008 431C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:14 | reserved |  | RO | 0x0 0000
13:0 | cfg_rcd_stab | Value for RDIMM RCD clock stabilization time (tSTAB), specified in memory clocks. When clocks are disabled using cfg_dram_clk_disable_in_self_refresh, this delay is combined with cfg_cksrx when the clocks are restarted before the CKE inputs to the RCD are asserted. | RW | 0x0000

### DDR_CSR_APB : CFG_DFI_T_CTRL_DELAY

Address offset | 0x0 4320
Physical address | 0x2008 4320 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_dfi_t_ctrl_delay | Number of memory clocks required for the DFI control signals presented to the PHY to reach the DRAM interface of the PHY. This value is used to delay the disable of the clock going to memory via dfi_dram_clk_disable, after self-refresh entry when cfg_dram_clk_disable_in_self_refresh is set to 1. | RW | 0x00

### DDR_CSR_APB : CFG_DFI_T_DRAM_CLK_ENABLE

Address offset | 0x0 4324
Physical address | 0x2008 4324 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_dfi_t_dram_clk_enable | Number of memory clock cycles from the deassertion of the dfi_dram_clk_disable signal until the first valid rising clock edge at the DRAM interface of the PHY. | RW | 0x00

### DDR_CSR_APB : CFG_IDLE_TIME_TO_SELF_REFRESH

Address offset | 0x0 4328
Physical address | 0x2008 4328 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_idle_time_to_self_refresh | Duration from the last data transaction to when the controller automatically puts all ranks in self-refresh, specified in memory clocks. A value of 0 disables the automatic self-refresh entry feature. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_IDLE_TIME_TO_POWER_DOWN

Address offset | 0x0 432C
Physical address | 0x2008 432C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_idle_time_to_power_down | Duration from the last data transaction to when the controller automatically puts all ranks in power-down, specified in memory clocks. A value of 0 disables the automatic power-down entry feature. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_BURST_RW_REFRESH_HOLDOFF

Address offset | 0x0 4330
Physical address | 0x2008 4330 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_burst_rw_refresh_holdoff | When set, refresh request is held off until all writes or reads of current burst has been executed. In this mode, refresh is demoted to priority level below that of writes and reads. | RW | 0

### DDR_CSR_APB : INIT_REFRESH_COUNT

Address offset | 0x0 4334
Physical address | 0x2008 4334 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | init_refresh_count | Indicates the number of REFRESH commands that are in the automatic refresh queue when cfg_auto_ref_en = 1. Values > 1 indicate that REFRESH commands are being postponed. | RO | 0x00

### DDR_CSR_APB : CFG_BG_INTERLEAVE

Address offset | 0x0 4384
Physical address | 0x2008 4384 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_bg_interleave | Enables interleaving of bank-groups in back-to-back transactions to avoid tCCD_L delays in DRAM architectures with bank groups (DDR4 and HBM). When set, the address is mapped such that the BG0 bit toggles on each successive read/write command as l_addr is sequentially increased. The Multi-burst core also uses this register to determine when to issue requests with the auto-precharge attribute. When this register is set and l_auto_pch is set for a request, the multiburst module sets the auto-precharge attribute with the last two requests in a multi-burst series so that both of the accessed banks are closed. When this register is clear and l_auto_pch is set, the multiburst module sets the auto-precharge attribute with only the last request since that is the only bank group that has been accessed. | RW | 1

### DDR_CSR_APB : CFG_REFRESH_DURING_PHY_TRAINING

Address offset | 0x0 43FC
Physical address | 0x2008 43FC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_refresh_during_phy_training | Use in conjunction with cfg_auto_ref_en to enable controller-initiated refresh cycles during PHY training. When this is set to '0', the controller will not issue refresh while PHY training is active. | RW | 0

### DDR_CSR_APB : MT_EN

Address offset | 0x0 4400
Physical address | 0x2008 4400 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | mt_en | Rising edge on 'mt_en' or 'mt_enable_single" starts a test. | RW | 0

### DDR_CSR_APB : MT_EN_SINGLE

Address offset | 0x0 4404
Physical address | 0x2008 4404 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | mt_en_single | Enables single memory test. The memory test will only start after a low to high transition of this signal. The memory test will not repeat if 'mt_en_single' remains asserted at the end of the memory test. | RW | 0

### DDR_CSR_APB : MT_STOP_ON_ERROR

Address offset | 0x0 4408
Physical address | 0x2008 4408 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | mt_stop_on_error | When mt_en is held asserted so that the memory test repeats multiple times, setting this bit will prevent the test from repeating again if an error was detected on the previous run. This is useful for debugging very infrequent errors which require many repetitions of the test before the error occurs. For example, once the error has occurred and the test has stopped, the test can be repeated with the 'mt_read_only' flag set, to help determine if the error occurred on a write or a read. | RW | 0

### DDR_CSR_APB : MT_RD_ONLY

Address offset | 0x0 440C
Physical address | 0x2008 440C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | mt_rd_only | Causes only reads to be performed when the memory test is enabled. Should not be set when 'mt_wr_only' is also set. | RW | 0

### DDR_CSR_APB : MT_WR_ONLY

Address offset | 0x0 4410
Physical address | 0x2008 4410 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | mt_wr_only | Causes only writes to be performed when the memory test is enabled. Should not be set when 'mt_rd_only' is also set. | RW | 0

### DDR_CSR_APB : MT_DATA_PATTERN

Address offset | 0x0 4414
Physical address | 0x2008 4414 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | mt_data_pattern | Memory test data pattern selection: 0x0 : Counting pattern 0x1 : Walking 1's 0x2 : Repeating Pseudo-random data (generated with LFSR). Repeats pattern sequence on each pass when test is run repetitively with 'mt_en' held high. 0x3 : Non-Repeating Pseudo-random data (generated with LFSR). Pattern continues from where it left off on previous test when 'mt_en' is held high. 0x4 : Alternating all 1's and all 0's 0x5 : Alternating 5's and a's 0x6 : User-specified pattern, specified with mt_user_data_pattern. Pattern copied across all bytes of data bus on memory writes, and all bytes of expected data on memory reads. 0x7 : Pseudo-random 16-bit data (generated with LFSR), copied across all words of data bus. 0x8 : Pseudo-random 8-bit data (generated with LFSR), copied across all bytes of data bus. | RW | 0x0

### DDR_CSR_APB : MT_ADDR_PATTERN

Address offset | 0x0 4418
Physical address | 0x2008 4418 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | mt_addr_pattern | Memory test address pattern selection: 0x0 : Counting pattern 0x1 : LFSR 0x2 : Arbitrary Pattern Generator 0x3 : Reserved The LFSR address pattern is used only when the LFSR address pattern is selected and (mt_addr_bits - cfg_bl - 1) is greater than 2. Otherwise, counting address pattern is used, regardless of which address pattern is selected. | RW | 0x0

### DDR_CSR_APB : MT_DATA_INVERT

Address offset | 0x0 441C
Physical address | 0x2008 441C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | mt_data_invert | Invert data pattern | RW | 0

### DDR_CSR_APB : MT_ADDR_BITS

Address offset | 0x0 4420
Physical address | 0x2008 4420 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | mt_addr_bits | Address range to test. Test will start at 'mt_start_addr' and continue to addresses 'mt_start_addr' + 2 ^ mt_addr_bits. Note: The minimum valid value is a function of memory burst length: 1 - (memory burst length = 2) 2 - (memory burst length = 4) 3 - (memory burst length = 8) | RW | 0x08

### DDR_CSR_APB : MT_ERROR_STS

Address offset | 0x0 4424
Physical address | 0x2008 4424 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | mt_error_sts | Goes true when the memory test module detects a mismatch between expected data and the data read from the sdram. Cleared immediately after reading this csr. | RO RtoClr | 0

### DDR_CSR_APB : MT_DONE_ACK

Address offset | 0x0 4428
Physical address | 0x2008 4428 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | mt_done_ack | Indicates completion of memory test through address range specified by 'mt_addr_bits'. Signal is asserted when final test completes after mt_en has been cleared. | RO RtoClr | 0

### DDR_CSR_APB : MT_START_ADDR_0

Address offset | 0x0 44B4
Physical address | 0x2008 44B4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | mt_start_addr_0 | Address to start memory test at. This port is not used when 'mt_addr_pattern' is set to 0x1 (pseudo-random). | RW | 0x0000 0000

### DDR_CSR_APB : MT_START_ADDR_1

Address offset | 0x0 44B8
Physical address | 0x2008 44B8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved |  | RO | 0x000 0000
6:0 | mt_start_addr_1 | Address to start memory test at. This port is not used when 'mt_addr_pattern' is set to 0x1 (pseudo-random). | RW | 0x00

### DDR_CSR_APB : MT_ERROR_MASK_0

Address offset | 0x0 44BC
Physical address | 0x2008 44BC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | mt_error_mask_0 | Error mask. All bits set in this field will mask read-back errors in corresponding data bits. The 'mt_error_sts' flag will not get set when errors are encountered on those data bits. | RW | 0x0000 0000

### DDR_CSR_APB : MT_ERROR_MASK_1

Address offset | 0x0 44C0
Physical address | 0x2008 44C0 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | mt_error_mask_1 | Error mask. All bits set in this field will mask read-back errors in corresponding data bits. The 'mt_error_sts' flag will not get set when errors are encountered on those data bits. | RW | 0x0000 0000

### DDR_CSR_APB : MT_ERROR_MASK_2

Address offset | 0x0 44C4
Physical address | 0x2008 44C4 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | mt_error_mask_2 | Error mask. All bits set in this field will mask read-back errors in corresponding data bits. The 'mt_error_sts' flag will not get set when errors are encountered on those data bits. | RW | 0x0000 0000

### DDR_CSR_APB : MT_ERROR_MASK_3

Address offset | 0x0 44C8
Physical address | 0x2008 44C8 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | mt_error_mask_3 | Error mask. All bits set in this field will mask read-back errors in corresponding data bits. The 'mt_error_sts' flag will not get set when errors are encountered on those data bits. | RW | 0x0000 0000

### DDR_CSR_APB : MT_ERROR_MASK_4

Address offset | 0x0 44CC
Physical address | 0x2008 44CC | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved |  | RO | 0x0000
15:0 | mt_error_mask_4 | Error mask. All bits set in this field will mask read-back errors in corresponding data bits. The 'mt_error_sts' flag will not get set when errors are encountered on those data bits. | RW | 0x0000

### DDR_CSR_APB : MT_USER_DATA_PATTERN

Address offset | 0x0 4670
Physical address | 0x2008 4670 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | mt_user_data_pattern | User-specified data pattern for use with Algorithmic Pattern Generator, when mt_data_pattern selects user-specified pattern. | RW | 0x00

### DDR_CSR_APB : MT_ALG_AUTO_PCH

Address offset | 0x0 467C
Physical address | 0x2008 467C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | mt_alg_auto_pch | Causes auto_precharge to be asserted when the memory test is enabled and the algorithmic pattern generator is being used. | RW | 0

### DDR_CSR_APB : CFG_STARVE_TIMEOUT_P0

Address offset | 0x0 4C00
Physical address | 0x2008 4C00 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved |  | RO | 0x0 0000
11:0 | cfg_starve_timeout_p0 | Amount of time that may elapse (in system clocks) before this port is serviced. If a request is pending to this port for a period of time longer than 'cfg_starve_timeout_pN', it will automatically be promoted to the highest priority and serviced next. Any port having this value set to '0' will have its starvation timeout disabled. | RW | 0x000

### DDR_CSR_APB : CFG_STARVE_TIMEOUT_P1

Address offset | 0x0 4C04
Physical address | 0x2008 4C04 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved |  | RO | 0x0 0000
11:0 | cfg_starve_timeout_p1 | Amount of time that may elapse (in system clocks) before this port is serviced. If a request is pending to this port for a period of time longer than 'cfg_starve_timeout_pN', it will automatically be promoted to the highest priority and serviced next. Any port having this value set to '0' will have its starvation timeout disabled. | RW | 0x000

### DDR_CSR_APB : CFG_STARVE_TIMEOUT_P2

Address offset | 0x0 4C08
Physical address | 0x2008 4C08 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved |  | RO | 0x0 0000
11:0 | cfg_starve_timeout_p2 | Amount of time that may elapse (in system clocks) before this port is serviced. If a request is pending to this port for a period of time longer than 'cfg_starve_timeout_pN', it will automatically be promoted to the highest priority and serviced next. Any port having this value set to '0' will have its starvation timeout disabled. | RW | 0x000

### DDR_CSR_APB : CFG_STARVE_TIMEOUT_P3

Address offset | 0x0 4C0C
Physical address | 0x2008 4C0C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved |  | RO | 0x0 0000
11:0 | cfg_starve_timeout_p3 | Amount of time that may elapse (in system clocks) before this port is serviced. If a request is pending to this port for a period of time longer than 'cfg_starve_timeout_pN', it will automatically be promoted to the highest priority and serviced next. Any port having this value set to '0' will have its starvation timeout disabled. | RW | 0x000

### DDR_CSR_APB : CFG_STARVE_TIMEOUT_P4

Address offset | 0x0 4C10
Physical address | 0x2008 4C10 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved |  | RO | 0x0 0000
11:0 | cfg_starve_timeout_p4 | Amount of time that may elapse (in system clocks) before this port is serviced. If a request is pending to this port for a period of time longer than 'cfg_starve_timeout_pN', it will automatically be promoted to the highest priority and serviced next. Any port having this value set to '0' will have its starvation timeout disabled. | RW | 0x000

### DDR_CSR_APB : CFG_STARVE_TIMEOUT_P5

Address offset | 0x0 4C14
Physical address | 0x2008 4C14 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved |  | RO | 0x0 0000
11:0 | cfg_starve_timeout_p5 | Amount of time that may elapse (in system clocks) before this port is serviced. If a request is pending to this port for a period of time longer than 'cfg_starve_timeout_pN', it will automatically be promoted to the highest priority and serviced next. Any port having this value set to '0' will have its starvation timeout disabled. | RW | 0x000

### DDR_CSR_APB : CFG_STARVE_TIMEOUT_P6

Address offset | 0x0 4C18
Physical address | 0x2008 4C18 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved |  | RO | 0x0 0000
11:0 | cfg_starve_timeout_p6 | Amount of time that may elapse (in system clocks) before this port is serviced. If a request is pending to this port for a period of time longer than 'cfg_starve_timeout_pN', it will automatically be promoted to the highest priority and serviced next. Any port having this value set to '0' will have its starvation timeout disabled. | RW | 0x000

### DDR_CSR_APB : CFG_STARVE_TIMEOUT_P7

Address offset | 0x0 4C1C
Physical address | 0x2008 4C1C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | reserved |  | RO | 0x0 0000
11:0 | cfg_starve_timeout_p7 | Amount of time that may elapse (in system clocks) before this port is serviced. If a request is pending to this port for a period of time longer than 'cfg_starve_timeout_pN', it will automatically be promoted to the highest priority and serviced next. Any port having this value set to '0' will have its starvation timeout disabled. | RW | 0x000

### DDR_CSR_APB : CFG_REORDER_EN

Address offset | 0x0 5000
Physical address | 0x2008 5000 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_reorder_en | Enable for request reordering. 0 - Request reordering disabled 1 - Request reordering enabled This port is only used in configurations of the Reorder Core where request reordering is supported. Refer to section 3.4 for details on request reordering. When this port is set to '1' and 'cfg_reorder_queue_en' is also '1', reordering of buffered entries is enabled, otherwise the buffered entries are issued in fifo order. If 'cfg_reorder_queue_en' is set to '0', cfg_reorder_en is a don't care. | RW | 1

### DDR_CSR_APB : CFG_REORDER_QUEUE_EN

Address offset | 0x0 5004
Physical address | 0x2008 5004 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_reorder_queue_en | Reorder queue enable. When set to '1', allows requests to stack up in reorder queue. Reordering will occur if 'cfg_reorder_en' is also set to 1. This port is only used in configurations of the Reorder Core where request reordering is supported. Refer to section section 3.4 for details on request reordering. This port is typically only provided for ASIC configurations. Under normal circumstances this port will always be set to '1'. It is provided for debugging purposes. | RW | 1

### DDR_CSR_APB : CFG_INTRAPORT_REORDER_EN

Address offset | 0x0 5008
Physical address | 0x2008 5008 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_intraport_reorder_en | Enable intra-port reordering. 0 - Intra-port request reordering disabled 1 - Intra-port request reordering enabled This port is ignored if cfg_reorder_en is set to '0'. Refer to section section 3.4 for details on request reordering and intraport reordering. | RW | 1

### DDR_CSR_APB : CFG_MAINTAIN_COHERENCY

Address offset | 0x0 500C
Physical address | 0x2008 500C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_maintain_coherency | Causes data coherency to be maintained by preventing reordering of requests addressing the same memory region. Refer to Reorder Core User Guide for a description of memory regions. | RW | 1

### DDR_CSR_APB : CFG_Q_AGE_LIMIT

Address offset | 0x0 5010
Physical address | 0x2008 5010 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_q_age_limit | Reorder core queue entry age limit. The age limit value prevents the oldest entry in the queue from being 'stuck' in the reorder queue for too long. When the oldest entry in the queue changes, the age limit counter is reset and starts counting. Each time a newer entry exits the reorder queue (has been issued to the controller) without the oldest entry in the queue being issued, the 'age' of the oldest entry in the queue is incremented. If cfg_q_age_limit newer entries are issued before the oldest entry is issued, then the oldest entry in the queue becomes the highest priority and is always issued next. The width of the cfg_q_age_limit value is set by the parameter QUEUE_AGE_BITS. QUEUE_AGE_BITS can be set to as small as 1 (but this is not recommended) and can be set to as large of a value that the application needs; however when using cfg_q_age_limit values larger than the REORDER_QUEUE_DEPTH, this can result in the oldest entry being "stuck" in the queue for too long. This port is only useful in configurations of the Reorder Core where request reordering is supported. Refer to section 3.4 for details on request reordering. Both 'cfg_reorder_en' and 'cfg_reorder_queue_en' must be set to '1'. When either of these configuration bits are set to 0, the reorder queue entries are issued in the order that they arrived at the input to the reorder queue. | RW | 0xFF

### DDR_CSR_APB : CFG_RO_CLOSED_PAGE_POLICY

Address offset | 0x0 5018
Physical address | 0x2008 5018 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_ro_closed_page_policy | Reorder core closed page policy control. When this bit is set, the reorder core adjusts its reordering algorithm (currently only when using Criteria 0) to optimize for the case that all read/write accesses are issued with the auto_precharge bit set. When the reorder_queue entry buffering is enabled (cfg_reorder_queue_en = 1), this bit forces all accesses that exit the reorder core to have the auto-precharge bit set if the closed page policy mode has been selected. In other words, cfg_ro_closed_page_policy must be clear or cfg_reorder_queue_en must be clear to allow l_auto_pch inputs (per port) to control the auto precharge function per mpfe input port. | RW | 0

### DDR_CSR_APB : CFG_REORDER_RW_ONLY

Address offset | 0x0 501C
Physical address | 0x2008 501C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_reorder_rw_only | Reorder core read/write reordering only. When this bit is set, the reorder core adjusts its reordering algorithm (currently only when using Criteria 0)to maximize the grouping of reads and writes together (normal Criteria 0 filtering is not used). Switching between issuing reads and writes only occur if one of the following things occur: o Issuing a stream of reads (or writes) and there are no more coherent, priority-enabled reads (or writes) to issue o The oldest entry in the reorder queue times out. Note that if cfg_manual_address_map is set and reordering is enabled, then the cfg_reorder_rw_only bit should normally be set as well (normal reordering algorithms will not work as expected if using manual address mapping in the controller core). When cfg_reorder_rw_only is clear and reordering is enabled, then the normal filtering algorithm is used to select the next request to issue from the reorder core. | RW | 0

### DDR_CSR_APB : CFG_RO_PRIORITY_EN

Address offset | 0x0 5020
Physical address | 0x2008 5020 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_ro_priority_en | Reorder_core QOS/priority enable. When this bit is set (and REORDER_PRIORITY_ENABLE paramter was set during synthesis), the reorder core will normally send out only requests that have the highest priority (except if the oldest entry in the reorder core has aged/timed-out). If clear (or the REORDER_PRIORITY_ENABLE parameter was clear during synthesis), the reorder core ignores any incoming priority and selects the next request from the reorder_queue to maximize bandwidth/performance. | RW | 0

### DDR_CSR_APB : CFG_DM_EN

Address offset | 0x0 5400
Physical address | 0x2008 5400 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_dm_en | When set to '1' the RMW Core will use data mask signals to the memory in order to optimize certain RMW operations. This port must be set to '0' if the DRAM data mask signals are not connected to the memory devices. | RW | 1

### DDR_CSR_APB : CFG_RMW_EN

Address offset | 0x0 5404
Physical address | 0x2008 5404 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_rmw_en | Enable or disable RMW. 0 - disables RMW operations. 1 - enables RMW operations. When disabled, the RMW Core requires that the memory support data mask functionality (no ECC, data mask pins connected through to memory devices) and cfg_dm_en must be set to '1'. A setting of '0' also enables use of the 'l_dm_in' data mask inputs. | RW | 1

### DDR_CSR_APB : CFG_ECC_CORRECTION_EN

Address offset | 0x0 5800
Physical address | 0x2008 5800 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_ecc_correction_en | Enables ECC error correction and detection 0x1 - Correction and detection function is enabled, 1 bit errors will be corrected, multi-bit errors will not be corrected. Errors occurring in an odd number of bits (3,5,7, etc.) could have additional bit inversions due to attempted correction. 0x0 - Correction and detection function is disabled. ECC errors are not reported. | RW | 1

### DDR_CSR_APB : CFG_ECC_BYPASS

Address offset | 0x0 5840
Physical address | 0x2008 5840 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_ecc_bypass | When set to 1, the controller will not compute ECC check data or perform ECC correction on received data. When in ECC bypass mode, axiN_wdata_parity input pins are repurposed to be the data that gets written to ECC memory. Likewise, axiN_rdata_parity outputs are repurposed to be the data that gets read out of ECC memory. | RW | 0

### DDR_CSR_APB : INIT_WRITE_DATA_1B_ECC_ERROR_GEN

Address offset | 0x0 5844
Physical address | 0x2008 5844 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | init_write_data_1b_ecc_error_gen | Memory controller write data path 1-bit ECC error generation. This register contains one bit per 64-bits (ECC generators are used per 64-bits of data path width) of user interface data path width. When set, will invert the corresponding ECC generator's least significant ECC check bit (causing a 1-bit ECC error) on the next cycle of write data. Error generation will persist for only one cycle. To cause a subsequent 1-bit ECC error generation cycle, a bit must be written to 0 and then back to 1. | RW | 0x0

### DDR_CSR_APB : INIT_WRITE_DATA_2B_ECC_ERROR_GEN

Address offset | 0x0 5848
Physical address | 0x2008 5848 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | init_write_data_2b_ecc_error_gen | Memory controller write data path 2-bit ECC error generation. This register contains one bit per 64-bits (ECC generators are used per 64-bits of data path width) of user interface data path width. When set, will invert the corresponding ECC generator's 2 most significant of the 3 least significant ECC check bits (causing a 2-bit ECC error) on the next cycle of write data. Error generation will persist for only one cycle. To cause a subsequent 2-bit ECC error generation cycle, a bit must be written to 0 and then back to 1. | RW | 0x0

### DDR_CSR_APB : CFG_ECC_1BIT_INT_THRESH

Address offset | 0x0 585C
Physical address | 0x2008 585C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | cfg_ecc_1bit_int_thresh | This 8-bit value defines the number of ECC 1-bit error corrections that must be exceeded before the stat_int_ecc_1bit_thresh status bit (and interrupt output pin) are set and the error summing register is cleared to start summing new ECC 1bit error correction counts. Setting this value to 0 means that each new correctable ecc error will signal an interrupt/set the status bit. Setting this value to the maximum value of 0xff will disable generating the interrupt and interrupt status. Note that if the parity error retry module is included, 1bit error corrections signaled into that unit are not counted and only the 1bit corrected errors that are passed on to the user logic interface from this unit are counted. Also if the RMW unit is included and a read prefetch is performed to allow data to be merged with a user write and the read prefetch results in a 1bit ecc correction, this 1bit correction will be counted by the ecc_1bit_int_threshold detection logic. Finally, if the ECC Scrub logic is included, any ECC corrections deteted by this unit will also be counted. | RW | 0x00

### DDR_CSR_APB : STAT_INT_ECC_1BIT_THRESH

Address offset | 0x0 5860
Physical address | 0x2008 5860 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | stat_int_ecc_1bit_thresh | This bit is set when the number of 1bit ECC error corrections is greater-than the cfg_ecc_1bit_thresh. This status bit should be read to clear the status and associated interrupt pin output as soon as possible, to avoid missing the setting of this status/interrupt due to new 1bit ECC error corrections. | RO RtoClr | 0

### DDR_CSR_APB : INIT_READ_CAPTURE_ADDR

Address offset | 0x0 5C00
Physical address | 0x2008 5C00 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | init_read_capture_addr | Address to be read from read capture buffer. The address is referenced to the location of the buffer corresponding to the oldest data captured (i.e. location 0 is the oldest captured data). A write to this register will strobe the init_read_capture_data 'holding register' with new data from the specified address. The first subsequent read to init_read_capture_data will get this data from the 'holding register'; thus an update of init_read_capture_addr should only occur after the read data has been captured in the controller and the controller is quiesced (not performing new local bus or csr initiated reads). The read capture buffer has a depth based on the frequency ratio and the supported memory type. For memory controller configurations that support LPDDR4 memory, the depth is as follows: Frequency ratio 1 - depth is 8 entries Frequency ratio 2 - depth is 4 entries Frequency ratio 4 - depth is 2 entries For all other memory controller configurations, the depth is as follows: Frequency ratio 1 - depth is 4 entries Frequency ratio 2 - depth is 2 entries Frequency ratio 4 - depth is 1 entry | RW | 0x0

### DDR_CSR_APB : INIT_READ_CAPTURE_DATA_0

Address offset | 0x0 5C04
Physical address | 0x2008 5C04 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | init_read_capture_data_0 | A read returns data from read capture buffer holding register that must first be set to the new value at an offset set by a write to the 'init_read_capture_addr'. Each read of the 'init_read_capture_data' register will automatically increment the read address after the read to the next location of the buffer and update the read capture buffer holding register with the new data to allow efficiently reading the locations sequentially. Note that the user must not initiate any new memory device reads that will update read capture buffer, until the init_read_caputre buffer has been read-out for the prior memory device read. | RO | 0x0000 0000

### DDR_CSR_APB : INIT_READ_CAPTURE_DATA_1

Address offset | 0x0 5C08
Physical address | 0x2008 5C08 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | init_read_capture_data_1 | A read returns data from read capture buffer holding register that must first be set to the new value at an offset set by a write to the 'init_read_capture_addr'. Each read of the 'init_read_capture_data' register will automatically increment the read address after the read to the next location of the buffer and update the read capture buffer holding register with the new data to allow efficiently reading the locations sequentially. Note that the user must not initiate any new memory device reads that will update read capture buffer, until the init_read_caputre buffer has been read-out for the prior memory device read. | RO | 0x0000 0000

### DDR_CSR_APB : INIT_READ_CAPTURE_DATA_2

Address offset | 0x0 5C0C
Physical address | 0x2008 5C0C | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | init_read_capture_data_2 | A read returns data from read capture buffer holding register that must first be set to the new value at an offset set by a write to the 'init_read_capture_addr'. Each read of the 'init_read_capture_data' register will automatically increment the read address after the read to the next location of the buffer and update the read capture buffer holding register with the new data to allow efficiently reading the locations sequentially. Note that the user must not initiate any new memory device reads that will update read capture buffer, until the init_read_caputre buffer has been read-out for the prior memory device read. | RO | 0x0000 0000

### DDR_CSR_APB : INIT_READ_CAPTURE_DATA_3

Address offset | 0x0 5C10
Physical address | 0x2008 5C10 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | init_read_capture_data_3 | A read returns data from read capture buffer holding register that must first be set to the new value at an offset set by a write to the 'init_read_capture_addr'. Each read of the 'init_read_capture_data' register will automatically increment the read address after the read to the next location of the buffer and update the read capture buffer holding register with the new data to allow efficiently reading the locations sequentially. Note that the user must not initiate any new memory device reads that will update read capture buffer, until the init_read_caputre buffer has been read-out for the prior memory device read. | RO | 0x0000 0000

### DDR_CSR_APB : INIT_READ_CAPTURE_DATA_4

Address offset | 0x0 5C14
Physical address | 0x2008 5C14 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | reserved |  | RO | 0x0000
15:0 | init_read_capture_data_4 | A read returns data from read capture buffer holding register that must first be set to the new value at an offset set by a write to the 'init_read_capture_addr'. Each read of the 'init_read_capture_data' register will automatically increment the read address after the read to the next location of the buffer and update the read capture buffer holding register with the new data to allow efficiently reading the locations sequentially. Note that the user must not initiate any new memory device reads that will update read capture buffer, until the init_read_caputre buffer has been read-out for the prior memory device read. | RO | 0x0000

### DDR_CSR_APB : CFG_ERROR_GROUP_SEL

Address offset | 0x0 6400
Physical address | 0x2008 6400 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_error_group_sel | Specify compressed error bus or actual data bytes for storage. Refer to Memory Test Analyzer Core User Guide. 0 - Actual bytes/byte lanes are stored 1 - Compressed error bus stored. | RW | 0

### DDR_CSR_APB : CFG_DATA_SEL

Address offset | 0x0 6404
Physical address | 0x2008 6404 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved |  | RO | 0x000 0000
6:0 | cfg_data_sel | Select byte lane or compressed error bus for storage. Refer to the Memory Test Analyzer Core User Guide. | RW | 0x00

### DDR_CSR_APB : CFG_TRIG_MODE

Address offset | 0x0 6408
Physical address | 0x2008 6408 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_trig_mode | Used by the Memory Test Analyzer Core and Data Analyzer Core. Refer to the respective core User Guides for details. If 1: Acquisition acquires continuously on acq_en, stopping after the trigger by cfg_acq_cycs_post_trig. If 0: Acquisition acquires without trigger on acq_en | RW | 0

### DDR_CSR_APB : CFG_POST_TRIG_CYCS

Address offset | 0x0 640C
Physical address | 0x2008 640C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved |  | RO | 0x000 0000
6:0 | cfg_post_trig_cycs | Defines the number of acq_en qualified cycles to store after the trigger (including the trigger cycle) | RW | 0x00

### DDR_CSR_APB : CFG_TRIG_MASK

Address offset | 0x0 6410
Physical address | 0x2008 6410 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | reserved |  | RO | 0x0000 0000
2:0 | cfg_trig_mask | Bits of AND trigger bus to mask (address match, error, valid = [2:0]). Refer to the Memory Test Analyzer Core User Guide. Trigger on: 3'b000 - valid cycles where error occurs on an address match 3'b010 - valid cycles with an address match 3'b100 - valid cycles with an error 3'b110 - valid cycles All other bit combinations reserved. | RW | 0x0

### DDR_CSR_APB : CFG_EN_MASK

Address offset | 0x0 6414
Physical address | 0x2008 6414 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_en_mask | Bits of AND enable bus to mask (error, valid = [1:0]). Refer to the Memory Test Analyzer Core User Guide. Store data in Acquisition Memory on: 2'b00 - Valid cycles containing errors 2'b10 - Valid cycles All other bit combinations reserved. | RW | 0x0

### DDR_CSR_APB : MTC_ACQ_ADDR

Address offset | 0x0 6418
Physical address | 0x2008 6418 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | mtc_acq_addr | Address to initialize Capture Memory Address (with 'acq_addr_wr_en') | RW | 0x00

### DDR_CSR_APB : MTC_ACQ_CYCS_STORED

Address offset | 0x0 641C
Physical address | 0x2008 641C | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | reserved |  | RO | 0x000 0000
6:0 | mtc_acq_cycs_stored | Number of vectors stored with last armed acquisition. Note: This value is not synchonized for CSR readout with coherency of the bits. It is assumed that this register is only read when the memory test is idle. | RO | 0x00

### DDR_CSR_APB : MTC_ACQ_TRIG_DETECT

Address offset | 0x0 6420
Physical address | 0x2008 6420 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | mtc_acq_trig_detect | Indicates if trigger was detected in last armed acquisition | RO | 0

### DDR_CSR_APB : MTC_ACQ_MEM_TRIG_ADDR

Address offset | 0x0 6424
Physical address | 0x2008 6424 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | mtc_acq_mem_trig_addr | Memory address corresponding to trigger vector. Note: This value is not synchonized for CSR readout with coherency of the bits. It is assumed that this register is only read when the memory test is idle. | RO | 0x00

### DDR_CSR_APB : MTC_ACQ_MEM_LAST_ADDR

Address offset | 0x0 6428
Physical address | 0x2008 6428 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | mtc_acq_mem_last_addr | Memory address of last stored vector. Note: This value is not synchonized for CSR readout with coherency of the bits. It is assumed that this register is only read when the memory test is idle. | RO | 0x00

### DDR_CSR_APB : MTC_ACK

Address offset | 0x0 642C
Physical address | 0x2008 642C | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | mtc_ack | Set to acknowledge completion of read or write of acquisition memory, or to write of acquisition memory address in Memory Test Analyzer Core. | RO RtoClr | 0

### DDR_CSR_APB : CFG_TRIG_MT_ADDR_0

Address offset | 0x0 6430
Physical address | 0x2008 6430 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_trig_mt_addr_0 | Specify match address for triggered address mode | RW | 0x0000 0000

### DDR_CSR_APB : CFG_TRIG_MT_ADDR_1

Address offset | 0x0 6434
Physical address | 0x2008 6434 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | reserved |  | RO | 0x000 0000
6:0 | cfg_trig_mt_addr_1 | Specify match address for triggered address mode | RW | 0x00

### DDR_CSR_APB : CFG_TRIG_ERR_MASK_0

Address offset | 0x0 6438
Physical address | 0x2008 6438 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_trig_err_mask_0 | Per-bit mask for memory errors (affect trigger, enable, and error acquisition) | RW | 0x0000 0000

### DDR_CSR_APB : CFG_TRIG_ERR_MASK_1

Address offset | 0x0 643C
Physical address | 0x2008 643C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_trig_err_mask_1 | Per-bit mask for memory errors (affect trigger, enable, and error acquisition) | RW | 0x0000 0000

### DDR_CSR_APB : CFG_TRIG_ERR_MASK_2

Address offset | 0x0 6440
Physical address | 0x2008 6440 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_trig_err_mask_2 | Per-bit mask for memory errors (affect trigger, enable, and error acquisition) | RW | 0x0000 0000

### DDR_CSR_APB : CFG_TRIG_ERR_MASK_3

Address offset | 0x0 6444
Physical address | 0x2008 6444 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_trig_err_mask_3 | Per-bit mask for memory errors (affect trigger, enable, and error acquisition) | RW | 0x0000 0000

### DDR_CSR_APB : CFG_TRIG_ERR_MASK_4

Address offset | 0x0 6448
Physical address | 0x2008 6448 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved |  | RO | 0x0000
15:0 | cfg_trig_err_mask_4 | Per-bit mask for memory errors (affect trigger, enable, and error acquisition) | RW | 0x0000

### DDR_CSR_APB : MTC_ACQ_WR_DATA_0

Address offset | 0x0 644C
Physical address | 0x2008 644C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | mtc_acq_wr_data_0 | Write Data for Capture Memory Debug | RW | 0x0000 0000

### DDR_CSR_APB : MTC_ACQ_WR_DATA_1

Address offset | 0x0 6450
Physical address | 0x2008 6450 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | mtc_acq_wr_data_1 | Write Data for Capture Memory Debug | RW | 0x0000 0000

### DDR_CSR_APB : MTC_ACQ_WR_DATA_2

Address offset | 0x0 6454
Physical address | 0x2008 6454 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | mtc_acq_wr_data_2 | Write Data for Capture Memory Debug | RW | 0x00

### DDR_CSR_APB : MTC_ACQ_RD_DATA_0

Address offset | 0x0 6458
Physical address | 0x2008 6458 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | mtc_acq_rd_data_0 | Read Data for Capture Memory Read back | RO | 0x0000 0000

### DDR_CSR_APB : MTC_ACQ_RD_DATA_1

Address offset | 0x0 645C
Physical address | 0x2008 645C | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | mtc_acq_rd_data_1 | Read Data for Capture Memory Read back | RO | 0x0000 0000

### DDR_CSR_APB : MTC_ACQ_RD_DATA_2

Address offset | 0x0 6460
Physical address | 0x2008 6460 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | mtc_acq_rd_data_2 | Read Data for Capture Memory Read back | RO | 0x00

### DDR_CSR_APB : CFG_PRE_TRIG_CYCS

Address offset | 0x0 652C
Physical address | 0x2008 652C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved |  | RO | 0x0000
15:0 | cfg_pre_trig_cycs | Defines the number of acq_en qualified cycles to skip before enabling storage for subsequent cycles. | RW | 0x0000

### DDR_CSR_APB : MTC_ACQ_ERROR_CNT

Address offset | 0x0 6538
Physical address | 0x2008 6538 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | reserved |  | RO | 0x00 0000
9:0 | mtc_acq_error_cnt | Number of errors detected in the current acquisition. | RO | 0x000

### DDR_CSR_APB : MTC_ACQ_ERROR_CNT_OVFL

Address offset | 0x0 6544
Physical address | 0x2008 6544 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | mtc_acq_error_cnt_ovfl | The mtc_acq_error_cnt counter has overflowed. | RO | 0

### DDR_CSR_APB : CFG_DATA_SEL_FIRST_ERROR

Address offset | 0x0 6550
Physical address | 0x2008 6550 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_data_sel_first_error | Select first byte lane with compressed error bus bit set for storage. Has priority over cfg_data_sel setting. Refer to the Memory Test Analyzer Core User Guide. | RW | 0

### DDR_CSR_APB : CFG_DQ_WIDTH

Address offset | 0x0 7C00
Physical address | 0x2008 7C00 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_dq_width | Variable DQ width. 0 - Full-Width 1 - Half-Width 2 - Quarter-Width | RW | 0x0

### DDR_CSR_APB : CFG_ACTIVE_DQ_SEL

Address offset | 0x0 7C04
Physical address | 0x2008 7C04 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_active_dq_sel | Selectable active DQ. 0 - Word/Byte 0 1 - Word/Byte 1 2 - Word/Byte 2 3 - Word/Byte 3 | RW | 0x0

### DDR_CSR_APB : STAT_CA_PARITY_ERROR

Address offset | 0x0 8000
Physical address | 0x2008 8000 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | stat_ca_parity_error | For DDR4: Asserts when an assertion is detected on the 'ALERT_n' pin. Each occurrence of a write CRC error or CA parity error will cause assertion of the DDR4 device 'ALERT_n' pin. For HBM: Asserts when an assertion is detected on the 'AERR' pin. Each occurrence of an address parity error will cause an assertion of the HBM device 'AERR' pin. The value is cleared on read. | RO RtoClr | 0

### DDR_CSR_APB : INIT_CA_PARITY_ERROR_GEN_REQ

Address offset | 0x0 800C
Physical address | 0x2008 800C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_ca_parity_error_gen_req | When asserted, causes parity error to be introduced on command/address bus on the next command corresponding to that specified in the init_ca_parity_error_gen_cmd register. The parity error is generated by inverting the 'parity_in' bit going to the PHY from the calculated even parity value. Only one parity error is introduced per 'init_ca_parity_error_gen_req' / 'init_ca_parity_error_gen_ack' cycle. | RW | 0

### DDR_CSR_APB : INIT_CA_PARITY_ERROR_GEN_CMD

Address offset | 0x0 8010
Physical address | 0x2008 8010 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | init_ca_parity_error_gen_cmd | Specifies command for which parity error will be generated when 'init_ca_parity_error_gen_req' is asserted. The controller will wait for this command before generating the error. Command encoding is as follows: 0x0 - Reserved 0x1 - Reserved 0x2 - Reserved 0x3 - Reserved 0x4 - Reserved 0x5 - Reserved 0x6 - Reserved 0x7 - ACT 0x8 - MRS 0x9 - REF 0xa - PRE / PREA 0xb - Reserved 0xc - WR/WRA 0xd - RD/RDA 0xe - ZQ-Cal 0xf - NOP | RW | 0x0

### DDR_CSR_APB : INIT_CA_PARITY_ERROR_GEN_ACK

Address offset | 0x0 8014
Physical address | 0x2008 8014 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_ca_parity_error_gen_ack | Asserted to acknowledge 'init_ca_parity_error_gen_req'. | RO RtoClr | 0

### DDR_CSR_APB : CFG_DFI_T_RDDATA_EN

Address offset | 0x1 0000
Physical address | 0x2009 0000 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | cfg_dfi_t_rddata_en | Used to derive the delay from assertion of read command to dfi_rddata_en assertion at the DFI interface. The resulting delay, referred to as tRDDATA_EN in the DFI specification, is calculated below. Full-Rate: CAS read latency + Additive Latency + Parity Latency (DDR4 only) + Command Address Latency (DDR4 only) + cfg_regdimm + cfg_dfi_t_rddata_en - 9 Half-Rate: CAS read latency + Additive Latency + Parity Latency (DDR4 only) + Command Address Latency (DDR4 only) + cfg_regdimm + cfg_dfi_t_rddata_en - 19 Quarter-Rate: CAS read latency + Additive Latency + Parity Latency (DDR4 only) + Command Address Latency (DDR4 only) + cfg_regdimm + cfg_dfi_t_rddata_en - 36 This value is typically established as a constant for a particular PHY and is not intended to be changed from its reset value. Since the tRDDATA_EN that the controller generates is a function of the programmed latencies, cfg_dfi_t_rddata_en does not need to be reprogrammed whenever the latencies are changed. | RW | 0x14

### DDR_CSR_APB : CFG_DFI_T_PHY_RDLAT

Address offset | 0x1 0004
Physical address | 0x2009 0004 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_dfi_t_phy_rdlat | Number of memory clocks from assertion of dfi_rddata_en to dfi_rddata_valid assertion. This parameter is only valid for PHY configurations where the dfi_rddata_valid is generated within the controller and the dfi_rddata_valid from the PHY is unused or unavailable. When the controller is generating the dfi_rddata_valid, this value is set based on PHY requirements. | RW | 0x05

### DDR_CSR_APB : CFG_DFI_T_PHY_WRLAT

Address offset | 0x1 0008
Physical address | 0x2009 0008 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | cfg_dfi_t_phy_wrlat | Used to derive the delay from assertion of the write command to dfi_wrdata_en assertion at the DFI interface. The resulting delay, referred to as tPHY_WRLAT in the DFI specification, is calculated below. Full-Rate: CAS write latency + Additive Latency + Parity Latency (DDR4 only) + Command Address Latency (DDR4 only) + cfg_regdimm + cfg_dfi_t_phy_wrlat - 3 Half-Rate: CAS write latency + Additive Latency + Parity Latency (DDR4 only) + Command Address Latency (DDR4 only) + cfg_regdimm + cfg_dfi_t_phy_wrlat - 6 Quarter-Rate: CAS write latency + Additive Latency + Parity Latency (DDR4 only) + Command Address Latency (DDR4 only) + cfg_regdimm + cfg_dfi_t_phy_wrlat - 12 This value is typically established as a constant for a particular PHY and is not intended to be changed from its reset value. Since the tPHY_WRLAT that the controller generates is a function of the programmed latencies, cfg_dfi_phy_wrlat does not need to be reprogrammed whenever the latencies are changed. | RW | 0x05

### DDR_CSR_APB : CFG_DFI_PHYUPD_EN

Address offset | 0x1 000C
Physical address | 0x2009 000C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_dfi_phyupd_en | For PHYs using dfi_phyupd_req, this register can configure the PHY not to assert requests during initialization or test sequences where the update requests could cause interference with the controller. | RW | 1

### DDR_CSR_APB : INIT_DFI_LP_DATA_REQ

Address offset | 0x1 0010
Physical address | 0x2009 0010 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_dfi_lp_data_req | Value applied to dfi_lp_data_req on DFI interface to PHY. | RW | 0

### DDR_CSR_APB : INIT_DFI_LP_CTRL_REQ

Address offset | 0x1 0014
Physical address | 0x2009 0014 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | init_dfi_lp_ctrl_req | Value applied to dfi_lp_ctrl_req on DFI interface to PHY. | RW | 0

### DDR_CSR_APB : STAT_DFI_LP_ACK

Address offset | 0x1 0018
Physical address | 0x2009 0018 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | stat_dfi_lp_ack | Status of dfi_lp_ack on DFI interface from PHY. | RO RtoClr | 0

### DDR_CSR_APB : INIT_DFI_LP_WAKEUP

Address offset | 0x1 001C
Physical address | 0x2009 001C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | init_dfi_lp_wakeup | Value applied to dfi_lp_wakeup on DFI interface to PHY. | RW | 0x0

### DDR_CSR_APB : INIT_DFI_DRAM_CLK_DISABLE

Address offset | 0x1 0020
Physical address | 0x2009 0020 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | init_dfi_dram_clk_disable | Value applied to dfi_dram_clk_disable on DFI interface to PHY. | RW | 0x0

### DDR_CSR_APB : STAT_DFI_TRAINING_ERROR

Address offset | 0x1 0024
Physical address | 0x2009 0024 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | stat_dfi_training_error | Status of dfi_training_error on DFI interface from PHY. | RO | 0

### DDR_CSR_APB : STAT_DFI_ERROR

Address offset | 0x1 0028
Physical address | 0x2009 0028 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | stat_dfi_error | Status of dfi_error on DFI interface from PHY. | RO RtoClr | 0

### DDR_CSR_APB : STAT_DFI_ERROR_INFO

Address offset | 0x1 002C
Physical address | 0x2009 002C | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | stat_dfi_error_info | Status of dfi_error_info on DFI interface from PHY. | RO | 0x0

### DDR_CSR_APB : CFG_DFI_DATA_BYTE_DISABLE

Address offset | 0x1 0030
Physical address | 0x2009 0030 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | reserved |  | RO | 0x000 0000
4:0 | cfg_dfi_data_byte_disable | Value applied to dfi_data_byte_disable on DFI interface to PHY. | RW | 0x00

### DDR_CSR_APB : STAT_DFI_INIT_COMPLETE

Address offset | 0x1 0034
Physical address | 0x2009 0034 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | stat_dfi_init_complete | Status of dfi_init_complete on DFI interface from PHY. | RO | 0

### DDR_CSR_APB : STAT_DFI_TRAINING_COMPLETE

Address offset | 0x1 0038
Physical address | 0x2009 0038 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | stat_dfi_training_complete | Status of dfi_training_complete on DFI interface from PHY. | RO | 0

### DDR_CSR_APB : CFG_DFI_LVL_SEL

Address offset | 0x1 003C
Physical address | 0x2009 003C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_dfi_lvl_sel | Mux select for dfi_lvl_periodic and dfi_lvl_pattern. 0 - PHY initialization module controls signals 1 - CSR control | RW | 0

### DDR_CSR_APB : CFG_DFI_LVL_PERIODIC

Address offset | 0x1 0040
Physical address | 0x2009 0040 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_dfi_lvl_periodic | Training length indicator. | RW | 0

### DDR_CSR_APB : CFG_DFI_LVL_PATTERN

Address offset | 0x1 0044
Physical address | 0x2009 0044 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | cfg_dfi_lvl_pattern | Training pattern used for read training. | RW | 0x0

### DDR_CSR_APB : PHY_DFI_INIT_START

Address offset | 0x1 0050
Physical address | 0x2009 0050 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | phy_dfi_init_start | Set the init start signal into the PHY | RW | 0

### DDR_CSR_APB : CFG_AXI_START_ADDRESS_AXI1_0

Address offset | 0x1 2C18
Physical address | 0x2009 2C18 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_axi_start_address_axi1_0 | Sets the lower valid AXI address boundary for this AXI Interface. The AXI Interface Core will respond with a DECERR (decode error) response to AXI read and write requests with an address value less than this port setting. The Verilog parameter ADDR_MAP_SIG_BITS sets the number of significant bits that are used in the address value comparison. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_AXI_START_ADDRESS_AXI1_1

Address offset | 0x1 2C1C
Physical address | 0x2009 2C1C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_axi_start_address_axi1_1 | Sets the lower valid AXI address boundary for this AXI Interface. The AXI Interface Core will respond with a DECERR (decode error) response to AXI read and write requests with an address value less than this port setting. The Verilog parameter ADDR_MAP_SIG_BITS sets the number of significant bits that are used in the address value comparison. | RW | 0x0

### DDR_CSR_APB : CFG_AXI_START_ADDRESS_AXI2_0

Address offset | 0x1 2C20
Physical address | 0x2009 2C20 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_axi_start_address_axi2_0 | Sets the lower valid AXI address boundary for this AXI Interface. The AXI Interface Core will respond with a DECERR (decode error) response to AXI read and write requests with an address value less than this port setting. The Verilog parameter ADDR_MAP_SIG_BITS sets the number of significant bits that are used in the address value comparison. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_AXI_START_ADDRESS_AXI2_1

Address offset | 0x1 2C24
Physical address | 0x2009 2C24 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_axi_start_address_axi2_1 | Sets the lower valid AXI address boundary for this AXI Interface. The AXI Interface Core will respond with a DECERR (decode error) response to AXI read and write requests with an address value less than this port setting. The Verilog parameter ADDR_MAP_SIG_BITS sets the number of significant bits that are used in the address value comparison. | RW | 0x0

### DDR_CSR_APB : CFG_AXI_END_ADDRESS_AXI1_0

Address offset | 0x1 2F18
Physical address | 0x2009 2F18 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_axi_end_address_axi1_0 | Sets the upper valid AXI address boundary for this AXI Interface. The AXI Interface Core will respond with a DECERR (decode error) response to AXI read and write requests with an address value greater than this port setting. The Verilog parameter ADDR_MAP_SIG_BITS sets the number of significant bits that are used in the address value comparison. | RW | 0xFFFF FFFF

### DDR_CSR_APB : CFG_AXI_END_ADDRESS_AXI1_1

Address offset | 0x1 2F1C
Physical address | 0x2009 2F1C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_axi_end_address_axi1_1 | Sets the upper valid AXI address boundary for this AXI Interface. The AXI Interface Core will respond with a DECERR (decode error) response to AXI read and write requests with an address value greater than this port setting. The Verilog parameter ADDR_MAP_SIG_BITS sets the number of significant bits that are used in the address value comparison. | RW | 0x3

### DDR_CSR_APB : CFG_AXI_END_ADDRESS_AXI2_0

Address offset | 0x1 2F20
Physical address | 0x2009 2F20 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_axi_end_address_axi2_0 | Sets the upper valid AXI address boundary for this AXI Interface. The AXI Interface Core will respond with a DECERR (decode error) response to AXI read and write requests with an address value greater than this port setting. The Verilog parameter ADDR_MAP_SIG_BITS sets the number of significant bits that are used in the address value comparison. | RW | 0xFFFF FFFF

### DDR_CSR_APB : CFG_AXI_END_ADDRESS_AXI2_1

Address offset | 0x1 2F24
Physical address | 0x2009 2F24 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_axi_end_address_axi2_1 | Sets the upper valid AXI address boundary for this AXI Interface. The AXI Interface Core will respond with a DECERR (decode error) response to AXI read and write requests with an address value greater than this port setting. The Verilog parameter ADDR_MAP_SIG_BITS sets the number of significant bits that are used in the address value comparison. | RW | 0x3

### DDR_CSR_APB : CFG_MEM_START_ADDRESS_AXI1_0

Address offset | 0x1 3218
Physical address | 0x2009 3218 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_mem_start_address_axi1_0 | Memory controller address offset for this AXI Interface. The value of cfg_mem_start_address is subtracted off of every AXI read and write request before being submitted to the memory controller. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_MEM_START_ADDRESS_AXI1_1

Address offset | 0x1 321C
Physical address | 0x2009 321C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_mem_start_address_axi1_1 | Memory controller address offset for this AXI Interface. The value of cfg_mem_start_address is subtracted off of every AXI read and write request before being submitted to the memory controller. | RW | 0x0

### DDR_CSR_APB : CFG_MEM_START_ADDRESS_AXI2_0

Address offset | 0x1 3220
Physical address | 0x2009 3220 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_mem_start_address_axi2_0 | Memory controller address offset for this AXI Interface. The value of cfg_mem_start_address is subtracted off of every AXI read and write request before being submitted to the memory controller. | RW | 0x0000 0000

### DDR_CSR_APB : CFG_MEM_START_ADDRESS_AXI2_1

Address offset | 0x1 3224
Physical address | 0x2009 3224 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | reserved |  | RO | 0x0000 0000
1:0 | cfg_mem_start_address_axi2_1 | Memory controller address offset for this AXI Interface. The value of cfg_mem_start_address is subtracted off of every AXI read and write request before being submitted to the memory controller. | RW | 0x0

### DDR_CSR_APB : CFG_ENABLE_BUS_HOLD_AXI1

Address offset | 0x1 3514
Physical address | 0x2009 3514 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_enable_bus_hold_axi1 | For this AXI Interface, enables bus hold function that will stop arbitration in the MPFE when the read reorder buffer is full | RW | 0

### DDR_CSR_APB : CFG_ENABLE_BUS_HOLD_AXI2

Address offset | 0x1 3518
Physical address | 0x2009 3518 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | cfg_enable_bus_hold_axi2 | For this AXI Interface, enables bus hold function that will stop arbitration in the MPFE when the read reorder buffer is full | RW | 0

### DDR_CSR_APB : CFG_AXI_AUTO_PCH

Address offset | 0x1 3690
Physical address | 0x2009 3690 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | cfg_axi_auto_pch | This is AXI interface register that can be configured to be 8, 16, or 32 bits wide depending upon the number of AXI ports supported. Bit 0 of this register is always associated with axi port 0, bit 1 with axi port 1, etc. If port Y uses a local bus interface, then cfg_axi_auto_pch[Y] is not used and is considered a don't care. If it is an axi port input, cfg_axi_auto_pch serves solely as the auto_pch control for that AXI port. When cfg_axi_auto_pch is set and a long (multibeat) AXI read or write is issued by user logic, then the NWL axi interface logic will insure that only the last sdram controller request being issued (on behalf of a single long AXI request) asserts auto_precharge. If a reorder core is included and is enabled (cfg_reorder_queue_en = 1), then cfg_ro_closed_page_policy, when set, overrides the cfg_axi_auto_pch input and forces auto_pch asserted on all outgoing requests from the reoder core. | RW | 0x0000 0000

### DDR_CSR_APB : PHY_RESET_CONTROL

Address offset | 0x3 C000
Physical address | 0x200B C000 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved |  | RO | 0x0000
15:0 | phy_reset_control | Reset control register | RW | 0x000D

### DDR_CSR_APB : PHY_PC_RANK

Address offset | 0x3 C004
Physical address | 0x200B C004 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | reserved |  | RO | 0x000 0000
3:0 | phy_pc_rank | Select which rank to be trained. | RW | 0x0

### DDR_CSR_APB : PHY_RANKS_TO_TRAIN

Address offset | 0x3 C008
Physical address | 0x200B C008 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | reserved |  | RO | 0x0000
15:0 | phy_ranks_to_train | One hot encoding of which ranks to train during automatic initialization. | RW | 0x0000

### DDR_CSR_APB : PHY_WRITE_REQUEST

Address offset | 0x3 C00C
Physical address | 0x200B C00C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | phy_write_request | Request the memory controller to write to the SDRAM. Writes the eye training pattern into location 0 in the SDRAM | RW | 0

### DDR_CSR_APB : PHY_WRITE_REQUEST_DONE

Address offset | 0x3 C010
Physical address | 0x200B C010 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | phy_write_request_done | Indicate write request is completed | RO RtoClr | 0

### DDR_CSR_APB : PHY_READ_REQUEST

Address offset | 0x3 C014
Physical address | 0x200B C014 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | phy_read_request | Request the memory controller to read from the SDRAM. Intended for gate training and eye training | RW | 0

### DDR_CSR_APB : PHY_READ_REQUEST_DONE

Address offset | 0x3 C018
Physical address | 0x200B C018 | Instance | DDRCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | phy_read_request_done | Indicate read request is completed | RO RtoClr | 0

### DDR_CSR_APB : PHY_WRITE_LEVEL_DELAY

Address offset | 0x3 C01C
Physical address | 0x200B C01C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | phy_write_level_delay | Number of cycles to allow PHY response before sending another strobe. | RW | 0x00

### DDR_CSR_APB : PHY_GATE_TRAIN_DELAY

Address offset | 0x3 C020
Physical address | 0x200B C020 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | phy_gate_train_delay | Number of cycles to allow PHY response before sending the next read command. | RW | 0x00

### DDR_CSR_APB : PHY_EYE_TRAIN_DELAY

Address offset | 0x3 C024
Physical address | 0x200B C024 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | phy_eye_train_delay | Number of cycles to allow PHY response before sending the next read command. | RW | 0x00

### DDR_CSR_APB : PHY_EYE_PAT

Address offset | 0x3 C028
Physical address | 0x200B C028 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | reserved |  | RO | 0x00 0000
7:0 | phy_eye_pat | Eye training pattern to be loaded into the phy and the SDRAM | RW | 0x00

### DDR_CSR_APB : PHY_START_RECAL

Address offset | 0x3 C02C
Physical address | 0x200B C02C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | phy_start_recal | Rerun write leveling, gate training, and eye training. | RW | 0

### DDR_CSR_APB : PHY_CLR_DFI_LVL_PERIODIC

Address offset | 0x3 C030
Physical address | 0x200B C030 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | phy_clr_dfi_lvl_periodic | Clear PHY init SM Periodic Training incremental enable | RW | 0

### DDR_CSR_APB : PHY_TRAIN_STEP_ENABLE

Address offset | 0x3 C034
Physical address | 0x200B C034 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | reserved |  | RO | 0x000 0000
5:0 | phy_train_step_enable | PHY init state machine training step/stage enables, [5]: CA training, [4]: write leveling, [3]: read leveling, [2:0]: reserved | RW | 0x00

### DDR_CSR_APB : PHY_LPDDR_DQ_CAL_PAT

Address offset | 0x3 C038
Physical address | 0x200B C038 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | phy_lpddr_dq_cal_pat | LPDDR2/3 DQ training pattern, 0:A,1010_1010,MR32 1:B,0011_0011,MR40 | RW | 0

### DDR_CSR_APB : PHY_INDPNDT_TRAINING

Address offset | 0x3 C03C
Physical address | 0x200B C03C | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | phy_indpndt_training | Set to 1'b1 to indicate that the PHY will perform training without requiring interaction from the MC. The PHY will start training at the assertion of ctrlr_init_done and will signal completion with dfi_training_complete. | RW | 0

### DDR_CSR_APB : PHY_ENCODED_QUAD_CS

Address offset | 0x3 C040
Physical address | 0x200B C040 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | phy_encoded_quad_cs | Set to indicate configuration with DDR4 RDIMMs that have four ranks that encode chip-select down to 3 bits. When this port is set to '1', sd_cs_n[2:0] will only be used to designate rank selection to the RCD device. Refer to the JEDEC DDR4RCD01 DDR4 Registering Clock Driver (RCD) specification for details on how the Encoded Quad CS is used in an RDIMM application. | RW | 0

### DDR_CSR_APB : PHY_HALF_CLK_DLY_ENABLE

Address offset | 0x3 C044
Physical address | 0x200B C044 | Instance | DDRCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | reserved |  | RO | 0x0000 0000
0 | phy_half_clk_dly_enable | Set to enable 1/2 clock output delay of DQ/DQS datapath. Used to Align with RCD 1/2 clock delay. | RW | 0

DDR_CSR_APB has no common memories.