## SPI

This section provides information on the SPI Module Instance. Each of the module registers is described below.

Return to pfsoc_mss_regmap

## SPI Register Mapping Summary

### SPI Common Register Mapping Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset
CONTROL | RW | 32 | 0x8000 0102 | 0x000
FRAMESIZE | RW | 32 | 0x0000 0004 | 0x004
STATUS | RO | 32 | 0x0000 2440 | 0x008
INT_CLEAR | RW | 32 | 0x0000 0000 | 0x00C
RX_DATA | RO | 32 | 0x0000 0000 | 0x010
TX_DATA | WO | 32 | 0x0000 0000 | 0x014
CLK_GEN | RW | 32 | 0x0000 0007 | 0x018
SLAVE_SELECT | RW | 32 | 0x0000 0000 | 0x01C
INTMASK | RO | 32 | 0x0000 0000 | 0x020
INTRAW | RO | 32 | 0x0000 0000 | 0x024
CONTROL2 | RW | 32 | 0x0000 0000 | 0x028
COMMAND | RW | 32 | 0x0000 0000 | 0x02C
PKTSIZE | RW | 32 | 0x0000 0000 | 0x030
CMD_SIZE | RW | 32 | 0x0000 0000 | 0x034
HWSTATUS | RW | 32 | 0x0000 0000 | 0x038
STAT8 | RW | 32 | 0x0000 0044 | 0x03C
CTRL0 | RW | 32 | 0x0000 0002 | 0x040
CTRL1 | RW | 32 | 0x0000 0001 | 0x044
CTRL2 | RW | 32 | 0x0000 0000 | 0x048
CTRL3 | RW | 32 | 0x0000 0080 | 0x04C
FRAMESUP | RW | 32 | 0x0000 0001 | 0x050

## SPI Instances Mapping Summary

### SPI : SPI_A_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CONTROL | RW | 32 | 0x8000 0102 | 0x000 | 0x2010 8000
FRAMESIZE | RW | 32 | 0x0000 0004 | 0x004 | 0x2010 8004
STATUS | RO | 32 | 0x0000 2440 | 0x008 | 0x2010 8008
INT_CLEAR | RW | 32 | 0x0000 0000 | 0x00C | 0x2010 800C
RX_DATA | RO | 32 | 0x0000 0000 | 0x010 | 0x2010 8010
TX_DATA | WO | 32 | 0x0000 0000 | 0x014 | 0x2010 8014
CLK_GEN | RW | 32 | 0x0000 0007 | 0x018 | 0x2010 8018
SLAVE_SELECT | RW | 32 | 0x0000 0000 | 0x01C | 0x2010 801C
INTMASK | RO | 32 | 0x0000 0000 | 0x020 | 0x2010 8020
INTRAW | RO | 32 | 0x0000 0000 | 0x024 | 0x2010 8024
CONTROL2 | RW | 32 | 0x0000 0000 | 0x028 | 0x2010 8028
COMMAND | RW | 32 | 0x0000 0000 | 0x02C | 0x2010 802C
PKTSIZE | RW | 32 | 0x0000 0000 | 0x030 | 0x2010 8030
CMD_SIZE | RW | 32 | 0x0000 0000 | 0x034 | 0x2010 8034
HWSTATUS | RW | 32 | 0x0000 0000 | 0x038 | 0x2010 8038
STAT8 | RW | 32 | 0x0000 0044 | 0x03C | 0x2010 803C
CTRL0 | RW | 32 | 0x0000 0002 | 0x040 | 0x2010 8040
CTRL1 | RW | 32 | 0x0000 0001 | 0x044 | 0x2010 8044
CTRL2 | RW | 32 | 0x0000 0000 | 0x048 | 0x2010 8048
CTRL3 | RW | 32 | 0x0000 0080 | 0x04C | 0x2010 804C
FRAMESUP | RW | 32 | 0x0000 0001 | 0x050 | 0x2010 8050

### SPI : SPI_B_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CONTROL | RW | 32 | 0x8000 0102 | 0x000 | 0x2010 9000
FRAMESIZE | RW | 32 | 0x0000 0004 | 0x004 | 0x2010 9004
STATUS | RO | 32 | 0x0000 2440 | 0x008 | 0x2010 9008
INT_CLEAR | RW | 32 | 0x0000 0000 | 0x00C | 0x2010 900C
RX_DATA | RO | 32 | 0x0000 0000 | 0x010 | 0x2010 9010
TX_DATA | WO | 32 | 0x0000 0000 | 0x014 | 0x2010 9014
CLK_GEN | RW | 32 | 0x0000 0007 | 0x018 | 0x2010 9018
SLAVE_SELECT | RW | 32 | 0x0000 0000 | 0x01C | 0x2010 901C
INTMASK | RO | 32 | 0x0000 0000 | 0x020 | 0x2010 9020
INTRAW | RO | 32 | 0x0000 0000 | 0x024 | 0x2010 9024
CONTROL2 | RW | 32 | 0x0000 0000 | 0x028 | 0x2010 9028
COMMAND | RW | 32 | 0x0000 0000 | 0x02C | 0x2010 902C
PKTSIZE | RW | 32 | 0x0000 0000 | 0x030 | 0x2010 9030
CMD_SIZE | RW | 32 | 0x0000 0000 | 0x034 | 0x2010 9034
HWSTATUS | RW | 32 | 0x0000 0000 | 0x038 | 0x2010 9038
STAT8 | RW | 32 | 0x0000 0044 | 0x03C | 0x2010 903C
CTRL0 | RW | 32 | 0x0000 0002 | 0x040 | 0x2010 9040
CTRL1 | RW | 32 | 0x0000 0001 | 0x044 | 0x2010 9044
CTRL2 | RW | 32 | 0x0000 0000 | 0x048 | 0x2010 9048
CTRL3 | RW | 32 | 0x0000 0080 | 0x04C | 0x2010 904C
FRAMESUP | RW | 32 | 0x0000 0001 | 0x050 | 0x2010 9050

### SPI : SPI_A_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CONTROL | RW | 32 | 0x8000 0102 | 0x000 | 0x2810 8000
FRAMESIZE | RW | 32 | 0x0000 0004 | 0x004 | 0x2810 8004
STATUS | RO | 32 | 0x0000 2440 | 0x008 | 0x2810 8008
INT_CLEAR | RW | 32 | 0x0000 0000 | 0x00C | 0x2810 800C
RX_DATA | RO | 32 | 0x0000 0000 | 0x010 | 0x2810 8010
TX_DATA | WO | 32 | 0x0000 0000 | 0x014 | 0x2810 8014
CLK_GEN | RW | 32 | 0x0000 0007 | 0x018 | 0x2810 8018
SLAVE_SELECT | RW | 32 | 0x0000 0000 | 0x01C | 0x2810 801C
INTMASK | RO | 32 | 0x0000 0000 | 0x020 | 0x2810 8020
INTRAW | RO | 32 | 0x0000 0000 | 0x024 | 0x2810 8024
CONTROL2 | RW | 32 | 0x0000 0000 | 0x028 | 0x2810 8028
COMMAND | RW | 32 | 0x0000 0000 | 0x02C | 0x2810 802C
PKTSIZE | RW | 32 | 0x0000 0000 | 0x030 | 0x2810 8030
CMD_SIZE | RW | 32 | 0x0000 0000 | 0x034 | 0x2810 8034
HWSTATUS | RW | 32 | 0x0000 0000 | 0x038 | 0x2810 8038
STAT8 | RW | 32 | 0x0000 0044 | 0x03C | 0x2810 803C
CTRL0 | RW | 32 | 0x0000 0002 | 0x040 | 0x2810 8040
CTRL1 | RW | 32 | 0x0000 0001 | 0x044 | 0x2810 8044
CTRL2 | RW | 32 | 0x0000 0000 | 0x048 | 0x2810 8048
CTRL3 | RW | 32 | 0x0000 0080 | 0x04C | 0x2810 804C
FRAMESUP | RW | 32 | 0x0000 0001 | 0x050 | 0x2810 8050

### SPI : SPI_B_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CONTROL | RW | 32 | 0x8000 0102 | 0x000 | 0x2810 9000
FRAMESIZE | RW | 32 | 0x0000 0004 | 0x004 | 0x2810 9004
STATUS | RO | 32 | 0x0000 2440 | 0x008 | 0x2810 9008
INT_CLEAR | RW | 32 | 0x0000 0000 | 0x00C | 0x2810 900C
RX_DATA | RO | 32 | 0x0000 0000 | 0x010 | 0x2810 9010
TX_DATA | WO | 32 | 0x0000 0000 | 0x014 | 0x2810 9014
CLK_GEN | RW | 32 | 0x0000 0007 | 0x018 | 0x2810 9018
SLAVE_SELECT | RW | 32 | 0x0000 0000 | 0x01C | 0x2810 901C
INTMASK | RO | 32 | 0x0000 0000 | 0x020 | 0x2810 9020
INTRAW | RO | 32 | 0x0000 0000 | 0x024 | 0x2810 9024
CONTROL2 | RW | 32 | 0x0000 0000 | 0x028 | 0x2810 9028
COMMAND | RW | 32 | 0x0000 0000 | 0x02C | 0x2810 902C
PKTSIZE | RW | 32 | 0x0000 0000 | 0x030 | 0x2810 9030
CMD_SIZE | RW | 32 | 0x0000 0000 | 0x034 | 0x2810 9034
HWSTATUS | RW | 32 | 0x0000 0000 | 0x038 | 0x2810 9038
STAT8 | RW | 32 | 0x0000 0044 | 0x03C | 0x2810 903C
CTRL0 | RW | 32 | 0x0000 0002 | 0x040 | 0x2810 9040
CTRL1 | RW | 32 | 0x0000 0001 | 0x044 | 0x2810 9044
CTRL2 | RW | 32 | 0x0000 0000 | 0x048 | 0x2810 9048
CTRL3 | RW | 32 | 0x0000 0080 | 0x04C | 0x2810 904C
FRAMESUP | RW | 32 | 0x0000 0001 | 0x050 | 0x2810 9050

## SPI Register Descriptions

### SPI : CONTROL

Address offset | 0x000
Physical address | 0x2010 8000 | Instance | SPI_A_LO
| 0x2010 9000 |  | SPI_B_LO
| 0x2810 8000 |  | SPI_A_HI
| 0x2810 9000 |  | SPI_B_HI
Description | Control register
Type | RW

Bits | Field Name | Description | Type | Reset
31 | RESET | 0: SPI is enabled 1: SPI is held in Power reset state. | RW | 1
30 | OENOFF | 0: SPI output enable active as required 1: SPI output enable is not asserted. Allows multiple slaves to share a single slave select signal with a single master. | RW | 0
29 | BIGFIFO | Alters FIFO depth. 0: FIFO depth is 4 frames. 1: when frame size is [4-8] bits: FIFO depth is 32 frames. when frame size is [9-16] bits: FIFO depth is 16; and when frame size is [17-32] bits: FIFO depth is 8. | RW | 0
28 | CLK_MODE | Specifies the methodology used to calculate the SPICLK divider. 0: SPICLK = 1 / (2 ^ (CLK_GEN + 1)) where CLK_GEN = 0 to 15. 1: SPICLK = 1 / (2 * (CLK_GEN + 1)) where CLK_GEN = 0 to 255 | RW | 0
27 | FRAMEURUN | 0: The under-runs are generated whenever a read is attempted from an empty transmit FIFO. 1: The under-run condition will be ignored for the complete frame.. if the first data frame read resulted in a potential overflow; that is.. the slave was not ready to transmit any data. If the first data frame is read from the FIFO and transmitted.. an under-run will be generated.. when the FIFO becomes empty for any of the remaining packet frames (that is.. while SSEL is active). Master operation does not create a transmit FIFO under-run condition. | RW | 0
26 | SPS | Defines slave select behavior. | RW | 0
25 | SPH | Clock phase | RW | 0
24 | SPO | Clock polarity | RW | 0
23:8 | FRAMECNT | Number of data frames to be sent or received. Counts from 1. Maximum value is 64K. This register once set will not change, an internal frame counter counts the frames until it reaches the limit set by this register When this register is return, the internal frame counter also reset. When that counter reaches FRAMECNT, interrupts are generated and idle cycles are inserted on the SPI bus. The core will transmit data whenever the transmit FIFO is loaded, the counter is used to count frames, terminate bursts and generate interrupts | RW | 0x0001
7 | INTTXTURUN | Interrupt on transmit the under-run 0: Interrupt disabled 1: Interrupt enabled | RW | 0
6 | INTRXOVRFLO | Interrupt on receive overflow 0: Interrupt disable 1: Interrupt enabled | RW | 0
5 | INTTXDATA | Interrupt on transmit data 0: Interrupt disabled 1: Interrupt enabled | RW | 0
4 | INTRXDATA | Interrupt on receive data 0: Interrupt disabled 1: Interrupt enabled | RW | 0
3:2 | TRANSFPRTL | Transfer protocol Decode: 0b00: Motorola SPI 0b01: TI synchronous serial 0b10: National Semiconductor MICROWIRE 0b11: Reserved Note: The transfer protocol cannot be changed while the SPI is enabled. | RW | 0x0
1 | MODE | SPI implementation 0: Slave 1: Master (default) | RW | 1
0 | ENABLE | Core enable 0: Disable (default) 1: Enable The core will not respond to external signals (SPI_X_DI..SPI_X_DO) until this bit is enabled. SPI_X_CLK is driven low and SPI_X_OEN and SPI_X_SS (slave select) are driven inactive. | RW | 0

### SPI : FRAMESIZE

Address offset | 0x004
Physical address | 0x2010 8004 | Instance | SPI_A_LO
| 0x2010 9004 |  | SPI_B_LO
| 0x2810 8004 |  | SPI_A_HI
| 0x2810 9004 |  | SPI_B_HI
Description | Transmit and receive data frame size
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved |  | RO Rreturns0s | 0x000 0000
5:0 | FRAMESIZE | Transmit and receive data size. Default:4 Maximum value is 32. Number of bits shifted out and received per frame (count starts from 1 to 32). In National Semiconductor MICROWIRE mode.. this is the number of shifts to be done after the control byte is sent. Note: This register must be set before SPI is enabled. Writes to this register are ignored after the SPI is enabled. | RW | 0x04

### SPI : STATUS

Address offset | 0x008
Physical address | 0x2010 8008 | Instance | SPI_A_LO
| 0x2010 9008 |  | SPI_B_LO
| 0x2810 8008 |  | SPI_A_HI
| 0x2810 9008 |  | SPI_B_HI
Description | Status register
Type | RO

Bits | Field Name | Description | Type | Reset
31:15 | Reserved |  | RO Rreturns0s | 0x0 0000
14 | ACTIVE | SPI is still transmitting or receiving data. | RO | 0
13 | SSEL | Current state of SPI_X_SS[0] | RO | 1
12 | FRAMESTART | Indicates that the next frame in the receive FIFO was the first received after SSEL went active, i.e. the start of a packet of frames | RO | 0
11 | TXFIFOEMPNXT | Transmit FIFO will be empty after next transmission | RO | 0
10 | TXFIFOEMP | Transmit FIFO is empty | RO | 1
9 | TXFIFOFULNXT | Transmit FIFO full on next write | RO | 0
8 | TXFIFOFUL | Transmit FIFO is full | RO | 0
7 | RXFIFOEMPNXT | Receive FIFO empty on next read | RO | 0
6 | RXFIFOEMP | Receive FIFO empty | RO | 1
5 | RXFIFOFULNXT | Receive FIFO will be full after next frame received | RO | 0
4 | RXFIFOFUL | Receive FIFO is full | RO | 0
3 | TXUNDERRUN | No data available for transmission. The channel cannot read data from the transmit FIFO because the transmit FIFO is empty. Certainly this can only be raised in Slave mode because the master will not attempt to transmit unless there is data in FIFO. | RO | 0
2 | RXOVERFLOW | Channel is unable to write to receive FIFO as it is full. Applies to Master and Slave modes. | RO | 0
1 | RXDATRCED | When set.. it indicates that the number of frames specified by TxRXDFCOUNT has been received and can be read. Applies to Master and Slave modes. | RO | 0
0 | TXDATSENT | When set.. it indicates that the numbers of frames specified by TxRXDFCOUNT has been sent. Applies to Master and Slave modes. | RO | 0

### SPI : INT_CLEAR

Address offset | 0x00C
Physical address | 0x2010 800C | Instance | SPI_A_LO
| 0x2010 900C |  | SPI_B_LO
| 0x2810 800C |  | SPI_A_HI
| 0x2810 900C |  | SPI_B_HI
Description | Interrupt clear register
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved |  | RO Rreturns0s | 0x000 0000
5 | SSEND | Write one to clear the interrupt | WO | 0
4 | CMDINT | Write one to clear the interrupt | WO | 0
3 | TXCHUNDRUN | Transmit channel under-run | WO | 0
2 | RXCHOVRFLW | Receive channel over flow | WO | 0
1 | RXRDONECLR | Clears receive ready (RX_RDY) | WO | 0
0 | TXDONECLR | Clears transmit done (TX_DONE) by writing '1' | WO | 0

### SPI : RX_DATA

Address offset | 0x010
Physical address | 0x2010 8010 | Instance | SPI_A_LO
| 0x2010 9010 |  | SPI_B_LO
| 0x2810 8010 |  | SPI_A_HI
| 0x2810 9010 |  | SPI_B_HI
Description | Receive data register
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | RXDATA | Received data. Reading this clears the register of the received data. | RO | 0x0000 0000

### SPI : TX_DATA

Address offset | 0x014
Physical address | 0x2010 8014 | Instance | SPI_A_LO
| 0x2010 9014 |  | SPI_B_LO
| 0x2810 8014 |  | SPI_A_HI
| 0x2810 9014 |  | SPI_B_HI
Description | Transmit data register
Type | WO

Bits | Field Name | Description | Type | Reset
31:0 | TXDATA | Data to be transmitted. Writing to this clears the last data transmitted. | WO | 0x0000 0000

### SPI : CLK_GEN

Address offset | 0x018
Physical address | 0x2010 8018 | Instance | SPI_A_LO
| 0x2010 9018 |  | SPI_B_LO
| 0x2810 8018 |  | SPI_A_HI
| 0x2810 9018 |  | SPI_B_HI
Description | Output clock generator (Master mode)
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | CLK_GEN | Specifies the methodology used to calculate the SPICLK divider. CLK_MODE = 0: SPICLK = 1 / (2^(CLK_GEN + 1)) where CLK_GEN = 0 to 15. CLK_MODE = 1: SPICLK = 1 / (2 * (CLK_GEN + 1)) where CLK_GEN = 0 to 255. | RW | 0x07

### SPI : SLAVE_SELECT

Address offset | 0x01C
Physical address | 0x2010 801C | Instance | SPI_A_LO
| 0x2010 901C |  | SPI_B_LO
| 0x2810 801C |  | SPI_A_HI
| 0x2810 901C |  | SPI_B_HI
Description | Specifies slave selected (Master mode)
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | Reserved |  | RO Rreturns0s | 0x00 0000
9 | SSELOUT | 0: SSEL is inactive (Driven to 1) 1: SSEL is active (Driven to 0) | RW | 0
8 | DIRECT | 0: SSEL is driven by the FSM's 1: SSEL is driven by bit 9 in this register | RW | 0
7:0 | SLAVESELECT | Specifies the slave selected. Writing one to a bit position selects the corresponding slave. One SLAVESELECT[1] is available at the FPGA fabric interface.. while SLAVESELECT[0] is available at the SPI_X_SS[0] pin. Note: The slave select output signal is active low. | RW | 0x00

### SPI : INTMASK

Address offset | 0x020
Physical address | 0x2010 8020 | Instance | SPI_A_LO
| 0x2010 9020 |  | SPI_B_LO
| 0x2810 8020 |  | SPI_A_HI
| 0x2810 9020 |  | SPI_B_HI
Description | Masked interrupt status
Type | RO

Bits | Field Name | Description | Type | Reset
31:6 | Reserved |  | RO Rreturns0s | 0x000 0000
5 | SSEND | Equals RIS[5] and CONTROL2[5]. When this is high.. the interrupt is active. | RO | 0
4 | CMDINT | Equals RIS[4] and CONTROL2[4]. When this is high.. the interrupt is active. | RO | 0
3 | TXCHUNDDMSKINT | Masked interrupt status. Reading this returns interrupt status. Masked interrupt status = Raw interrupt status and interrupt mask (Control Register). MIS = RIS and CONTROL[7:4]. Masked status of transmit channel under-run TXCHUNDMSKINT=TXCHUNDRINT and INTTXUNRRUN | RO | 0
2 | RXCHOVRFMSKINT | Masked status of receive channel overflow. RXCHOVRFMSKINT = RXCHOVRFINT and INTRXOVRFLO | RO | 0
1 | RXRDYMSKINT | Masked status of receive data ready (data received in FIFO). RXRDYMSKINT = RXRDY and INTTXDATA | RO | 0
0 | TXDONEMSKINT | Masked status of transmit done (data shifted out) TXDONEMSKINT = TXDONE and INTRXDATA | RO | 0

### SPI : INTRAW

Address offset | 0x024
Physical address | 0x2010 8024 | Instance | SPI_A_LO
| 0x2010 9024 |  | SPI_B_LO
| 0x2810 8024 |  | SPI_A_HI
| 0x2810 9024 |  | SPI_B_HI
Description | Raw interrupt status
Type | RO

Bits | Field Name | Description | Type | Reset
31:6 | Reserved |  | RO Rreturns0s | 0x000 0000
5 | SSEND | Indicates that SPI_X_SS[x] has gone inactive. | RO | 0
4 | CMDINT | Indicates that the number of frames set by the CMDSIZE register has been received as a single packet of frames (SPI_X_SS[x] held active). | RO | 0
3 | TXCHUNDR | RAW interrupt status. Reading this returns raw interrupt status. Raw status of transmit channel under-run. Indicates in slave mode that data was not availiable when required in the transmit FIFO | RO | 0
2 | RXOVRFLW | Raw status of receive FIFO overflowed | RO | 0
1 | RXRDY | Receive data ready (data received in FIFO) | RO | 0
0 | TXDONE | Raw status of transmit done (data shifted out) | RO | 0

### SPI : CONTROL2

Address offset | 0x028
Physical address | 0x2010 8028 | Instance | SPI_A_LO
| 0x2010 9028 |  | SPI_B_LO
| 0x2810 8028 |  | SPI_A_HI
| 0x2810 9028 |  | SPI_B_HI
Description | Control bits for enhanced modes
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved |  | RO Rreturns0s | 0x000 0000
5 | INTEN_SSEND | 0:No effect 1: Enables the interrupt as SPI_X_SS[x] has gone inactive. | RW | 0
4 | INTEN_CMD | 0: No effect. 1: Enables the interrupt after the number of frames set by the CMDSIZE register have been received as a single packet of frames (SPI_X_SS[x] held active). | RW | 0
3 | Reserved |  | RO Rreturns0s | 0
2 | DISFRMCNT | 0: The internal frame counter is active. When the counter reaches the programmed limit.. it will pause the current SPI transfer inserting idle cycles and generate the appropriate interrupts. 1: The internal frame counter is not active.The core transmits data until the transmit FIFO empties. The FRAMECNT (CONTROL register) should also be programmed to zero. | RW | 0
1 | AUTOPOLL | 0: No effect 1: The first receive frame after SPI_X_SS[0] is active. It is discarded (not written to the FIFO) and supports the POLL function. | RW | 0
0 | AUTOSTATUS | 0: No effect 1: The first transmitted frame (Slave mode) contains the hardware status.. not data from the transmit FIFO. | RW | 0

### SPI : COMMAND

Address offset | 0x02C
Physical address | 0x2010 802C | Instance | SPI_A_LO
| 0x2010 902C |  | SPI_B_LO
| 0x2810 802C |  | SPI_A_HI
| 0x2810 902C |  | SPI_B_HI
Description | Command register
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved |  | RO Rreturns0s | 0x000 0000
6 | TXNOW | 0: No effect 1: Writing 1 clears the TxBUSY bit in Slave mode immediately rather than waiting for PKTSIZE frames to be available.. telling the master that there is data available. This is intended to use when less than the programmed PKTSIZE data frames are being transmitted.. removing the requirement to transmit PKTSIZE frames. This bit stays set until the first data frame is transmitted. | RW | 0
5 | AUTOSTALL | 0: No effect 1: Writing 1 will cause the master to delay transmission until the transmit FIFO contains the number of frames specified by the PKTSIZE register. This guarantee that the frames are transmitted with no idle cycles or time gaps between them. This bit will be automatically cleared as soon as the core starts transmitting the frames. | RW | 0
4 | CLRFRAMECNT | 0: No effect 1: Writing 1 clears the internal frame counter. This bit always reads as zero. The counter is also cleared when the core is disabled.. CTL1.. or CTL2 are written (that is.. the frame count limit changed). | RW | 0
3 | TXFIFORST | 0: No effect 1: Writing 1 resets the Tx FIFO. This bit always reads as zero. | RW | 0
2 | RXFIFORST | 0: No effect Writing 1 resets the Rx FIFO. This bit always reads as zero. | RW | 0
1 | AUTOEMPTY | 0: No effect 1: Writing 1 causes the SPI core to automatically discard any further received data until the number of frames requested in the FRAMECNT register has been received or (in Slave mode) SSEL goes inactive. This bit will stay set until all the frames are complete or it is cleared. | RW | 0
0 | AUTOFILL | 0: No effect 1: Writing 1 causes the SPI core to automatically fill the transmit FIFO with zeros to match the number of frames requested in the FRAMECNT register. Typically.. the five command bytes must be written to the TxDATA register and then this bit must be set. Data can be read from the receive FIFO until the complete set of frames has been read. This bit will stay set until all the frames are complete or it is cleared. | RW | 0

### SPI : PKTSIZE

Address offset | 0x030
Physical address | 0x2010 8030 | Instance | SPI_A_LO
| 0x2010 9030 |  | SPI_B_LO
| 0x2810 8030 |  | SPI_A_HI
| 0x2810 9030 |  | SPI_B_HI
Description | Packet size
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved |  | RO Rreturns0s | 0x000 0000
5:0 | PKTSIZE | Sets the size of the SPI CMD/data frame. PKTSIZE cannot be greater than the FIFO size. | RW | 0x00

### SPI : CMD_SIZE

Address offset | 0x034
Physical address | 0x2010 8034 | Instance | SPI_A_LO
| 0x2010 9034 |  | SPI_B_LO
| 0x2810 8034 |  | SPI_A_HI
| 0x2810 9034 |  | SPI_B_HI
Description | Command size
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved |  | RO Rreturns0s | 0x000 0000
5:0 | CMDSIZE | Number of frames after SPI_SS[0] going active that the CMD interrupt should be generated. Note: This controls the RxCMD interrupt. The internal counters count frames from SPI_SS[0] going low. It automatically resets and starts counting again once SSEL goes inactive. In TI mode.. back- to-back frames are counted.. any gaps in data causes the counter to start counting again. | RW | 0x00

### SPI : HWSTATUS

Address offset | 0x038
Physical address | 0x2010 8038 | Instance | SPI_A_LO
| 0x2010 9038 |  | SPI_B_LO
| 0x2810 8038 |  | SPI_A_HI
| 0x2810 9038 |  | SPI_B_HI
Description | Slave hardware status
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | Reserved |  | RO Rreturns0s | 0x000 0000
3:2 | USER | These bits are set by the CPU. Their function is undefined but could be used to send additional status or request information to the master. | RW | 0x0
1 | TXBUSY | 0: Master may request the requested data. There are PKTSIZE frames of data in the transmit FIFO (when AUTOPOLL is set to PKTSIZE - 1) 1: Indicates not ready to transmit data. | RO | 0
0 | RXBUSY | 1: Indicates that the receive buffer is busy (not empty). 0: Indicates that up to PKTSIZE frames of command followed by data may be sent to the slave. | RO | 0

### SPI : STAT8

Address offset | 0x03C
Physical address | 0x2010 803C | Instance | SPI_A_LO
| 0x2010 903C |  | SPI_B_LO
| 0x2810 803C |  | SPI_A_HI
| 0x2810 903C |  | SPI_B_HI
Description | Status register
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7 | ACTIVE | SPI is still transmitting the data | RW | 0
6 | SSEL | Current state of SPI_X_SS[0] | RW | 1
5 | TXUNDERRUN | Transmit FIFO underflowed | RW | 0
4 | RXOVERFLOW | Receive FIFO overflowed | RW | 0
3 | TXFIFOFUL | Transmit FIFO is full | RW | 0
2 | RXFIFOEMP | Receive FIFO is empty | RW | 1
1 | DONE | The number of request frames have been transmitted and received. | RW | 0
0 | FRAMESTART | Next frame in receive FIFO was received after SPI_X_SS[x] went active (command frame). | RW | 0

### SPI : CTRL0

Address offset | 0x040
Physical address | 0x2010 8040 | Instance | SPI_A_LO
| 0x2010 9040 |  | SPI_B_LO
| 0x2810 8040 |  | SPI_A_HI
| 0x2810 9040 |  | SPI_B_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RW | 0x00 0000
7:0 | CTRL0 | Aliased CONTROL register bits 7:0. This register allows byte operations from an 8-bit processor in the fabric. It is not intended for access from internal MSS masters. | RW | 0x02

### SPI : CTRL1

Address offset | 0x044
Physical address | 0x2010 8044 | Instance | SPI_A_LO
| 0x2010 9044 |  | SPI_B_LO
| 0x2810 8044 |  | SPI_A_HI
| 0x2810 9044 |  | SPI_B_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RW | 0x00 0000
7:0 | CTRL1 | Aliased CONTROL register bits 15:8. This register allows byte operations from an 8-bit processor in the fabric. It is not intended for access from internal MSS masters. | RW | 0x01

### SPI : CTRL2

Address offset | 0x048
Physical address | 0x2010 8048 | Instance | SPI_A_LO
| 0x2010 9048 |  | SPI_B_LO
| 0x2810 8048 |  | SPI_A_HI
| 0x2810 9048 |  | SPI_B_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RW | 0x00 0000
7:0 | CTRL2 | Aliased CONTROL register bits 23:16. This register allows byte operations from an 8-bit processor in the fabric. It is not intended for access from internal MSS masters. | RW | 0x00

### SPI : CTRL3

Address offset | 0x04C
Physical address | 0x2010 804C | Instance | SPI_A_LO
| 0x2010 904C |  | SPI_B_LO
| 0x2810 804C |  | SPI_A_HI
| 0x2810 904C |  | SPI_B_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RW | 0x00 0000
7:0 | CTRL3 | Aliased CONTROL register bits 31:24. This register allows byte operations from an 8-bit processor in the fabric. It is not intended for access from internal MSS masters. | RW | 0x80

### SPI : FRAMESUP

Address offset | 0x050
Physical address | 0x2010 8050 | Instance | SPI_A_LO
| 0x2010 9050 |  | SPI_B_LO
| 0x2810 8050 |  | SPI_A_HI
| 0x2810 9050 |  | SPI_B_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | BYTESUPPER | W: Writes the upper 16 bits of the number of bytes to be transmitted. R: Returns the written value. | RW | 0x0000
15:0 | BYTESLOWER | W: No operation. R: Resturns the lower 16 bits of the byte count from the FRAMES register. | RW | 0x0001

SPI has no common memories.