## MMUART

Auto-generated by Socrates-Bitwise 1.13
Generation timestamp: 2021-12-06 03:49:22

This section provides information on the MMUART Module Instance. Each of the module registers is described below.

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## MMUART Register Mapping Summary

### MMUART Common Register Mapping Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset
RBR | RO | 32 | 0x0000 0000 | 0x000
IER | RW | 32 | 0x0000 0000 | 0x004
IIR | RO | 32 | 0x0000 00C1 | 0x008
LCR | RW | 32 | 0x0000 0000 | 0x00C
MCR | RW | 32 | 0x0000 0000 | 0x010
LSR | RO | 32 | 0x0000 0060 | 0x014
MSR | RO | 32 | 0x0000 0000 | 0x018
SR | RW | 32 | 0x0000 0000 | 0x01C
Reserved | RO | 32 | 0x0000 0000 | 0x020
IEM | RW | 32 | 0x0000 0000 | 0x024
IIM | RO | 32 | 0x0000 0000 | 0x028
Reserved_1 | RO | 32 | 0x0000 0000 | 0x02C
MM0 | RW | 32 | 0x0000 0000 | 0x030
MM1 | RW | 32 | 0x0000 0000 | 0x034
MM2 | RW | 32 | 0x0000 0000 | 0x038
DFR | RW | 32 | 0x0000 0000 | 0x03C
GFR | RW | 32 | 0x0000 0000 | 0x044
TTG | RW | 32 | 0x0000 0000 | 0x048
RTO | RW | 32 | 0x0000 0000 | 0x04C
ADR | RW | 32 | 0x0000 0000 | 0x050
DLR | RW | 32 | 0x0000 0001 | 0x080
DMR | RW | 32 | 0x0000 0000 | 0x084
THR | RW | 32 | 0x0000 0000 | 0x100
FCR | WO | 32 | 0x0000 00C1 | 0x108

## MMUART Instances Mapping Summary

### MMUART : MMUART0_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
RBR | RO | 32 | 0x0000 0000 | 0x000 | 0x2000 0000
IER | RW | 32 | 0x0000 0000 | 0x004 | 0x2000 0004
IIR | RO | 32 | 0x0000 00C1 | 0x008 | 0x2000 0008
LCR | RW | 32 | 0x0000 0000 | 0x00C | 0x2000 000C
MCR | RW | 32 | 0x0000 0000 | 0x010 | 0x2000 0010
LSR | RO | 32 | 0x0000 0060 | 0x014 | 0x2000 0014
MSR | RO | 32 | 0x0000 0000 | 0x018 | 0x2000 0018
SR | RW | 32 | 0x0000 0000 | 0x01C | 0x2000 001C
Reserved | RO | 32 | 0x0000 0000 | 0x020 | 0x2000 0020
IEM | RW | 32 | 0x0000 0000 | 0x024 | 0x2000 0024
IIM | RO | 32 | 0x0000 0000 | 0x028 | 0x2000 0028
Reserved_1 | RO | 32 | 0x0000 0000 | 0x02C | 0x2000 002C
MM0 | RW | 32 | 0x0000 0000 | 0x030 | 0x2000 0030
MM1 | RW | 32 | 0x0000 0000 | 0x034 | 0x2000 0034
MM2 | RW | 32 | 0x0000 0000 | 0x038 | 0x2000 0038
DFR | RW | 32 | 0x0000 0000 | 0x03C | 0x2000 003C
GFR | RW | 32 | 0x0000 0000 | 0x044 | 0x2000 0044
TTG | RW | 32 | 0x0000 0000 | 0x048 | 0x2000 0048
RTO | RW | 32 | 0x0000 0000 | 0x04C | 0x2000 004C
ADR | RW | 32 | 0x0000 0000 | 0x050 | 0x2000 0050
DLR | RW | 32 | 0x0000 0001 | 0x080 | 0x2000 0080
DMR | RW | 32 | 0x0000 0000 | 0x084 | 0x2000 0084
THR | RW | 32 | 0x0000 0000 | 0x100 | 0x2000 0100
FCR | WO | 32 | 0x0000 00C1 | 0x108 | 0x2000 0108

### MMUART : MMUART1_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
RBR | RO | 32 | 0x0000 0000 | 0x000 | 0x2010 0000
IER | RW | 32 | 0x0000 0000 | 0x004 | 0x2010 0004
IIR | RO | 32 | 0x0000 00C1 | 0x008 | 0x2010 0008
LCR | RW | 32 | 0x0000 0000 | 0x00C | 0x2010 000C
MCR | RW | 32 | 0x0000 0000 | 0x010 | 0x2010 0010
LSR | RO | 32 | 0x0000 0060 | 0x014 | 0x2010 0014
MSR | RO | 32 | 0x0000 0000 | 0x018 | 0x2010 0018
SR | RW | 32 | 0x0000 0000 | 0x01C | 0x2010 001C
Reserved | RO | 32 | 0x0000 0000 | 0x020 | 0x2010 0020
IEM | RW | 32 | 0x0000 0000 | 0x024 | 0x2010 0024
IIM | RO | 32 | 0x0000 0000 | 0x028 | 0x2010 0028
Reserved_1 | RO | 32 | 0x0000 0000 | 0x02C | 0x2010 002C
MM0 | RW | 32 | 0x0000 0000 | 0x030 | 0x2010 0030
MM1 | RW | 32 | 0x0000 0000 | 0x034 | 0x2010 0034
MM2 | RW | 32 | 0x0000 0000 | 0x038 | 0x2010 0038
DFR | RW | 32 | 0x0000 0000 | 0x03C | 0x2010 003C
GFR | RW | 32 | 0x0000 0000 | 0x044 | 0x2010 0044
TTG | RW | 32 | 0x0000 0000 | 0x048 | 0x2010 0048
RTO | RW | 32 | 0x0000 0000 | 0x04C | 0x2010 004C
ADR | RW | 32 | 0x0000 0000 | 0x050 | 0x2010 0050
DLR | RW | 32 | 0x0000 0001 | 0x080 | 0x2010 0080
DMR | RW | 32 | 0x0000 0000 | 0x084 | 0x2010 0084
THR | RW | 32 | 0x0000 0000 | 0x100 | 0x2010 0100
FCR | WO | 32 | 0x0000 00C1 | 0x108 | 0x2010 0108

### MMUART : MMUART2_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
RBR | RO | 32 | 0x0000 0000 | 0x000 | 0x2010 2000
IER | RW | 32 | 0x0000 0000 | 0x004 | 0x2010 2004
IIR | RO | 32 | 0x0000 00C1 | 0x008 | 0x2010 2008
LCR | RW | 32 | 0x0000 0000 | 0x00C | 0x2010 200C
MCR | RW | 32 | 0x0000 0000 | 0x010 | 0x2010 2010
LSR | RO | 32 | 0x0000 0060 | 0x014 | 0x2010 2014
MSR | RO | 32 | 0x0000 0000 | 0x018 | 0x2010 2018
SR | RW | 32 | 0x0000 0000 | 0x01C | 0x2010 201C
Reserved | RO | 32 | 0x0000 0000 | 0x020 | 0x2010 2020
IEM | RW | 32 | 0x0000 0000 | 0x024 | 0x2010 2024
IIM | RO | 32 | 0x0000 0000 | 0x028 | 0x2010 2028
Reserved_1 | RO | 32 | 0x0000 0000 | 0x02C | 0x2010 202C
MM0 | RW | 32 | 0x0000 0000 | 0x030 | 0x2010 2030
MM1 | RW | 32 | 0x0000 0000 | 0x034 | 0x2010 2034
MM2 | RW | 32 | 0x0000 0000 | 0x038 | 0x2010 2038
DFR | RW | 32 | 0x0000 0000 | 0x03C | 0x2010 203C
GFR | RW | 32 | 0x0000 0000 | 0x044 | 0x2010 2044
TTG | RW | 32 | 0x0000 0000 | 0x048 | 0x2010 2048
RTO | RW | 32 | 0x0000 0000 | 0x04C | 0x2010 204C
ADR | RW | 32 | 0x0000 0000 | 0x050 | 0x2010 2050
DLR | RW | 32 | 0x0000 0001 | 0x080 | 0x2010 2080
DMR | RW | 32 | 0x0000 0000 | 0x084 | 0x2010 2084
THR | RW | 32 | 0x0000 0000 | 0x100 | 0x2010 2100
FCR | WO | 32 | 0x0000 00C1 | 0x108 | 0x2010 2108

### MMUART : MMUART3_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
RBR | RO | 32 | 0x0000 0000 | 0x000 | 0x2010 4000
IER | RW | 32 | 0x0000 0000 | 0x004 | 0x2010 4004
IIR | RO | 32 | 0x0000 00C1 | 0x008 | 0x2010 4008
LCR | RW | 32 | 0x0000 0000 | 0x00C | 0x2010 400C
MCR | RW | 32 | 0x0000 0000 | 0x010 | 0x2010 4010
LSR | RO | 32 | 0x0000 0060 | 0x014 | 0x2010 4014
MSR | RO | 32 | 0x0000 0000 | 0x018 | 0x2010 4018
SR | RW | 32 | 0x0000 0000 | 0x01C | 0x2010 401C
Reserved | RO | 32 | 0x0000 0000 | 0x020 | 0x2010 4020
IEM | RW | 32 | 0x0000 0000 | 0x024 | 0x2010 4024
IIM | RO | 32 | 0x0000 0000 | 0x028 | 0x2010 4028
Reserved_1 | RO | 32 | 0x0000 0000 | 0x02C | 0x2010 402C
MM0 | RW | 32 | 0x0000 0000 | 0x030 | 0x2010 4030
MM1 | RW | 32 | 0x0000 0000 | 0x034 | 0x2010 4034
MM2 | RW | 32 | 0x0000 0000 | 0x038 | 0x2010 4038
DFR | RW | 32 | 0x0000 0000 | 0x03C | 0x2010 403C
GFR | RW | 32 | 0x0000 0000 | 0x044 | 0x2010 4044
TTG | RW | 32 | 0x0000 0000 | 0x048 | 0x2010 4048
RTO | RW | 32 | 0x0000 0000 | 0x04C | 0x2010 404C
ADR | RW | 32 | 0x0000 0000 | 0x050 | 0x2010 4050
DLR | RW | 32 | 0x0000 0001 | 0x080 | 0x2010 4080
DMR | RW | 32 | 0x0000 0000 | 0x084 | 0x2010 4084
THR | RW | 32 | 0x0000 0000 | 0x100 | 0x2010 4100
FCR | WO | 32 | 0x0000 00C1 | 0x108 | 0x2010 4108

### MMUART : MMUART4_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
RBR | RO | 32 | 0x0000 0000 | 0x000 | 0x2010 6000
IER | RW | 32 | 0x0000 0000 | 0x004 | 0x2010 6004
IIR | RO | 32 | 0x0000 00C1 | 0x008 | 0x2010 6008
LCR | RW | 32 | 0x0000 0000 | 0x00C | 0x2010 600C
MCR | RW | 32 | 0x0000 0000 | 0x010 | 0x2010 6010
LSR | RO | 32 | 0x0000 0060 | 0x014 | 0x2010 6014
MSR | RO | 32 | 0x0000 0000 | 0x018 | 0x2010 6018
SR | RW | 32 | 0x0000 0000 | 0x01C | 0x2010 601C
Reserved | RO | 32 | 0x0000 0000 | 0x020 | 0x2010 6020
IEM | RW | 32 | 0x0000 0000 | 0x024 | 0x2010 6024
IIM | RO | 32 | 0x0000 0000 | 0x028 | 0x2010 6028
Reserved_1 | RO | 32 | 0x0000 0000 | 0x02C | 0x2010 602C
MM0 | RW | 32 | 0x0000 0000 | 0x030 | 0x2010 6030
MM1 | RW | 32 | 0x0000 0000 | 0x034 | 0x2010 6034
MM2 | RW | 32 | 0x0000 0000 | 0x038 | 0x2010 6038
DFR | RW | 32 | 0x0000 0000 | 0x03C | 0x2010 603C
GFR | RW | 32 | 0x0000 0000 | 0x044 | 0x2010 6044
TTG | RW | 32 | 0x0000 0000 | 0x048 | 0x2010 6048
RTO | RW | 32 | 0x0000 0000 | 0x04C | 0x2010 604C
ADR | RW | 32 | 0x0000 0000 | 0x050 | 0x2010 6050
DLR | RW | 32 | 0x0000 0001 | 0x080 | 0x2010 6080
DMR | RW | 32 | 0x0000 0000 | 0x084 | 0x2010 6084
THR | RW | 32 | 0x0000 0000 | 0x100 | 0x2010 6100
FCR | WO | 32 | 0x0000 00C1 | 0x108 | 0x2010 6108

### MMUART : MMUART0_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
RBR | RO | 32 | 0x0000 0000 | 0x000 | 0x2800 0000
IER | RW | 32 | 0x0000 0000 | 0x004 | 0x2800 0004
IIR | RO | 32 | 0x0000 00C1 | 0x008 | 0x2800 0008
LCR | RW | 32 | 0x0000 0000 | 0x00C | 0x2800 000C
MCR | RW | 32 | 0x0000 0000 | 0x010 | 0x2800 0010
LSR | RO | 32 | 0x0000 0060 | 0x014 | 0x2800 0014
MSR | RO | 32 | 0x0000 0000 | 0x018 | 0x2800 0018
SR | RW | 32 | 0x0000 0000 | 0x01C | 0x2800 001C
Reserved | RO | 32 | 0x0000 0000 | 0x020 | 0x2800 0020
IEM | RW | 32 | 0x0000 0000 | 0x024 | 0x2800 0024
IIM | RO | 32 | 0x0000 0000 | 0x028 | 0x2800 0028
Reserved_1 | RO | 32 | 0x0000 0000 | 0x02C | 0x2800 002C
MM0 | RW | 32 | 0x0000 0000 | 0x030 | 0x2800 0030
MM1 | RW | 32 | 0x0000 0000 | 0x034 | 0x2800 0034
MM2 | RW | 32 | 0x0000 0000 | 0x038 | 0x2800 0038
DFR | RW | 32 | 0x0000 0000 | 0x03C | 0x2800 003C
GFR | RW | 32 | 0x0000 0000 | 0x044 | 0x2800 0044
TTG | RW | 32 | 0x0000 0000 | 0x048 | 0x2800 0048
RTO | RW | 32 | 0x0000 0000 | 0x04C | 0x2800 004C
ADR | RW | 32 | 0x0000 0000 | 0x050 | 0x2800 0050
DLR | RW | 32 | 0x0000 0001 | 0x080 | 0x2800 0080
DMR | RW | 32 | 0x0000 0000 | 0x084 | 0x2800 0084
THR | RW | 32 | 0x0000 0000 | 0x100 | 0x2800 0100
FCR | WO | 32 | 0x0000 00C1 | 0x108 | 0x2800 0108

### MMUART : MMUART1_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
RBR | RO | 32 | 0x0000 0000 | 0x000 | 0x2810 0000
IER | RW | 32 | 0x0000 0000 | 0x004 | 0x2810 0004
IIR | RO | 32 | 0x0000 00C1 | 0x008 | 0x2810 0008
LCR | RW | 32 | 0x0000 0000 | 0x00C | 0x2810 000C
MCR | RW | 32 | 0x0000 0000 | 0x010 | 0x2810 0010
LSR | RO | 32 | 0x0000 0060 | 0x014 | 0x2810 0014
MSR | RO | 32 | 0x0000 0000 | 0x018 | 0x2810 0018
SR | RW | 32 | 0x0000 0000 | 0x01C | 0x2810 001C
Reserved | RO | 32 | 0x0000 0000 | 0x020 | 0x2810 0020
IEM | RW | 32 | 0x0000 0000 | 0x024 | 0x2810 0024
IIM | RO | 32 | 0x0000 0000 | 0x028 | 0x2810 0028
Reserved_1 | RO | 32 | 0x0000 0000 | 0x02C | 0x2810 002C
MM0 | RW | 32 | 0x0000 0000 | 0x030 | 0x2810 0030
MM1 | RW | 32 | 0x0000 0000 | 0x034 | 0x2810 0034
MM2 | RW | 32 | 0x0000 0000 | 0x038 | 0x2810 0038
DFR | RW | 32 | 0x0000 0000 | 0x03C | 0x2810 003C
GFR | RW | 32 | 0x0000 0000 | 0x044 | 0x2810 0044
TTG | RW | 32 | 0x0000 0000 | 0x048 | 0x2810 0048
RTO | RW | 32 | 0x0000 0000 | 0x04C | 0x2810 004C
ADR | RW | 32 | 0x0000 0000 | 0x050 | 0x2810 0050
DLR | RW | 32 | 0x0000 0001 | 0x080 | 0x2810 0080
DMR | RW | 32 | 0x0000 0000 | 0x084 | 0x2810 0084
THR | RW | 32 | 0x0000 0000 | 0x100 | 0x2810 0100
FCR | WO | 32 | 0x0000 00C1 | 0x108 | 0x2810 0108

### MMUART : MMUART2_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
RBR | RO | 32 | 0x0000 0000 | 0x000 | 0x2810 2000
IER | RW | 32 | 0x0000 0000 | 0x004 | 0x2810 2004
IIR | RO | 32 | 0x0000 00C1 | 0x008 | 0x2810 2008
LCR | RW | 32 | 0x0000 0000 | 0x00C | 0x2810 200C
MCR | RW | 32 | 0x0000 0000 | 0x010 | 0x2810 2010
LSR | RO | 32 | 0x0000 0060 | 0x014 | 0x2810 2014
MSR | RO | 32 | 0x0000 0000 | 0x018 | 0x2810 2018
SR | RW | 32 | 0x0000 0000 | 0x01C | 0x2810 201C
Reserved | RO | 32 | 0x0000 0000 | 0x020 | 0x2810 2020
IEM | RW | 32 | 0x0000 0000 | 0x024 | 0x2810 2024
IIM | RO | 32 | 0x0000 0000 | 0x028 | 0x2810 2028
Reserved_1 | RO | 32 | 0x0000 0000 | 0x02C | 0x2810 202C
MM0 | RW | 32 | 0x0000 0000 | 0x030 | 0x2810 2030
MM1 | RW | 32 | 0x0000 0000 | 0x034 | 0x2810 2034
MM2 | RW | 32 | 0x0000 0000 | 0x038 | 0x2810 2038
DFR | RW | 32 | 0x0000 0000 | 0x03C | 0x2810 203C
GFR | RW | 32 | 0x0000 0000 | 0x044 | 0x2810 2044
TTG | RW | 32 | 0x0000 0000 | 0x048 | 0x2810 2048
RTO | RW | 32 | 0x0000 0000 | 0x04C | 0x2810 204C
ADR | RW | 32 | 0x0000 0000 | 0x050 | 0x2810 2050
DLR | RW | 32 | 0x0000 0001 | 0x080 | 0x2810 2080
DMR | RW | 32 | 0x0000 0000 | 0x084 | 0x2810 2084
THR | RW | 32 | 0x0000 0000 | 0x100 | 0x2810 2100
FCR | WO | 32 | 0x0000 00C1 | 0x108 | 0x2810 2108

### MMUART : MMUART3_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
RBR | RO | 32 | 0x0000 0000 | 0x000 | 0x2810 4000
IER | RW | 32 | 0x0000 0000 | 0x004 | 0x2810 4004
IIR | RO | 32 | 0x0000 00C1 | 0x008 | 0x2810 4008
LCR | RW | 32 | 0x0000 0000 | 0x00C | 0x2810 400C
MCR | RW | 32 | 0x0000 0000 | 0x010 | 0x2810 4010
LSR | RO | 32 | 0x0000 0060 | 0x014 | 0x2810 4014
MSR | RO | 32 | 0x0000 0000 | 0x018 | 0x2810 4018
SR | RW | 32 | 0x0000 0000 | 0x01C | 0x2810 401C
Reserved | RO | 32 | 0x0000 0000 | 0x020 | 0x2810 4020
IEM | RW | 32 | 0x0000 0000 | 0x024 | 0x2810 4024
IIM | RO | 32 | 0x0000 0000 | 0x028 | 0x2810 4028
Reserved_1 | RO | 32 | 0x0000 0000 | 0x02C | 0x2810 402C
MM0 | RW | 32 | 0x0000 0000 | 0x030 | 0x2810 4030
MM1 | RW | 32 | 0x0000 0000 | 0x034 | 0x2810 4034
MM2 | RW | 32 | 0x0000 0000 | 0x038 | 0x2810 4038
DFR | RW | 32 | 0x0000 0000 | 0x03C | 0x2810 403C
GFR | RW | 32 | 0x0000 0000 | 0x044 | 0x2810 4044
TTG | RW | 32 | 0x0000 0000 | 0x048 | 0x2810 4048
RTO | RW | 32 | 0x0000 0000 | 0x04C | 0x2810 404C
ADR | RW | 32 | 0x0000 0000 | 0x050 | 0x2810 4050
DLR | RW | 32 | 0x0000 0001 | 0x080 | 0x2810 4080
DMR | RW | 32 | 0x0000 0000 | 0x084 | 0x2810 4084
THR | RW | 32 | 0x0000 0000 | 0x100 | 0x2810 4100
FCR | WO | 32 | 0x0000 00C1 | 0x108 | 0x2810 4108

### MMUART : MMUART4_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
RBR | RO | 32 | 0x0000 0000 | 0x000 | 0x2810 6000
IER | RW | 32 | 0x0000 0000 | 0x004 | 0x2810 6004
IIR | RO | 32 | 0x0000 00C1 | 0x008 | 0x2810 6008
LCR | RW | 32 | 0x0000 0000 | 0x00C | 0x2810 600C
MCR | RW | 32 | 0x0000 0000 | 0x010 | 0x2810 6010
LSR | RO | 32 | 0x0000 0060 | 0x014 | 0x2810 6014
MSR | RO | 32 | 0x0000 0000 | 0x018 | 0x2810 6018
SR | RW | 32 | 0x0000 0000 | 0x01C | 0x2810 601C
Reserved | RO | 32 | 0x0000 0000 | 0x020 | 0x2810 6020
IEM | RW | 32 | 0x0000 0000 | 0x024 | 0x2810 6024
IIM | RO | 32 | 0x0000 0000 | 0x028 | 0x2810 6028
Reserved_1 | RO | 32 | 0x0000 0000 | 0x02C | 0x2810 602C
MM0 | RW | 32 | 0x0000 0000 | 0x030 | 0x2810 6030
MM1 | RW | 32 | 0x0000 0000 | 0x034 | 0x2810 6034
MM2 | RW | 32 | 0x0000 0000 | 0x038 | 0x2810 6038
DFR | RW | 32 | 0x0000 0000 | 0x03C | 0x2810 603C
GFR | RW | 32 | 0x0000 0000 | 0x044 | 0x2810 6044
TTG | RW | 32 | 0x0000 0000 | 0x048 | 0x2810 6048
RTO | RW | 32 | 0x0000 0000 | 0x04C | 0x2810 604C
ADR | RW | 32 | 0x0000 0000 | 0x050 | 0x2810 6050
DLR | RW | 32 | 0x0000 0001 | 0x080 | 0x2810 6080
DMR | RW | 32 | 0x0000 0000 | 0x084 | 0x2810 6084
THR | RW | 32 | 0x0000 0000 | 0x100 | 0x2810 6100
FCR | WO | 32 | 0x0000 00C1 | 0x108 | 0x2810 6108

## MMUART Register Descriptions

### MMUART : RBR

Address offset | 0x000
Physical address | 0x2000 0000 | Instance | MMUART0_LO
| 0x2010 0000 |  | MMUART1_LO
| 0x2010 2000 |  | MMUART2_LO
| 0x2010 4000 |  | MMUART3_LO
| 0x2010 6000 |  | MMUART4_LO
| 0x2800 0000 |  | MMUART0_HI
| 0x2810 0000 |  | MMUART1_HI
| 0x2810 2000 |  | MMUART2_HI
| 0x2810 4000 |  | MMUART3_HI
| 0x2810 6000 |  | MMUART4_HI
Description | Receiver buffer register
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | RBR | This register holds the receive data bits for MMUART_x. The default value is unknown since the register is loaded with data in the receive FIFO. Bit 0 is the LSB and it is the first bit received. It may be configured as the MSB by configuring the E_MSB_RX bit in the MM1. The divisor latch access bit (DLAB).. bit 7 of LCR.. must be 0 to read this register. This register is read only. Writing to this register with the DLAB 0 changes the transmit holding register (THR) register value. | RO | 0x00

### MMUART : IER

Address offset | 0x004
Physical address | 0x2000 0004 | Instance | MMUART0_LO
| 0x2010 0004 |  | MMUART1_LO
| 0x2010 2004 |  | MMUART2_LO
| 0x2010 4004 |  | MMUART3_LO
| 0x2010 6004 |  | MMUART4_LO
| 0x2800 0004 |  | MMUART0_HI
| 0x2810 0004 |  | MMUART1_HI
| 0x2810 2004 |  | MMUART2_HI
| 0x2810 4004 |  | MMUART3_HI
| 0x2810 6004 |  | MMUART4_HI
Description | Interrupt enable register
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | Reserved |  | RO Rreturns0s | 0x000 0000
3 | EDSSI | Modem status interrupt enable 0: Disabled (default) 1: Enabled | RW | 0
2 | ELSI | Receiver line status interrupt enable 0: Disabled (default) 1: Enabled | RW | 0
1 | ETBEI | Transmitter holding register empty interrupt enable 0: Disabled (default) 1: Enabled | RW | 0
0 | ERBFI | Enables received data available interrupt 0: Disabled (default) 1: Enabled | RW | 0

### MMUART : IIR

Address offset | 0x008
Physical address | 0x2000 0008 | Instance | MMUART0_LO
| 0x2010 0008 |  | MMUART1_LO
| 0x2010 2008 |  | MMUART2_LO
| 0x2010 4008 |  | MMUART3_LO
| 0x2010 6008 |  | MMUART4_LO
| 0x2800 0008 |  | MMUART0_HI
| 0x2810 0008 |  | MMUART1_HI
| 0x2810 2008 |  | MMUART2_HI
| 0x2810 4008 |  | MMUART3_HI
| 0x2810 6008 |  | MMUART4_HI
Description | Interrupt identification register
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:6 | Mode | Always 0b11. Enables FIFO mode. | RO | 0x3
5:4 | Reserved |  | RO Rreturns0s | 0x0
3:0 | IIR | Interrupt identification bits. 0b0110: Highest priority. Receiver line status interrupts due to overrun error.. parity error.. framing error.. or break interrupt. Reading the line status register resets this interrupt. 0b0100: Second priority. Receive data available interrupt modem status interrupt. Reading the receiver buffer register (RBR) or the FIFO drops below the trigger level resets this interrupt. 0b1100: Second priority. Character timeout indication interrupt occurs when no characters have been read from the Rx FIFO during the last four character times and there was at least one character in it during this time. Reading the RBR resets this interrupt. 0b0010: Third priority. Transmit holding register empty interrupt. Reading the IIR or writing to the transmit holding register (THR) resets the interrupt. 0b0000: Fourth priority. Modem status interrupt due to clear to send.. data set ready.. ring indicator.. or data carrier detect being asserted. Reading the modem status register resets this interrupt. 0b0011: Fifth priority. Multi-mode interrupts can occur due to any of the interrupts mentioned in IIM. For more details refer to Table 12-15. | RO | 0x1

### MMUART : LCR

Address offset | 0x00C
Physical address | 0x2000 000C | Instance | MMUART0_LO
| 0x2010 000C |  | MMUART1_LO
| 0x2010 200C |  | MMUART2_LO
| 0x2010 400C |  | MMUART3_LO
| 0x2010 600C |  | MMUART4_LO
| 0x2800 000C |  | MMUART0_HI
| 0x2810 000C |  | MMUART1_HI
| 0x2810 200C |  | MMUART2_HI
| 0x2810 400C |  | MMUART3_HI
| 0x2810 600C |  | MMUART4_HI
Description | Line control register
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7 | DLAB | Divisor latch access bit. Enables access to the divisor latch registers during read or write operation to address 0 and 1. 0: Disabled (default) 1: Enabled | RW | 0
6 | SB | Set break. Enabling this bit sets MMUART_x_TXD to 0. This does not have any effect on transmitter logic. The break is disabled by setting the bit to 0. 0: Disabled (default) 1: Set break | RW | 0
5 | SP | Stick parity 0: Disabled (default) 1: Enabled When stick parity is enabled.. the parity is set according to bits [4:3] as follows: 11: 0 will be sent as a parity bit and checked when receiving. 01: 1 will be sent as a parity bit and checked when receiving. | RW | 0
4 | EPS | Even parity select 0: Odd parity (default) 1: Even parity | RW | 0
3 | PEN | Parity enable 0: Disabled 1: Enabled. Parity is added in transmission and checked in receiving. | RW | 0
2 | STB | Number of stop bits (STB) 0: 1 stop bit (default) 1: 11/2 stop bits when WLS=00 The number of stop bits is 2 for all other cases not described above (STB=1 and WLS=01.. 10.. or 11). | RW | 0
1:0 | WLS | Word length select 0b00: 5 bits (default) 0b01: 6 bits 0b10: 7 bits 0b11: 8 bits | RW | 0x0

### MMUART : MCR

Address offset | 0x010
Physical address | 0x2000 0010 | Instance | MMUART0_LO
| 0x2010 0010 |  | MMUART1_LO
| 0x2010 2010 |  | MMUART2_LO
| 0x2010 4010 |  | MMUART3_LO
| 0x2010 6010 |  | MMUART4_LO
| 0x2800 0010 |  | MMUART0_HI
| 0x2810 0010 |  | MMUART1_HI
| 0x2810 2010 |  | MMUART2_HI
| 0x2810 4010 |  | MMUART3_HI
| 0x2810 6010 |  | MMUART4_HI
Description | Modem control register
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved |  | RO Rreturns0s | 0x000 0000
6:5 | RLoop | Remote loopback enable bits. In the Remote loopback mode.. when a bit is received.. it is sent directly out the transmit line.. bypassing the transmitter block.. and disabling the receiver. In the Automatic echo mode.. when a bit is received.. it is sent directly out the transmit line.. bypassing the transmitter block.. while the receiver is still enabled. 00: Disabled (default) 01: Remote loopback enabled 10: Automatic echo enabled 11: Reserved Note: Local loopback mode has priority over the remote/echo loopback modes. | RW | 0x0
4 | Loop | In the Loopback mode.. MMUART_x_TXD is set to 1. The MMUART_x_RXD.. MMUART_x_DSR.. MMUART_x_CTS.. MMUART_x_RI.. and MMUART_x_DCD inputs are disconnected. The output of the transmitter shift register is looped back into the receiver shift register. The modem control outputs (MMUART_x_DTR.. MMUART_x_RTS.. MMUART_x_OUT1.. and MMUART_x_OUT2) are connected internally to the modem control inputs.. and the modem control output pins are set as 1. The transmitted data is immediately received.. allowing Cortex-M3 processor to check the operation of the MMUART_x. The interrupts are operating in the Loopback mode. 0: Disabled (default) 1: Local loopback enabled Note: The local loopback mode has priority over the remote loopback modes. LOOPBACK is only implemented in basic UART mode. It does function in LIN IRDA or Smart card modes. | RW | 0
3 | OUT2 | Controls the output2 (OUT2) signal. Active Low 0: OUT2n is less than equal to 1 (default) 1: OUT2n is less than equal to 0 | RW | 0
2 | OUT1 | Controls the output1 (OUT1) signal. Active Low 0: OUT1n is less than equal to 1 (default) 1: OUT1n is less than equal to 0 | RW | 0
1 | RTS | Controls the request to send (MMUART_x_RTS) signal. Active Low 0: RTSn is less than equal to 1 (default) 1: RTSn is less than equal to 0 | RW | 0
0 | DTR | Data terminal ready (MMUART_x_DTR) output. Active Low 0: DTRn is less than or equal to 1 (default) 1: DTRn is less than or equal to 0 | RW | 0

### MMUART : LSR

Address offset | 0x014
Physical address | 0x2000 0014 | Instance | MMUART0_LO
| 0x2010 0014 |  | MMUART1_LO
| 0x2010 2014 |  | MMUART2_LO
| 0x2010 4014 |  | MMUART3_LO
| 0x2010 6014 |  | MMUART4_LO
| 0x2800 0014 |  | MMUART0_HI
| 0x2810 0014 |  | MMUART1_HI
| 0x2810 2014 |  | MMUART2_HI
| 0x2810 4014 |  | MMUART3_HI
| 0x2810 6014 |  | MMUART4_HI
Description | Line status register
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7 | FIER | This bit is set when there is at least one parity error.. framing error.. or break indication in the FIFO. FIER is cleared when Cortex-M3 processor reads the LSR.. if there are no subsequent errors in the FIFO. | RO | 0
6 | TEMT | Transmit empty (TEMT). This bit is set to 1 when both the transmitter FIFO and shift registers are empty. | RO | 1
5 | THRE | Transmitter holding register empty (THRE). Indicates that the MMUART_x is ready to transmit a new data byte. THRE causes an interrupt to the Cortex-M3 processor when bit 1 (ETBEI) in the interrupt enable register is 1. This bit is set when the Tx FIFO is empty. It is cleared when at least one byte is written to the Tx FIFO. | RO | 1
4 | BI | Break interrupt (BI). Indicates that the receive data is at 0 longer than a full word transmission time (start bit + data bits + parity + stop bits). BI is cleared when Cortex-M3 processor reads the line status register (LSR). This error is revealed to the Cortex-M3 processor when it is associated character is at the top of the FIFO. When break occurs.. only one zero character is loaded into the FIFO. | RO | 0
3 | FE | Framing error (FE). Indicates that the receive byte did not have a valid stop bit. FE is cleared when Cortex-M3 processor reads the LSR. The MMUART_x tries to resynchronize after a framing error. To do this.. it assumes that the framing error was due to the next start bit.. so it samples this start bit twice.. and then starts receiving the data. This error is revealed to Cortex-M3 processor when it is associated character is at the top of the FIFO. | RO | 0
2 | PE | Parity error (PE). Indicates that the receive byte had a parity error. PE is cleared when the Cortex-M3 processor reads the LSR. This error is revealed to the Cortex-M3 processor when it is associated character is at the top of the FIFO. | RO | 0
1 | OE | Overrun error (OE). Indicates that the new byte was received before the Cortex-M3 processor reads the byte from the receive buffer.. and that the earlier data byte was destroyed. OE is cleared when the Cortex-M3 processor reads the LSR. If the data continues to fill the FIFO beyond the trigger level.. an overrun error occurs once the FIFO is full and the next character has been completely received in the shift register. The character in the shift register is overwritten.. but it is not transferred to the FIFO. | RO | 0
0 | DR | Data ready (DR). 1: Indicates when a data byte is received and stored in the receive buffer or the FIFO. DR is cleared to 0 when the Cortex-M3 processor reads the data from the receive buffer or the FIFO. | RO | 0

### MMUART : MSR

Address offset | 0x018
Physical address | 0x2000 0018 | Instance | MMUART0_LO
| 0x2010 0018 |  | MMUART1_LO
| 0x2010 2018 |  | MMUART2_LO
| 0x2010 4018 |  | MMUART3_LO
| 0x2010 6018 |  | MMUART4_LO
| 0x2800 0018 |  | MMUART0_HI
| 0x2810 0018 |  | MMUART1_HI
| 0x2810 2018 |  | MMUART2_HI
| 0x2810 4018 |  | MMUART3_HI
| 0x2810 6018 |  | MMUART4_HI
Description | Modem status register
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7 | DCD | Data carrier detect (DCD) (MMUART_x_DCD).The complement of DCD input. When bit 4 of the MCR is set to 1 (loop).. this bit is equivalent to OUT2 in the MCR. | RO | 0
6 | RI | Ring indicator (RI) (MMUART_x_RI). The complement of the RI input. When bit 4 of the MCR is set to 1 (loop).. this bit is equivalent to OUT1 in the MCR. | RO | 0
5 | DSR | Data set ready (DSR) (MMUART_x_DSR). The complement of the DSR input. When bit 4 of the MCR is set to 1 (loop).. this bit is equivalent to RTS in the MCR. | RO | 0
4 | CTS | Clear to send (CTS) (MMUART_x_CTS). The complement of the CTS input. When bit 4 of the MCR is set to 1 (loop).. this bit is equivalent to DTR in the MCR. | RO | 0
3 | DDCD | Delta data carrier detect (DDCD) indicator. Indicates that DCD input has changed state. Whenever bit 0.. 1.. 2.. or 3 is set to 1.. a modem status interrupt is generated. | RO | 0
2 | TERI | Trailing edge of ring indicator (TERI) detector. Indicates that RI input has changed from 0 to 1. Whenever bit 0.. 1.. 2.. or 3 is set to 1.. a modem status interrupt is generated. | RO | 0
1 | DDSR | Delta data set ready (DDSR) indicator. Indicates that the DSRn input has changed state since the last time it was read by the Cortex-M3 processor. Whenever bit 0.. 1.. 2.. or 3 is set to 1.. a modem status interrupt is generated. | RO | 0
0 | DCTS | Delta clear to send (DCTS) indicator. Indicates that the CTSn input has changed state since the last time it was read by the Cortex-M3 processor. Whenever bit 0.. 1.. 2.. or 3 is set to 1.. a modem status interrupt is generated. | RO | 0

### MMUART : SR

Address offset | 0x01C
Physical address | 0x2000 001C | Instance | MMUART0_LO
| 0x2010 001C |  | MMUART1_LO
| 0x2010 201C |  | MMUART2_LO
| 0x2010 401C |  | MMUART3_LO
| 0x2010 601C |  | MMUART4_LO
| 0x2800 001C |  | MMUART0_HI
| 0x2810 001C |  | MMUART1_HI
| 0x2810 201C |  | MMUART2_HI
| 0x2810 401C |  | MMUART3_HI
| 0x2810 601C |  | MMUART4_HI
Description | Scratch register
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | SCR | Scratch register. This register has no effect on MMUART_x operation. | RW | 0x00

### MMUART : Reserved

Address offset | 0x020
Physical address | 0x2000 0020 | Instance | MMUART0_LO
| 0x2010 0020 |  | MMUART1_LO
| 0x2010 2020 |  | MMUART2_LO
| 0x2010 4020 |  | MMUART3_LO
| 0x2010 6020 |  | MMUART4_LO
| 0x2800 0020 |  | MMUART0_HI
| 0x2810 0020 |  | MMUART1_HI
| 0x2810 2020 |  | MMUART2_HI
| 0x2810 4020 |  | MMUART3_HI
| 0x2810 6020 |  | MMUART4_HI
Description | Reserved register
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved1 |  | RO | 0x00 0000
7:0 | Reserved | reads as 00h | RO | 0x00

### MMUART : IEM

Address offset | 0x024
Physical address | 0x2000 0024 | Instance | MMUART0_LO
| 0x2010 0024 |  | MMUART1_LO
| 0x2010 2024 |  | MMUART2_LO
| 0x2010 4024 |  | MMUART3_LO
| 0x2010 6024 |  | MMUART4_LO
| 0x2800 0024 |  | MMUART0_HI
| 0x2810 0024 |  | MMUART1_HI
| 0x2810 2024 |  | MMUART2_HI
| 0x2810 4024 |  | MMUART3_HI
| 0x2810 6024 |  | MMUART4_HI
Description | Multi-mode interrupt enable register
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | Reserved |  | RO Rreturns0s | 0x000 0000
4 | ELINSI | Enables the LIN sync detection interrupt. 0: Disabled (default) 1: Enabled | RW | 0
3 | ELINBI | Enables LIN break interrupt. 0: Disabled (default) 1: Enabled | RW | 0
2 | EPID_PEI | Enables PID parity error interrupt 0: Disabled (default) 1: Enabled | RW | 0
1 | ENACKI | Enables NACK interrupt. 0: Disabled (default) 1: Enabled | RW | 0
0 | ERTOI | Enables receiver timeout interrupt. 0: Disabled (default) 1: Enabled | RW | 0

### MMUART : IIM

Address offset | 0x028
Physical address | 0x2000 0028 | Instance | MMUART0_LO
| 0x2010 0028 |  | MMUART1_LO
| 0x2010 2028 |  | MMUART2_LO
| 0x2010 4028 |  | MMUART3_LO
| 0x2010 6028 |  | MMUART4_LO
| 0x2800 0028 |  | MMUART0_HI
| 0x2810 0028 |  | MMUART1_HI
| 0x2810 2028 |  | MMUART2_HI
| 0x2810 4028 |  | MMUART3_HI
| 0x2810 6028 |  | MMUART4_HI
Description | Multi-mode interrupt identification register
Type | RO

Bits | Field Name | Description | Type | Reset
31:5 | Reserved |  | RO Rreturns0s | 0x000 0000
4 | LINSI | LIN sync detection interrupt ID. This bit set when 5th falling edge is detected by the sync timer. It resets the FIFO address pointers so that the PID will be in the first location. Reading the IIM register clears this interrupt. | RO RtoClr | 0
3 | LINBI | LIN break interrupt.. set automatically when break length of 11.5 Tbits is detected. Reading the IIM register clears this interrupt. | RO RtoClr | 0
2 | PID_PEI | Protected identifier field (PID) parity error interrupt is generated when there is a mismatch in PID in LIN header.. that is.. when either the P0 or P1 bits in the incoming PID byte do not match the calculated P0 and P1 error. | RO | 0
1 | NACKI | NACK interrupt is asserted when EERR bit is set in MM2. Reading the MM2 clears the interrupt. | RO RtoClr | 0
0 | RTOII | Receiver time-out (RTO) interrupt ID. RTO interrupt is asserted when RTO value is reached by the counter. It gets cleared when writing to the RTO register. | RO | 0

### MMUART : Reserved_1

Address offset | 0x02C
Physical address | 0x2000 002C | Instance | MMUART0_LO
| 0x2010 002C |  | MMUART1_LO
| 0x2010 202C |  | MMUART2_LO
| 0x2010 402C |  | MMUART3_LO
| 0x2010 602C |  | MMUART4_LO
| 0x2800 002C |  | MMUART0_HI
| 0x2810 002C |  | MMUART1_HI
| 0x2810 202C |  | MMUART2_HI
| 0x2810 402C |  | MMUART3_HI
| 0x2810 602C |  | MMUART4_HI
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved1 |  | RO | 0x00 0000
7:0 | Reserved | reads as 00h | RO | 0x00

### MMUART : MM0

Address offset | 0x030
Physical address | 0x2000 0030 | Instance | MMUART0_LO
| 0x2010 0030 |  | MMUART1_LO
| 0x2010 2030 |  | MMUART2_LO
| 0x2010 4030 |  | MMUART3_LO
| 0x2010 6030 |  | MMUART4_LO
| 0x2800 0030 |  | MMUART0_HI
| 0x2810 0030 |  | MMUART1_HI
| 0x2810 2030 |  | MMUART2_HI
| 0x2810 4030 |  | MMUART3_HI
| 0x2810 6030 |  | MMUART4_HI
Description | Multi-mode control register0
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7 | EFBR | Enable fractional baud rate (FBR) mode. 0: Disabled (default) 1: Enabled | RW | 0
6 | ERTO | Enable receiver timeout (RTO). Writing this bit enables the timeout and restarts the counter value. The timeout value is determined by the RTO register. 0: Disabled (default) 1: Enabled | RW | 0
5 | ETTG | Enable transmitter time guard (TTG). The time guard value is determined by the TTG Register. 0: Disabled (default) 1: Enabled | RW | 0
4 | Reserved |  | RO Rreturns0s | 0
3 | ELIN | Enable LIN header detection and automatic baud rate calculation. 0: Disabled (default) 1: Enabled | RW | 0
2:0 | ESYN | Enable synchronous operation. There are four types of Synchronous Operation modes that can be enabled. 0b000: Disabled.. that is.. Asynchronous mode (default) 0b001: Synchronous slave enabled.. positive-edge clock 0b010: Synchronous slave enabled.. negative-edge clock 0b011: Synchronous master enabled.. positive-edge clock 0b100: Synchronous master enabled.. negative-edge clock 0b101.. 0b110.. and 0b111: Reserved | RW | 0x0

### MMUART : MM1

Address offset | 0x034
Physical address | 0x2000 0034 | Instance | MMUART0_LO
| 0x2010 0034 |  | MMUART1_LO
| 0x2010 2034 |  | MMUART2_LO
| 0x2010 4034 |  | MMUART3_LO
| 0x2010 6034 |  | MMUART4_LO
| 0x2800 0034 |  | MMUART0_HI
| 0x2810 0034 |  | MMUART1_HI
| 0x2810 2034 |  | MMUART2_HI
| 0x2810 4034 |  | MMUART3_HI
| 0x2810 6034 |  | MMUART4_HI
Description | Multi-mode control register1
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved |  | RO Rreturns0s | 0x000 0000
5 | EITP | Output pulse width for RZI mod can be modified using this bit. 0: 3/16th Tbit pulse width (default). 1: 1/4th Tbit pulse width. | RW | 0
4 | EITX | You can configure output polarity for RZI modulation. 0: RZI output pulses are active Low and signify a low NRZ value (default). 1: RZI output pulses are active High and signify a high NRZ value. | RW | 0
3 | EIRX | You can configure input polarity for RZI demodulation. 0: RZI input pulses are active Low.. signifying a low NRZ value (default). 1: RZI input pulses are active High.. signifying a high NRZ value. | RW | 0
2 | EIRD | Enables RZI modulation/demodulation. 0: Disabled (default) 1: Enabled | RW | 0
1 | E_MSB_TX | LSB or MSB can be sent first by configuring this bit. By default.. the "THR" bit 0 is the LSB.. and is the first transmitted bit. Bit 0 of the THR may be configured as the last transmitted bit.. MSB. 0: THR's bit 0 is the first transmitted bit.(LSB). (default). 1: THR's bit 0 is the last transmitted bit.(MSB). | RW | 0
0 | E_MSB_RX | LSB or MSB can be received first by configuring this bit. By default.. the receiver buffer register's (RBR) bit 0 is the LSB.. and is the first received bit. Bit 0 of the RBR may be configured as the last received bit.. MSB. 0: RBR's bit 0 is the first received bit(LSB). (default). 1: RBR's bit 0 is the last received bit(MSB). | RW | 0

### MMUART : MM2

Address offset | 0x038
Physical address | 0x2000 0038 | Instance | MMUART0_LO
| 0x2010 0038 |  | MMUART1_LO
| 0x2010 2038 |  | MMUART2_LO
| 0x2010 4038 |  | MMUART3_LO
| 0x2010 6038 |  | MMUART4_LO
| 0x2800 0038 |  | MMUART0_HI
| 0x2810 0038 |  | MMUART1_HI
| 0x2810 2038 |  | MMUART2_HI
| 0x2810 4038 |  | MMUART3_HI
| 0x2810 6038 |  | MMUART4_HI
Description | Multi-mode control register2
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | Reserved |  | RO Rreturns0s | 0x000 0000
3 | ESWM | Enable single-wire.. half-duplex mode. 0: Disabled (default) 1: Enabled | RW | 0
2 | EAFC | Enable a address flag clear (EAFC). When EAFM is enabled the Rx FIFO is disabled until another address flag with matching address is received. The bit gets cleared on write in multi-mode control registers 2. 0: Disabled (default) 1: Enabled | RW | 0
1 | EAFM | Enable automatic 9-bit address flag mode (EAFM). It should be noted that for enabling this bit it requires.. the LCR should be in an 8-bit and stick parity (SP) bit configured to 0. If EAFM bit is disabled.. the Rx FIFO is enabled by receiving all the bytes. When EAFM bit is enabled.. the Rx FIFO is disabled until an address flag with matching address is received. Note: If an address match occurs and the Rx FIFO is enabled then it can be disabled.. if either another address flag occurs or there is a mismatch or the EAFC bit is set. In either case.. the Address flag compare will continue as long as the EAFM bit is set. 0: Disabled (default) 1: Enabled | RW | 0
0 | EERR | When the EERR bit is set.. the receiver forces an error signal transmit out.. if an incoming parity error is detected. Error signal (ACK/NACK) is sent during stop time enable. Note: The EERR only applies in an 8-bit data length.. 2 stop bit configuration. Error signal occurs during the last 1.5 stop bits as per Figure 12-18 on page 529. 0: Disabled (default) 1: Enabled | RW | 0

### MMUART : DFR

Address offset | 0x03C
Physical address | 0x2000 003C | Instance | MMUART0_LO
| 0x2010 003C |  | MMUART1_LO
| 0x2010 203C |  | MMUART2_LO
| 0x2010 403C |  | MMUART3_LO
| 0x2010 603C |  | MMUART4_LO
| 0x2800 003C |  | MMUART0_HI
| 0x2810 003C |  | MMUART1_HI
| 0x2810 203C |  | MMUART2_HI
| 0x2810 403C |  | MMUART3_HI
| 0x2810 603C |  | MMUART4_HI
Description | Fractional divisor register
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved |  | RO Rreturns0s | 0x000 0000
5:0 | DFR | The fractional divisor register (DFR) is used to store the fractional divisor used to calculate the fractional baud rate value in 1/64th using EQ 5. 0x0: 0/64 0x1: 1/64 .... 0x3F: 63/64 | RW | 0x00

### MMUART : GFR

Address offset | 0x044
Physical address | 0x2000 0044 | Instance | MMUART0_LO
| 0x2010 0044 |  | MMUART1_LO
| 0x2010 2044 |  | MMUART2_LO
| 0x2010 4044 |  | MMUART3_LO
| 0x2010 6044 |  | MMUART4_LO
| 0x2800 0044 |  | MMUART0_HI
| 0x2810 0044 |  | MMUART1_HI
| 0x2810 2044 |  | MMUART2_HI
| 0x2810 4044 |  | MMUART3_HI
| 0x2810 6044 |  | MMUART4_HI
Description | Glitch filter register
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved |  | RO Rreturns0s | 0x0000 0000
2:0 | GLR | The glitch filter resynchronizes (GLR) and suppresses random input noise from MMUART_x_RXD (serial input data) and MMUART_x_SCK_IN (serial input clock in synchronous mode) based on the filter length given in number system clock cycles. The following are the different filter lengths in the APB clock cycles that can be written into the GLR register and their description. 0b000: Two resynchronize flip-flops are used but there is no spike suppression. 0b001: Three resynchronize flip-flops are used but there is no spike suppression. 0b010: Three resynchronize flip-flops are used and it also causes 1 APB clock cycle suppression. 0b011: Three resynchronize flip-flops are used and it also causes 2 APB clock cycle suppression. 0b100: Three resynchronize flip-flops are used and it also causes 3 APB clock cycle suppression. 0b101: Three resynchronize flip-flops are used and it also causes 4 APB clock cycle suppression. 0b110: Three resynchronize flip-flops are used and it also causes 5 APB clock cycle suppression. 0b111: Three resynchronize flip-flops are used and it also causes 6 APB clock cycle suppression. | RW | 0x0

### MMUART : TTG

Address offset | 0x048
Physical address | 0x2000 0048 | Instance | MMUART0_LO
| 0x2010 0048 |  | MMUART1_LO
| 0x2010 2048 |  | MMUART2_LO
| 0x2010 4048 |  | MMUART3_LO
| 0x2010 6048 |  | MMUART4_LO
| 0x2800 0048 |  | MMUART0_HI
| 0x2810 0048 |  | MMUART1_HI
| 0x2810 2048 |  | MMUART2_HI
| 0x2810 4048 |  | MMUART3_HI
| 0x2810 6048 |  | MMUART4_HI
Description | Transmitter time guard register
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | TTG | If the transmitter time guard is enabled from the multi-mode control register 0 (MM0).. the transmitter time guard value determines the amount of system clock cycles to wait between transmissions. The time guard equation is based on the baud rate bit time (Tbit) value as follows: Tx Time Guard Value = TTG x Bit Time (Tbit) | RW | 0x00

### MMUART : RTO

Address offset | 0x04C
Physical address | 0x2000 004C | Instance | MMUART0_LO
| 0x2010 004C |  | MMUART1_LO
| 0x2010 204C |  | MMUART2_LO
| 0x2010 404C |  | MMUART3_LO
| 0x2010 604C |  | MMUART4_LO
| 0x2800 004C |  | MMUART0_HI
| 0x2810 004C |  | MMUART1_HI
| 0x2810 204C |  | MMUART2_HI
| 0x2810 404C |  | MMUART3_HI
| 0x2810 604C |  | MMUART4_HI
Description | Receiver time-out register
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | RTO | Writing to the RTO register sets the counter value and enables.. if the ERTO bit in the MM0 is enabled. You can configure the timeout value by writing into this register. The RTO counts when the Rx block input state is idle; is reset when a start condition occurs.. and restarts counting upon returning to the idle state. When the RTO value is reached.. the RTOII interrupt is set. Re-writing the RTO register clears the interrupt and sets the counter. The receiver timeout value equation is based on the baud rate bit time (Tbit) as follows: Rx Timeout Value = 4 x RTO x Bit Time (Tbit) | RW | 0x00

### MMUART : ADR

Address offset | 0x050
Physical address | 0x2000 0050 | Instance | MMUART0_LO
| 0x2010 0050 |  | MMUART1_LO
| 0x2010 2050 |  | MMUART2_LO
| 0x2010 4050 |  | MMUART3_LO
| 0x2010 6050 |  | MMUART4_LO
| 0x2800 0050 |  | MMUART0_HI
| 0x2810 0050 |  | MMUART1_HI
| 0x2810 2050 |  | MMUART2_HI
| 0x2810 4050 |  | MMUART3_HI
| 0x2810 6050 |  | MMUART4_HI
Description | Address register
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | ADR | The address register is used in 9-bit Address Flag mode. When an address flag is received on the 9th bit.. and EAFM is set in MM2.. the incoming data is checked against the address register. If a match occurs.. the Rx FIFO is enabled. | RW | 0x00

### MMUART : DLR

Address offset | 0x080
Physical address | 0x2000 0080 | Instance | MMUART0_LO
| 0x2010 0080 |  | MMUART1_LO
| 0x2010 2080 |  | MMUART2_LO
| 0x2010 4080 |  | MMUART3_LO
| 0x2010 6080 |  | MMUART4_LO
| 0x2800 0080 |  | MMUART0_HI
| 0x2810 0080 |  | MMUART1_HI
| 0x2810 2080 |  | MMUART2_HI
| 0x2810 4080 |  | MMUART3_HI
| 0x2810 6080 |  | MMUART4_HI
Description | Divisor latch (LSB)
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | DLR | This divisor latch LSB register (DLR) holds the LSB of the integer divisor value used to calculate the baud rate. The baud rate can be calculated using EQ 1.. 2.. 3.. or 4. ** To access this Register DAP (bit7) of Line Control Register (LCR) should be set. | RW | 0x01

### MMUART : DMR

Address offset | 0x084
Physical address | 0x2000 0084 | Instance | MMUART0_LO
| 0x2010 0084 |  | MMUART1_LO
| 0x2010 2084 |  | MMUART2_LO
| 0x2010 4084 |  | MMUART3_LO
| 0x2010 6084 |  | MMUART4_LO
| 0x2800 0084 |  | MMUART0_HI
| 0x2810 0084 |  | MMUART1_HI
| 0x2810 2084 |  | MMUART2_HI
| 0x2810 4084 |  | MMUART3_HI
| 0x2810 6084 |  | MMUART4_HI
Description | Divisor latch (MSB)
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | DMR | This divisor latch MSB register (DMR) holds the MSB of the integer divisor value used to calculate the baud rate. The baud rate can be calculated using EQ 1.. 2.. 3.. or 4. ** To access this Register DAP (bit7) of Line Control Register (LCR) should be set. | RW | 0x00

### MMUART : THR

Address offset | 0x100
Physical address | 0x2000 0100 | Instance | MMUART0_LO
| 0x2010 0100 |  | MMUART1_LO
| 0x2010 2100 |  | MMUART2_LO
| 0x2010 4100 |  | MMUART3_LO
| 0x2010 6100 |  | MMUART4_LO
| 0x2800 0100 |  | MMUART0_HI
| 0x2810 0100 |  | MMUART1_HI
| 0x2810 2100 |  | MMUART2_HI
| 0x2810 4100 |  | MMUART3_HI
| 0x2810 6100 |  | MMUART4_HI
Description | Transmit holding register
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | THR | This register holds the data bits to be transmitted. Bit 0 is the LSB and is transmitted first. The MSB may be transmitted first.. if it is configured with the E_MSB_TX bit in the MM1. The reset value is unknown since the register is loaded with data in the transmit FIFO. The DLAB.. bit 7 of LCR.. must be 0 to write to this register. This register is write only. Reading from this register with the DLAB 0 reads the RBR register value. | WO | 0x00

### MMUART : FCR

Address offset | 0x108
Physical address | 0x2000 0108 | Instance | MMUART0_LO
| 0x2010 0108 |  | MMUART1_LO
| 0x2010 2108 |  | MMUART2_LO
| 0x2010 4108 |  | MMUART3_LO
| 0x2010 6108 |  | MMUART4_LO
| 0x2800 0108 |  | MMUART0_HI
| 0x2810 0108 |  | MMUART1_HI
| 0x2810 2108 |  | MMUART2_HI
| 0x2810 4108 |  | MMUART3_HI
| 0x2810 6108 |  | MMUART4_HI
Description | FIFO control register
Type | WO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | WO | 0x00 0000
7:6 | RX_TRIG | These bits are used to set the trigger level for the Rx FIFO interrupt. Rx FIFO trigger level (bytes) are: 0b00: 1 byte 0b01: 4 bytes 0b10: 8 bytes 0b11: 14 bytes | WO | 0x3
5:4 | Reserved |  | WO | 0x0
3 | ENABLE_TXRDY_RXRDY | Switches between RXRDY and TXRDY mode 0 and mode 1 functionality. 0-Mode 0. 1-Mode 1 | WO | 0
2 | CLEAR_TX_FIFO | Clears all bytes in the Tx FIFO and resets its counter logic. The shift register is not cleared. 0: Disabled (default) 1: Enabled | WO | 0
1 | CLEAR_RX_FIFO | Clears all bytes in Rx FIFO and resets counter logic. This shift register is not cleared. 0: Disabled (default) 1: Enabled | WO | 0
0 | ENABLE_TX_RX_FIFO | It enables both the Tx and Rx FIFOs and is hardwired to 1.. which means it is always enabled and cannot be changed. | WO | 1

MMUART has no common memories.