## IOSCB_CFM_SGMII

This section provides information on the IOSCB_CFM_SGMII Module Instance. Each of the module registers is described below.

Return to mpfs_ioscb_memmap_dri

## IOSCB_CFM_SGMII Register Mapping Summary

### cfm_eth Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x00 | 0x0E20 0000
RFCKMUX | RW | 32 | 0x0000 0000 | 0x04 | 0x0E20 0004
SGMII_CLKMUX | RW | 32 | 0x0000 0000 | 0x08 | 0x0E20 0008
SPARE0 | RW | 32 | 0x0000 0000 | 0x0C | 0x0E20 000C
CLK_XCVR | RW | 32 | 0x0000 0000 | 0x10 | 0x0E20 0010
TEST_CTRL | RW | 32 | 0x0000 0000 | 0x14 | 0x0E20 0014

## IOSCB_CFM_SGMII Register Descriptions

### IOSCB_CFM_SGMII : SOFT_RESET

Address offset | 0x00
Physical address | 0x0E20 0000 | Instance | cfm_eth
Description | This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | BLOCKID | This returns the block type and chip location. (IO SCB bus only) | RO | 0x0000
|  | Read 0x0000 | [block_address_IOSCB_CFM_SGMII] |  |
15:9 | Reserved |  | RO Rreturns0s | 0x00
8 | PERIPH | This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0. | WO | 0
|  | Write 0 | [scb_periph_not_in_soft_reset_IOSCB_CFM_SGMII] |  |
|  | Write 1 | [scb_periph_reset_IOSCB_CFM_SGMII] |  |
7:2 | Reserved |  | RO Rreturns0s | 0x00
1 | V_MAP | This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit | WO | 0
|  | Write 0 | [scb_v_regs_not_in_soft_reset_IOSCB_CFM_SGMII] |  |
|  | Write 1 | [scb_v_regs_reset_IOSCB_CFM_SGMII] |  |
0 | NV_MAP | This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit | WO | 0
|  | Write 0 | [scb_nv_regs_not_in_soft_reset_IOSCB_CFM_SGMII] |  |
|  | Write 1 | [scb_nv_regs_reset_IOSCB_CFM_SGMII] |  |

### IOSCB_CFM_SGMII : RFCKMUX

Address offset | 0x04
Physical address | 0x0E20 0004 | Instance | cfm_eth
Description | PLL RF clk mux selections
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | Reserved |  | RO | 0x000 0000
3:2 | pll0_rfclk1_sel |  | RW | 0x0
1:0 | pll0_rfclk0_sel |  | RW | 0x0

### IOSCB_CFM_SGMII : SGMII_CLKMUX

Address offset | 0x08
Physical address | 0x0E20 0008 | Instance | cfm_eth
Description | MSS Clock mux selections
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SGMII_CLKMUX |  | RW | 0x0000 0000

### IOSCB_CFM_SGMII : SPARE0

Address offset | 0x0C
Physical address | 0x0E20 000C | Instance | cfm_eth
Description | spare logic
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | spare0 |  | RW | 0x0000 0000

### IOSCB_CFM_SGMII : CLK_XCVR

Address offset | 0x10
Physical address | 0x0E20 0010 | Instance | cfm_eth
Description | Clock Receiver
Type | RW

Bits | Field Name | Description | Type | Reset
31:14 | reserve3 |  | RO | 0x0 0000
13 | en_rdiff |  | RW | 0
12 | clkbuf_en_pullup |  | RW | 0
11:10 | en_rxmode_n |  | RW | 0x0
9:8 | en_term_n |  | RW | 0x0
7 | en_ins_hyst_n |  | RW | 0
6 | en_udrive_n |  | RW | 0
5:4 | en_rxmode_p |  | RW | 0x0
3:2 | en_term_p |  | RW | 0x0
1 | en_ins_hyst_p |  | RW | 0
0 | en_udrive_p |  | RW | 0

### IOSCB_CFM_SGMII : TEST_CTRL

Address offset | 0x14
Physical address | 0x0E20 0014 | Instance | cfm_eth
Description | Test MUX Controls
Type | RW

Bits | Field Name | Description | Type | Reset
31:18 | Reserved |  | RO Rreturns0s | 0x0000
17:13 | dtest1_sel |  | RW | 0x00
12 | dtest1_en |  | RW | 0
11:7 | dtest0_sel |  | RW | 0x00
6 | dtest0_en |  | RW | 0
5:0 | reserve4 |  | RO | 0x00

IOSCB_CFM_SGMII has no common memories.