## IOSCBCFG

This section provides information on the IOSCBCFG Module Instance. Each of the module registers is described below.

Return to pfsoc_mss_regmap

## IOSCBCFG Register Mapping Summary

### IOSCBCFG Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CONTROL__1 | RW | 32 | 0x0000 0000 | 0x000 | 0x3708 0000
STATUS | RO | 32 | 0x0000 0000 | 0x004 | 0x3708 0004
TIMER | RW | 32 | 0x0000 2080 | 0x008 | 0x3708 0008

## IOSCBCFG Register Descriptions

### IOSCBCFG : CONTROL__1

Address offset | 0x000
Physical address | 0x3708 0000 | Instance | IOSCBCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | Reserved |  | RO Rreturns0s | 0x0000
16 | SCBCLOCK_ON | Setting this requests PFC to turn on the SCB clock permanently | RW | 0
15:9 | Reserved |  | RO Rreturns0s | 0x00
8 | RESET_CYCLE | Writing a '1' to the bit will cause a reset off the internal FSMS. Once set it will stay asserted until the reset cycle completes when it will be cleared. This may take several clock cycles depending on relative speeds of the SCB and AHB clocks. | RW | 0
7:4 | Reserved |  | RO Rreturns0s | 0x0
3 | INTEN_BUSERR | Enables interrupt when SCB bus error detected | RW | 0
2 | INTEN_TIMEOUT | Enables interrupt when timeout occurs | RW | 0
1 | INTEN_ERROR | Enables interrupt when SCB error asserted | RW | 0
0 | INTEN_SCB | Enables interrupt when SCB Interrupt asserted | RW | 0

### IOSCBCFG : STATUS

Address offset | 0x004
Physical address | 0x3708 0004 | Instance | IOSCBCFG
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
31:4 | Reserved |  | RO Rreturns0s | 0x000 0000
3 | SCB_BUSERR | Indicated that an SCB bus error (parity) was detected. Is cleared by initiating FSM reset cycle (Control register bit 16) | RO | 0
2 | TIMEOUT | Indicated that the SCB access timed out. Is cleared by initiating FSM reset cycle (Control register bit 16) | RO | 0
1 | SCB_ERROR | Indicates that the SCB error was asserted. Is cleared by initiating FSM reset cycle (Control register bit 16) | RO | 0
0 | SCB_INTERRUPT | Indicated SCB interrupt active. Is cleared by clearing the SCB interrupt source | RO | 0

### IOSCBCFG : TIMER

Address offset | 0x008
Physical address | 0x3708 0008 | Instance | IOSCBCFG
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved |  | RO Rreturns0s | 0x0000
15:8 | REQUEST_TIME | Sets how long SCB request is held active after SCB bus granted. Allows SCB bus mastership to maintained across multiple SCB access cycles | RW | 0x20
7:0 | TIMEOUT | Set the timeout for an SCB access in CPU cycles. | RW | 0x80

IOSCBCFG has no common memories.