## CRYPTO

This section provides information on the CRYPTO Module Instance. Each of the module registers is described below.

Return to pfsoc_mss_regmap

## CRYPTO Register Mapping Summary

### CRYPTO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CONFIG | RW | 32 | 0x0000 0001 | 0x0000 | 0x2012 7000
STALL | RW | 32 | 0x0000 0000 | 0x0004 | 0x2012 7004
UPPER_ADDRESS | RW | 32 | 0x0000 0000 | 0x0008 | 0x2012 7008

## CRYPTO Register Descriptions

### CRYPTO : CONFIG

Address offset | 0x0000
Physical address | 0x2012 7000 | Instance | CRYPTO
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | Reserved |  | RO Rreturns0s | 0x0
29 | fab_owner | Fabric controls the crypto block | RO | 0
28 | mss_owner | MSS controls the crypto block | RO | 0
27 | fab_release | Fabric has released the crypto, see the MSS/Fabric Crypto block ownership section in the MAS specification | RO | 0
26 | fab_request | Fabric is requesting crypto use, see the MSS/Fabric Crypto block ownership section in the MAS specification | RW | 0
25 | mss_release | MSS releases crypto, see the MSS/Fabric Crypto block ownership section in the MAS specification | RO | 0
24 | mss_request | MSS requests crypto use, see the MSS/Fabric Crypto block ownership section in the MAS specification | RW | 0
23:17 | Reserved |  | RO Rreturns0s | 0x00
16 | use_fab_clk | When '1' in MSS mode the Crypto core and AHB interconnect is clocked by the Fabric clock rather than by the MSS sourced 200MHz clock source. This allows the MSS to use the AHB interfaces and the Fabric the streaming interface. | RW | 0
15:13 | Reserved_1 |  | RW | 0x0
12 | Reserved | Indicates that the Athena core is busy. | RO Rreturns0s | 0
11 | stream_enabled | Indicates that the streaming interface ie enabled | RO | 0
10 | buserror | Status signal from Athena core indicating it received a AHB bus error response | RO | 0
9 | alarm | Status signal from Athena core indicating alarm condition | RO | 0
8 | complete | Status signal from Athena core indicating complete | RO | 0
7:6 | stall_rate | Sets the average stall rate. 00: 1 in 8 01: 1 in 16 10: 1 in 32 11: 1 in 64 | RW W1toClr | 0x0
5 | stall_enable | Enables the stall system on the Crypto core 0: Operates in G5 mode using fabric stall signal, clock_select must be 01 1: Internal mode enabled, stall occurrence generated internally on average 1 in 8 clocks. Works with clock_select 01 or 11. | RW | 0
4 | stream_enable | Enables the streaming interface to the fabric, must also be enabled via SCB device register | RW | 0
3 | RING_OSC_ON | Turns on the Athena ring oscillators, note turned off at reset | RW | 0
2 | GO | Asserts the Athena go input | RW | 0
1 | PURGE | Asserts the Athena purge command input | RW | 0
0 | RESET | Asserts the internal Athena core reset signal | RW | 1

### CRYPTO : STALL

Address offset | 0x0004
Physical address | 0x2012 7004 | Instance | CRYPTO
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | seed | Sets the seed value used in the generation off the Athena Stall logic | RW | 0x0000 0000

### CRYPTO : UPPER_ADDRESS

Address offset | 0x0008
Physical address | 0x2012 7008 | Instance | CRYPTO
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved |  | RO Rreturns0s | 0x000 0000
5:0 | address | Sets the upper 6-bits of the 38 bit Master address provided to the MSS. | RW | 0x00

CRYPTO has no common memories.