## I2C

This section provides information on the I2C Module Instance. Each of the module registers is described below.

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## I2C Register Mapping Summary

### I2C Common Register Mapping Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset
I2C0_CTRL | RW | 32 | 0x0000 0000 | 0x000
I2C0_STATUS | RO | 32 | 0x0000 00F8 | 0x004
I2C0_DATA | RW | 32 | 0x0000 0000 | 0x008
I2C0_SLAVE0ADR | RW | 32 | 0x0000 0000 | 0x00C
I2C0_SMBUS | RW | 32 | 0x0000 0050 | 0x010
I2C0_FREQ | RW | 32 | 0x0000 0008 | 0x014
I2C0_GLITCHREG | RW | 32 | 0x0000 0003 | 0x018
I2C0_SLAVE1ADR | RW | 32 | 0x0000 0000 | 0x01C

## I2C Instances Mapping Summary

### I2C : I2C_A_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
I2C0_CTRL | RW | 32 | 0x0000 0000 | 0x000 | 0x2010 A000
I2C0_STATUS | RO | 32 | 0x0000 00F8 | 0x004 | 0x2010 A004
I2C0_DATA | RW | 32 | 0x0000 0000 | 0x008 | 0x2010 A008
I2C0_SLAVE0ADR | RW | 32 | 0x0000 0000 | 0x00C | 0x2010 A00C
I2C0_SMBUS | RW | 32 | 0x0000 0050 | 0x010 | 0x2010 A010
I2C0_FREQ | RW | 32 | 0x0000 0008 | 0x014 | 0x2010 A014
I2C0_GLITCHREG | RW | 32 | 0x0000 0003 | 0x018 | 0x2010 A018
I2C0_SLAVE1ADR | RW | 32 | 0x0000 0000 | 0x01C | 0x2010 A01C

### I2C : I2C_B_LO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
I2C0_CTRL | RW | 32 | 0x0000 0000 | 0x000 | 0x2010 B000
I2C0_STATUS | RO | 32 | 0x0000 00F8 | 0x004 | 0x2010 B004
I2C0_DATA | RW | 32 | 0x0000 0000 | 0x008 | 0x2010 B008
I2C0_SLAVE0ADR | RW | 32 | 0x0000 0000 | 0x00C | 0x2010 B00C
I2C0_SMBUS | RW | 32 | 0x0000 0050 | 0x010 | 0x2010 B010
I2C0_FREQ | RW | 32 | 0x0000 0008 | 0x014 | 0x2010 B014
I2C0_GLITCHREG | RW | 32 | 0x0000 0003 | 0x018 | 0x2010 B018
I2C0_SLAVE1ADR | RW | 32 | 0x0000 0000 | 0x01C | 0x2010 B01C

### I2C : I2C_A_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
I2C0_CTRL | RW | 32 | 0x0000 0000 | 0x000 | 0x2810 A000
I2C0_STATUS | RO | 32 | 0x0000 00F8 | 0x004 | 0x2810 A004
I2C0_DATA | RW | 32 | 0x0000 0000 | 0x008 | 0x2810 A008
I2C0_SLAVE0ADR | RW | 32 | 0x0000 0000 | 0x00C | 0x2810 A00C
I2C0_SMBUS | RW | 32 | 0x0000 0050 | 0x010 | 0x2810 A010
I2C0_FREQ | RW | 32 | 0x0000 0008 | 0x014 | 0x2810 A014
I2C0_GLITCHREG | RW | 32 | 0x0000 0003 | 0x018 | 0x2810 A018
I2C0_SLAVE1ADR | RW | 32 | 0x0000 0000 | 0x01C | 0x2810 A01C

### I2C : I2C_B_HI Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
I2C0_CTRL | RW | 32 | 0x0000 0000 | 0x000 | 0x2810 B000
I2C0_STATUS | RO | 32 | 0x0000 00F8 | 0x004 | 0x2810 B004
I2C0_DATA | RW | 32 | 0x0000 0000 | 0x008 | 0x2810 B008
I2C0_SLAVE0ADR | RW | 32 | 0x0000 0000 | 0x00C | 0x2810 B00C
I2C0_SMBUS | RW | 32 | 0x0000 0050 | 0x010 | 0x2810 B010
I2C0_FREQ | RW | 32 | 0x0000 0008 | 0x014 | 0x2810 B014
I2C0_GLITCHREG | RW | 32 | 0x0000 0003 | 0x018 | 0x2810 B018
I2C0_SLAVE1ADR | RW | 32 | 0x0000 0000 | 0x01C | 0x2810 B01C

## I2C Register Descriptions

### I2C : I2C0_CTRL

Address offset | 0x000
Physical address | 0x2010 A000 | Instance | I2C_A_LO
| 0x2010 B000 |  | I2C_B_LO
| 0x2810 A000 |  | I2C_A_HI
| 0x2810 B000 |  | I2C_B_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7 | CR2 | Clock rate bit 2; refer to bit 0. | RW | 0
6 | ENS1 | Enable bit. When ens1='0', the sda and scl outputs are in a high impedance and sda and scl input signals are ignored. When ens1='1', the Core is enabled | RW | 0
5 | STA | The START Flag. When sta='1', the Core checks the status of the serial bus and generates a START condition if the bus is free. | RW | 0
4 | STO | The STOP Flag. When sto='1' and the Core is in a master mode, a STOP condition is transmitted to the serial bus. | RW | 0
3 | SI | The Serial Interrupt Flag. The SI flag is set by the Core whenever there is a service-able change in the Status Register. After the register has been updated, the "si" bit must be cleared by software. NOTE: The si bit is directly readable via the APB INTERRUPT signal. | RW | 0
2 | AA | The Assert Acknowledge Flag. When aa='1' an acknowledge will be returned when: The "own slave address" has been received. The general call address has been received while the gc bit in the Address register is set . A data byte has been received while the Core is in the master receiver mode . A data byte has been received while the Core is in the slave receiver mode. When aa='0', a not acknowledge will be returned when: A data byte has been received while the Core is in the master receiver mode .A data byte has been received while F2DSS_I2C is in the slave receiver mode | RW | 0
1 | CR1 | Serial Clock rate bit 1; refer to bit 0. | RW | 0
0 | CR0 | Serial Clock rate bit 0 ; Clock Rate is defined as follows: 000: PCLK frequency/256, 001: PCLK frequency/224, 010:PCLK frequency/192, 011: PCLK frequency/160, 100: PCLK frequency/960, 101: PCLK frequency/120, 110: PCLK frequency/60, 111:BCLK frequency/8. Note: BCLK is synchronized to PCLK and hence must be PCLKFREQ/2 or less. | RW | 0

### I2C : I2C0_STATUS

Address offset | 0x004
Physical address | 0x2010 A004 | Instance | I2C_A_LO
| 0x2010 B004 |  | I2C_B_LO
| 0x2810 A004 |  | I2C_A_HI
| 0x2810 B004 |  | I2C_B_HI
Description | 1. Master Transmitter Mode, 2. Master Receiver Mode, 3. Slave Transmitter Mode, 4. Slave Receiver Mode.
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | Status_Register | Read-only value yields the current state of the I2C Status Registers dependent on Mode. Master Transmitter Mode: 08H: A START condition has been transmitted. 10H: A repeated START condition has been transmitted 18H: SLA+W has been transmitted; ACK has been received 20H: SLA+W has been transmitted; not ACK has been received. 28H: Data byte in Data Register has been transmitted; ACK has been received. 30H: Data byte in Data Register has been transmitted; NACK has been received. 38H: Arbitration lost in SLA+R/W or data bytes. D0H: SMBus Master Reset has been activated. Master Receiver Mode: 08H: A START condition has been transmitted 10H: A repeated START condition has been transmitted 38H: Arbitration lost in not ACK bit 40H: SLA+R has been transmitted; ACK has been received 48H: SLA+R has been transmitted; not ACK has been received 50H: Data byte has been received; ACK has been returned 58H: Data byte has been received; not ACK has been returned D0H: SMBus Master Reset has been activated Slave Receiver Mode: 60H: Own SLA+W has been received; ACK has been returned 68H: Arbitration lost in SLA+R/W as master; own SLA+W has been received, ACK returned 70H: General call address (00H) has been received; ACK has been returned 78H: Arbitration lost in SLA+R/W as master; general call address has been received, ACK returned 80H: Previously addressed with own SLV address; DATA has been received; ACK returned 88H: Previously addressed with own SLA; DATA byte has been received; not ACK returned 90H: Previously addressed with general call address; DATA has been received; ACK returned 98H: Previously addressed with general call address; DATA has been received; NACK returned A0H: A STOP condition or repeated START condition has been received while still addressed as SLV/REC or SLV/TRX D8H: 25 ms SCL low time has been reached; device must be reset Slave Transmitter Mode: A8H: Own SLA+R has been received; ACK has been returned B0H: Arbitration lost in SLA+R/W as master; own SLA+R has been received; ACK has been returned B8H: Data byte has been transmitted; ACK has been received C0H: Data byte has been transmitted; not ACK has been received C8H: Last data byte has transmitted; ACK has received D8H: 25 ms SCL low time has been reached; device must be reset Miscellaneous States: 38H: Arbitration lost F8H: No relevant state information available; si=0 00H: Bus error during MST or selected slave modes | RO | 0xF8

Notes:

1. SLA = slave address

2. SLV = slave

3. REC = receiver

4. TRX = transmitter

5. SLA+W = Master Sends Slave Address then Writes Data to Slave

6. SLA+R = Master Sends Slave Address then Reads Data from Slave

### I2C : I2C0_DATA

Address offset | 0x008
Physical address | 0x2010 A008 | Instance | I2C_A_LO
| 0x2010 B008 |  | I2C_B_LO
| 0x2810 A008 |  | I2C_A_HI
| 0x2810 B008 |  | I2C_B_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7 | sd7 | Serial data bit 7 (MSB), Serial address bit 6 (MSB) | RW | 0
6 | sd6 | Serial data bit 6, Serial address bit 5 | RW | 0
5 | sd5 | Serial data bit 5, Serial address bit 4 | RW | 0
4 | sd4 | Serial data bit 4, Serial address bit 3. | RW | 0
3 | sd3 | Serial data bit 3, Serial address bit 2 | RW | 0
2 | sd2 | Serial data bit 2, Serial address bit 1. | RW | 0
1 | sd1 | Serial data bit 1, Serial address bit 0 (LSB) | RW | 0
0 | sd0 | Serial data bit 0 (LSB). Direction Bit: '0' = Write; '1' = Read | RW | 0

### I2C : I2C0_SLAVE0ADR

Address offset | 0x00C
Physical address | 0x2010 A00C | Instance | I2C_A_LO
| 0x2010 B00C |  | I2C_B_LO
| 0x2810 A00C |  | I2C_A_HI
| 0x2810 B00C |  | I2C_B_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7 | adr6 | Own slave0 address bit 6 | RW | 0
6 | adr5 | Own slave0 address bit 5 | RW | 0
5 | adr4 | Own slave0 address bit 4 | RW | 0
4 | adr3 | Own slave0 address bit 3 | RW | 0
3 | adr2 | Own slave0 address bit 2 | RW | 0
2 | adr1 | Own slave0 address bit 1 | RW | 0
1 | adr0 | Own slave0 address bit 0 | RW | 0
0 | gc | General Call Address Acknowledge. If the gc bit is set, the general call address is recognized; otherwise it is ignored. | RW | 0

### I2C : I2C0_SMBUS

Address offset | 0x010
Physical address | 0x2010 A010 | Instance | I2C_A_LO
| 0x2010 B010 |  | I2C_B_LO
| 0x2810 A010 |  | I2C_A_HI
| 0x2810 B010 |  | I2C_B_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7 | SMBus_Reset | Writing a one to this bit will force the clock line low until 35 ms has been exceeded, thus resetting the entire bus as per the SMBus Specification Version 2.0 | RW | 0
6 | SMBSUS_NO_Control | SMBSUS_NO control; used in master/host mode to force other devices into power down / suspend mode. Active low. | RW | 1
5 | SMBSUS_NI_Status | Status of SMBSUS_NI signal. | RO | 0
4 | SMBALERT_NO_Control | SMBALERT_NO control; used in slave/device mode to force communication with the master/host. Wired-AND. | RW | 1
3 | SMBALERT_NI_Status | Status of SMBALERT_NI signal. Wired-AND. | RO | 0
2 | SMBus_Enable | 0: SMBus timeouts and status logic disabled, i.e., standard I2C bus operation; 1: SMBus timeouts and status logic enabled | RW | 0
1 | SMBSUS_Interrupt_Enable | 0: SMBSUS Interrupt signal (SMBS) disabled. 1: SMBSUS Interrupt signal (SMBS) enabled. | RW | 0
0 | SMBALERT_Interrupt_Enable | 0: SMBALERT Interrupt signal (SMBA) disabled. 1: SMBALERT Interrupt signal (SMBA) enabled. | RW | 0

### I2C : I2C0_FREQ

Address offset | 0x014
Physical address | 0x2010 A014 | Instance | I2C_A_LO
| 0x2010 B014 |  | I2C_B_LO
| 0x2810 A014 |  | I2C_A_HI
| 0x2810 B014 |  | I2C_B_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7:0 | Frequency | PCLK Frequency in Mhz, from 1 to 255. Necessary for configuring Real-time Timeout Logic. Can be set to the PCLK Frequency for 25 ms SMBus timeouts, or may be changed to increase/decrease the timeout value. | RW | 0x08

### I2C : I2C0_GLITCHREG

Address offset | 0x018
Physical address | 0x2010 A018 | Instance | I2C_A_LO
| 0x2010 B018 |  | I2C_B_LO
| 0x2810 A018 |  | I2C_A_HI
| 0x2810 B018 |  | I2C_B_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RW | 0x00 0000
7:0 | GlitchReg_Num | This read/write register is used to adjust the input glitch filter length. Depending on the application, the glitch filter may be used to suppress spikes between 3 and 21 PCLK cycles. If GlitchReg_Fixed=0, then this register can be set from a length of 3 to 21 | RW | 0x03

### I2C : I2C0_SLAVE1ADR

Address offset | 0x01C
Physical address | 0x2010 A01C | Instance | I2C_A_LO
| 0x2010 B01C |  | I2C_B_LO
| 0x2810 A01C |  | I2C_A_HI
| 0x2810 B01C |  | I2C_B_HI
Description |
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO Rreturns0s | 0x00 0000
7 | adr6 | Own slave1 address bit 6 | RW | 0
6 | adr5 | Own slave1 address bit 5 | RW | 0
5 | adr4 | Own slave1 address bit 4 | RW | 0
4 | adr3 | Own slave1 address bit 3 | RW | 0
3 | adr2 | Own slave1 address bit 2 | RW | 0
2 | adr1 | Own slave1 address bit 1 | RW | 0
1 | adr0 | Own slave1 address bit 0 | RW | 0
0 | enadr | 1: Enable the SLAVE1 Address comparisons. 0: Disable SLAVE1 Address comparisons. | RW | 0

I2C has no common memories.