## IOSCB_IO_CALIB_DDR

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This section provides information on the IOSCB_IO_CALIB_DDR Module Instance. Each of the module registers is described below.

Return to mpfs_ioscb_memmap_dri

## IOSCB_IO_CALIB_DDR Register Mapping Summary

### pvt_ddr Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x00 | 0x0E04 0000
IOC_REG0 | RW | 32 | 0x0000 0000 | 0x04 | 0x0E04 0004
IOC_REG1 | RO | 32 | 0x0000 0000 | 0x08 | 0x0E04 0008
IOC_REG2 | RO | 32 | 0x0000 0000 | 0x0C | 0x0E04 000C
IOC_REG3 | RW | 32 | 0x0000 0000 | 0x10 | 0x0E04 0010
IOC_REG4 | RW | 32 | 0x0000 0000 | 0x14 | 0x0E04 0014
IOC_REG5 | RO | 32 | 0x0000 0000 | 0x18 | 0x0E04 0018
IOC_REG6 | RW | 32 | 0x0000 0000 | 0x1C | 0x0E04 001C

## IOSCB_IO_CALIB_DDR Register Descriptions

### IOSCB_IO_CALIB_DDR : SOFT_RESET

Address offset | 0x00
Physical address | 0x0E04 0000 | Instance | pvt_ddr
Description | This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | BLOCKID | This returns the block type and chip location. (IO SCB bus only) | RO | 0x0000
|  | Read 0x0000 | [block_address_IOSCB_IO_CALIB_DDR] |  |
15:9 | Reserved |  | RO Rreturns0s | 0x00
8 | PERIPH | This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0. | WO | 0
|  | Write 0 | [scb_periph_not_in_soft_reset_IOSCB_IO_CALIB_DDR] |  |
|  | Write 1 | [scb_periph_reset_IOSCB_IO_CALIB_DDR] |  |
7:2 | Reserved |  | RO Rreturns0s | 0x00
1 | V_MAP | This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit | WO | 0
|  | Write 0 | [scb_v_regs_not_in_soft_reset_IOSCB_IO_CALIB_DDR] |  |
|  | Write 1 | [scb_v_regs_reset_IOSCB_IO_CALIB_DDR] |  |
0 | NV_MAP | This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit | WO | 0
|  | Write 0 | [scb_nv_regs_not_in_soft_reset_IOSCB_IO_CALIB_DDR] |  |
|  | Write 1 | [scb_nv_regs_reset_IOSCB_IO_CALIB_DDR] |  |

### IOSCB_IO_CALIB_DDR : IOC_REG0

Address offset | 0x04
Physical address | 0x0E04 0004 | Instance | pvt_ddr
Description | IO calib control register0
Type | RW

Bits | Field Name | Description | Type | Reset
31:19 | Reserved |  | RO | 0x0000
18 | reg_calib_move_ncode |  | RW | 0
17 | reg_calib_move_pcode |  | RW | 0
16 | reg_calib_direction |  | RW | 0
15 | reg_calib_load |  | RW | 0
14 | reg_calib_lock |  | RW | 0
13 | reg_calib_start |  | RW | 0
12 | reg_calib_trim |  | RW | 0
11:6 | reg_ncode |  | RW | 0x00
5:0 | reg_pcode |  | RW | 0x00

### IOSCB_IO_CALIB_DDR : IOC_REG1

Address offset | 0x08
Physical address | 0x0E04 0008 | Instance | pvt_ddr
Description | IO calib control register1
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved |  | RO | 0x00 0000
7 | sro_comp_en |  | RO | 0
6 | sro_comp_sel |  | RO | 0
5 | sro_power_on |  | RO | 0
4 | sro_ioen_out |  | RO | 0
3 | sro_calib_intrpt |  | RO | 0
2 | sro_calib_status |  | RO | 0
1 | sro_code_done_n |  | RO | 0
0 | sro_code_done_p |  | RO | 0

### IOSCB_IO_CALIB_DDR : IOC_REG2

Address offset | 0x0C
Physical address | 0x0E04 000C | Instance | pvt_ddr
Description | IO calib control register2
Type | RO

Bits | Field Name | Description | Type | Reset
31:29 | Reserved |  | RO | 0x0
28 | sro_comp_out |  | RO | 0
27:21 | sro_ref_ncode |  | RO | 0x00
20:14 | sro_ref_pcode |  | RO | 0x00
13:7 | sro_ncode |  | RO | 0x00
6:0 | sro_pcode |  | RO | 0x00

### IOSCB_IO_CALIB_DDR : IOC_REG3

Address offset | 0x10
Physical address | 0x0E04 0010 | Instance | pvt_ddr
Description | IO calib control register3
Type | RW

Bits | Field Name | Description | Type | Reset
31:23 | Reserved |  | RO | 0x000
22 | reg_calib_foffset_dir |  | RW | 0
21 | reg_calib_roffset_dir |  | RW | 0
20 | reg_calib_move_slewf |  | RW | 0
19 | reg_calib_move_slewr |  | RW | 0
18 | reg_calib_noffset_dir |  | RW | 0
17:12 | reg_calib_noffset |  | RW | 0x00
11 | reg_calib_poffset_dir |  | RW | 0
10:5 | reg_calib_poffset |  | RW | 0x00
4:0 | Reserved |  | RO | 0x00

### IOSCB_IO_CALIB_DDR : IOC_REG4

Address offset | 0x14
Physical address | 0x0E04 0014 | Instance | pvt_ddr
Description | IO calib control register4
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved |  | RO | 0
30 | sro_slew_power_on |  | RO | 0
29 | sro_slew_ioen_out |  | RO | 0
28 | sro_slew_comp_sel |  | RO | 0
27 | sro_slew_comp_en |  | RO | 0
26 | sro_slew_comp_out |  | RO | 0
25 | sro_slew_status |  | RO | 0
24 | sro_slew_intrpt |  | RO | 0
23:18 | reg_slewf |  | RW | 0x00
17:12 | reg_slewr |  | RW | 0x00
11:6 | reg_foffset |  | RW | 0x00
5:0 | reg_roffset |  | RW | 0x00

### IOSCB_IO_CALIB_DDR : IOC_REG5

Address offset | 0x18
Physical address | 0x0E04 0018 | Instance | pvt_ddr
Description | IO calib control register5
Type | RO

Bits | Field Name | Description | Type | Reset
31:30 | Reserved |  | RO | 0x0
29:24 | sro_slewf |  | RO | 0x00
23:18 | sro_slewr |  | RO | 0x00
17:6 | sro_ref_slewf |  | RO | 0x000
5:0 | sro_ref_slewr |  | RO | 0x00

### IOSCB_IO_CALIB_DDR : IOC_REG6

Address offset | 0x1C
Physical address | 0x0E04 001C | Instance | pvt_ddr
Description | IO calibr control resgister6
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved |  | RO | 0x0000 0000
2:1 | reg_calib_clkdiv |  | RW | 0x0
0 | reg_calib_reset |  | RW | 0

IOSCB_IO_CALIB_DDR has no common memories.