## GPSS_MAIN

This section provides information on the GPSS_MAIN Module Instance. Each of the module registers is described below.

Register Lock Bits can prevent the XCVR configuration registers from being overwritten by hosts that have access to these registers. The lock bits can be managed using the Configure Register Lock Bits utility in the Libero SoC. The following registers can be locked.

· GPSSMAIN_SOFT_RESET

Return to mpfs_ioscb_memmap_dri

## GPSS_MAIN Register Mapping Summary

### GPSS_MAIN Common Register Mapping Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000
SPARE | RW | 32 | 0x0000 0000 | 0x190

## GPSS_MAIN Instances Mapping Summary

### GPSS_MAIN : serdes_1_GPSS_MAIN Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0209 0000
SPARE | RW | 32 | 0x0000 0000 | 0x190 | 0x0209 0190

### GPSS_MAIN : serdes_2_GPSS_MAIN Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0211 0000
SPARE | RW | 32 | 0x0000 0000 | 0x190 | 0x0211 0190

### GPSS_MAIN : serdes_3_GPSS_MAIN Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
SOFT_RESET | RW | 32 | 0x0000 0000 | 0x000 | 0x0221 0000
SPARE | RW | 32 | 0x0000 0000 | 0x190 | 0x0221 0190

## GPSS_MAIN Register Descriptions

### GPSS_MAIN : SOFT_RESET

Address offset | 0x000
Physical address | 0x0209 0000 | Instance | serdes_1_GPSS_MAIN
| 0x0211 0000 |  | serdes_2_GPSS_MAIN
| 0x0221 0000 |  | serdes_3_GPSS_MAIN
Description | Compulsory register for all SCB slaves, facilitating global soft reset.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | BLOCKID | This returns the block type and chip location. | RO | 0x0000
|  | Read 0x0000 | [block_address_GPSS_MAIN] Indicates the Block chip location. |  |
15:9 | Reserved |  | RO Rreturns0s | 0x00
8 | PERIPH | This asserts functional reset of the peripheral block. It is asserted and left asserted at power-up. | WO | 0
|  | Write 0 | [scb_periph_not_in_soft_reset_GPSS_MAIN] Reset not asserted. |  |
|  | Write 1 | [scb_periph_reset_GPSS_MAIN] SCB registers reset pulsed. |  |
7:2 | Reserved |  | RO Rreturns0s | 0x00
1 | V_MAP | Resets all the volatile register bits. | WO | 0
|  | Write 0 | [scb_v_regs_not_in_soft_reset_GPSS_MAIN] Reset not asserted. |  |
|  | Write 1 | [scb_v_regs_reset_GPSS_MAIN] SCB Volatile reset (i.e. RW-X registers are reset) |  |
0 | NV_MAP | Resets all the non-volatile register bits (e.g. RW-P bits). | WO | 0
|  | Write 0 | [scb_nv_regs_not_in_soft_reset_GPSS_MAIN] Reset not asserted. |  |
|  | Write 1 | [scb_nv_regs_reset_GPSS_MAIN] SCB Non-Volatile reset (i.e. RW-P registers are reset. |  |

### GPSS_MAIN : SPARE

Address offset | 0x190
Physical address | 0x0209 0190 | Instance | serdes_1_GPSS_MAIN
| 0x0211 0190 |  | serdes_2_GPSS_MAIN
| 0x0221 0190 |  | serdes_3_GPSS_MAIN
Description | Spare reg for scratch-pad and repair purposes.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | SPARE_CTRL | Spare control for future use. | RW | 0x00 0000
7:0 | SCRATCHPAD | Scratch-pad within GPSS address space. | RW | 0x00

GPSS_MAIN has no common memories.