# PolarFire SoC Register Descriptions

Release Notes(Link)

This document presents a summary of the register interfaces for the PolarFire SoC product.

· Each module instance in the design is presented, together with its associated register map and bitfield definitions.

· Register names are represented in UPPERCASE and used throughout the PolarFire SoC embedded firmware.

· The MSS register map is common across the entire family of PolarFire SoC devices

· Peripheral FPGA blocks not related to the MSS such as transceivers, PCIe, Crypto, TVS, and PLLs are provided.

· Use link for the peripheral FPGA block register definitions that are device specific.

§ MPFS Instance Map

The factory reserved registers should NOT be modified. Some reserved registers are RW registers that should not be modified. The reset values in this document are defined for a blank or unprogrammed device. The memory mapped registers are set automatically by the PolarFire Libero Software after being customized for the user’s design through input from configurators and design generation. These registers must be left at their Libero customized defaults, except for use cases that explicitly request different values. Register bits that are not explicitly noted in spreadsheet are considered reserved bits. These registers are READ_ONLY, meaning that a write to them won't affected the reserved value.

User Types: RO= Read Only, RW= Read/Write, RMW= Reserved bits that should not be changed, meaning that the user should perform a read, modify, write to preserve the internal values.

W1toClr = Write 1 clears value

## PolarFire MSS Instance Summary

The table below shows the base address and available address space for each of the leaf instances in the pfsoc_mss_regmap system. These registers are common for the entire PolarFire SoC device family.

Instance Name | Base Address | Range
MMUART0_LO | 0x2000 0000 | 4 KBytes
WDOG0_LO | 0x2000 1000 | 4 KBytes
PFSOC_MSS_TOP_SYSREG | 0x2000 2000 | 1 KBytes
SYSREGSCB | 0x2000 3000 | 1 KBytes
AXISW | 0x2000 4000 | 4 KBytes
MPUCFG | 0x2000 5000 | 4 KBytes
FR Q METER | 0x2000 6000 | 4 KBytes
CFG_DDR_SGMII_PHY | 0x2000 7000 | 4 KBytes
EMMC_SD | 0x2000 8000 | 4 KBytes
DDRCFG | 0x2008 0000 | 256 KBytes
MMUART1_LO | 0x2010 0000 | 4 KBytes
WDOG1_LO | 0x2010 1000 | 4 KBytes
MMUART2_LO | 0x2010 2000 | 4 KBytes
WDOG2_LO | 0x2010 3000 | 4 KBytes
MMUART3_LO | 0x2010 4000 | 4 KBytes
WDOG3_LO | 0x2010 5000 | 4 KBytes
MMUART4_LO | 0x2010 6000 | 4 KBytes
WDOG4_LO | 0x2010 7000 | 4 KBytes
SPI_A_LO | 0x2010 8000 | 4 KBytes
SPI_B_LO | 0x2010 9000 | 4 KBytes
I2C_A_LO | 0x2010 A000 | 4 KBytes
I2C_B_LO | 0x2010 B000 | 4 KBytes
CAN_A_LO | 0x2010 C000 | 4 KBytes
CAN_B_LO | 0x2010 D000 | 4 KBytes
GEM_A_LO | 0x2011 0000 | 8 KBytes
GEM_B_LO | 0x2011 2000 | 8 KBytes
GPIO_IOBANK0_LO | 0x2012 0000 | 4 KBytes
GPIO_IOBANK1_LO | 0x2012 1000 | 4 KBytes
GPIO_FAB_LO | 0x2012 2000 | 4 KBytes
MSRTC_LO | 0x2012 4000 | 4 KBytes
MSTIMER_LO | 0x2012 5000 | 4 KBytes
H2FINT_LO | 0x2012 6000 | 4 KBytes
CRYPTO | 0x2012 7000 | 64 KBytes
ENVMCFG | 0x2020 0000 | 4 KBytes
USB | 0x2020 1000 | 4 KBytes
QSPIXIP | 0x2100 0000 | 4 KBytes
ATHENA | 0x2200 0000 | 64 KBytes
TRACE | 0x2300 0000 | 192 KBytes
MMUART0_HI | 0x2800 0000 | 4 KBytes
WDOG0_HI | 0x2800 1000 | 4 KBytes
MMUART1_HI | 0x2810 0000 | 4 KBytes
WDOG1_HI | 0x2810 1000 | 4 KBytes
MMUART2_HI | 0x2810 2000 | 4 KBytes
WDOG2_HI | 0x2810 3000 | 4 KBytes
MMUART3_HI | 0x2810 4000 | 4 KBytes
WDOG3_HI | 0x2810 5000 | 4 KBytes
MMUART4_HI | 0x2810 6000 | 4 KBytes
WDOG4_HI | 0x2810 7000 | 4 KBytes
SPI_A_HI | 0x2810 8000 | 4 KBytes
SPI_B_HI | 0x2810 9000 | 4 KBytes
I2C_A_HI | 0x2810 A000 | 4 KBytes
I2C_B_HI | 0x2810 B000 | 4 KBytes
CAN_A_HI | 0x2810 C000 | 4 KBytes
CAN_B_HI | 0x2810 D000 | 4 KBytes
GEM_A_HI | 0x2811 0000 | 8 KBytes
GEM_B_HI | 0x2811 2000 | 8 KBytes
GPIO_IOBANK0_HI | 0x2812 0000 | 4 KBytes
GPIO_IOBANK1_HI | 0x2812 1000 | 4 KBytes
GPIO_FAB_HI | 0x2812 2000 | 4 KBytes
MSRTC_HI | 0x2812 4000 | 4 KBytes
MSTIMER_HI | 0x2812 5000 | 4 KBytes
H2FINT_HI | 0x2812 6000 | 4 KBytes
IOSCBCFG | 0x3708 0000 | 4 KBytes