.. _set_synthesis_top_module:

set_synthesis_top_module
----------------------------

This TCL command specifies the name of the Verilog module that should be set as
the top level when running FPGA vendors' synthesis flows.
By default the top level module for FPGA synthesis is "top", which instantiates
the RTL module of the top-level C function ("main" by default, or specified by
``set_custom_top_level_module``).

This top level name is also used when creating a new Libero project.


**Category**

Libero

**Value Type**

string

**Dependencies**

NONE

**Applicable Flows**

All devices and flows

**Test Status**

Actively in-use

**Examples**

    ``set_synthesis_top_module "accelerator_function"``

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