.. _STRENGTH_REDUCTION:

STRENGTH_REDUCTION
--------------------------

Strength reduction is an optimization that
converts multiply-by-constant into shifts and additions::

    Info: StrengthReduction: Replacing multiply by constant (i26 33038) with 3 adders:
            - (1 << 1) + (1 << 4) + (1 << 8) + (1 << 15)
    Info: StrengthReduction: Replacing multiply by constant (i26 6416) with 3 adders:
            + (1 << 4) + (1 << 8) + (1 << 11) + (1 << 12)
    Info: StrengthReduction: Replacing multiply by constant (i26 28784) with 3 adders:
            - (1 << 4) + (1 << 7) - (1 << 12) + (1 << 15)
    Info: StrengthReduction: Replacing multiply by constant (i26 4680) with 3 adders:
            + (1 << 3) + (1 << 6) + (1 << 9) + (1 << 12)
    Info: StrengthReduction: Replacing multiply by constant (i26 33024) with 1 adder:
            + (1 << 8) + (1 << 15)


This optimization saves DSP blocks on the FPGA but can also increase LUT usage in the design.

You can tune the number of adders allowed per multiplier with the constraint:
:ref:`STRENGTH_REDUCTION_ADDERS_ALLOWED_PER_MULTIPLIER`

**Category**

HLS Constraints

**Value Type**

Integer

**Valid Values**

0, 1

**Default Value**

1

**Location Where Default is Specified**

``examples/legup.tcl``

**Dependencies**

None

**Applicable Flows**

All devices and flows

**Test Status**

Actively in-use

**Examples**

    ``set_parameter STRENGTH_REDUCTION 1``

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