Gate arrays and embedded arrays fabricated on a radiation hardened 0.35-micron CMOS process, with up to four levels of metal for interconnect. These devices feature arrays of up to 1.6 million routable gates and 596 pads. High density and high pin count capabilities coupled with an ability to embed cores or memories on the same silicon make these arrays one of the best choices for system level integration. These devices are supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Verilog??, DFT??, Synopsys??, and Vital are the reference front end tools. The Cadence?? Logic Design Planner associated with timing driven layout provides an efficient back end cycle.