Microchip 0.5-micron, array based, CMOS product covering most system integration needs with arrays of up to 270K gates. It is manufactured using a 0.5 micron drawn, three metal layers, CMOS process called SCMOS 3/2RTP. Its base cell architecture provides a high routability of logic with extremely dense compiled RAM and DPRAM. ROM can be generated using synthesis tools. Accurate control of clock distribution can be achieved with PLL hardware and clock tree synthesis software. New noise prevention techniques are applied in the array and in the periphery.