Fully PCI-compliant, SRAM-based FPGA with distributed 18-ns programmable synchronous/asynchronous, dual port/single port SRAM. It also includes eight global clocks, partially or fully reconfigurable Cache Logic ability without loss of data, automatic component generators, and 46,000 ASIC gates. I/O counts range from 129 to 384 in aerospace standard packages. It supports 3.3V. This FPGA is designed to quickly implement high performance, large gate count designs through the use of synthesis and schematic-based tools used on Windows® and Linux® platforms. Microchip design tools provide easy integration with industry standard tools such as Synplicity, Modelsim, and Leonardo Spectrum/Precision Synthesis.