80MHz 32-bit core capable of best-in-class 1.56 DMIPS/MHz.
Allows high performance data transfers without CPU intervention, even in idle mode.
Host, Device, and OTG modes with dedicated DMA.
Up to 1024 messages, 32 message ID filters, 4 message ID masks. Each CAN controller has own dedicated DMA
Industry-standard MII and RMII interfaces enable seamless connection to commodity PHYs as well. Dedicated 2 channel DMA controller supports packet scatter/gather for outstanding low-CPU-overhead performance at full 100Mbps.
Reduce bottlenecks with the PIC32 Bus Matrix capable of concurrent transactions for unique targets.
128-bit wide prefetch cache enables zero wait-state performance from flash for most algorithms.
512KB Flash for code and data is organized in a x128 configuration for maximum bandwidth to the processor. There is an additional 12KB flash in all devices for boot and parameter data programming.
Up to 128KB zero-wait-state code/data SRAM.
Single and multi-vector interrupt controller capable of nesting. One of the 7 priority levels receive dedicated shadow register set for ultra-low latency.
Up to 85 General Purpose I/O
Integrated Voltage Regulator enables single supply 3.3V operation. Integrated Brown Out Detect, Low Voltage Detect, Power On Reset.
The 2-wire Port enables programming and debugging with less pins than JTAG.
With variable bus ratios of 1:1 thru 1:8, the Peripheral bus enables precise power vs. performance decisions for the designer
An 8 or 16 bit parallel peripheral interface supporting LCD panels, additional memory, and more.
Multi-function modes to generate:
Pairs of 16-bit timers can be combined to form 32-bit timers.
In addition to traditional RTC features, the calendar function provides for automatic leap-year, programmable alarms, and more.
