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The UNI/O® Serial EEPROM:
The UNI/O® EEPROM (11xx Family) is a three pin Serial EEPROM
All Communication occurs on the SCIO (pin1)
Working with the UNI/O® Bus:
Manchester Encoding:
The UNI/O® Bus is an asynchronous single I/O bus that uses the Manchester Encoding scheme to multiplex the data and clock on to a single I/O (SCIO). With data stream Manchester-encoded the UNI/O® device synchronizes to the MCU data rate. The clock signal is extracted by the receiver to correctly decode the data value of each bit.
1. MCU establishes the data rate with the start header.
2. UNI/O® device will time out and go to standby if an expected transition is not seen.
3. The EEPROM will sync to the MCU data rate as long as the clock frequency is between 10 KHz to 100 KHz.
Both the master and slave can operate as transmitter or receiver but the master determines which mode is active.
UNI/O® Bus Bit Period
The bit period is determined by the master and forms an integral part of the communication between the master and the receiver. It is with this bit period that clock and data can be extracted.
1. Bit period (TE) determined by the master.
2. One data bit per bit period.
3. Clock is extracted from the bit period – A transition always occurs at the middle of the bit period.
4. Falling edge indicates a ‘0’ while a rising edge indicates a ‘1’.
5. Bit period is between 10 us and 100 us.
6. Clock rate is between 100 KHz and 10 KHz.
UNI/O® EEPROM Command Summary:
1. Standby Pulse
o Long pulse used to ensure device is in standby and ready to receive commands.
o Required after a POR/BOR.
o Required when an error occurs.
o Not required during consecutive commands to the same device.
2. Start Header
o Used by UNI/O® device to synchronize with master.
o MCU must keep bit period the same until the next header is sent.
o UNI/O® device will transmit data at the same rate
3. Acknowledge
o MAK (Master Ack) – Occurs after each byte is sent by master
o MAK is sent as a “1” bit during the MAK period
o NoMAK is sent as a “0” bit during the MAK period
o NoMAK is used to terminate operation and initiate write cycle for write commands
o SAK (Slave Ack) – Slave tells master byte was received OK.
o SAK is sent as a “1” bit during the SAK period
o NoSAK is sent as a lack of state change
o SAK always sent when no error detected
o Exception: not sent after start header
o NoSak sent for error conditions and after the start header
o Master will need to send a Standby Pulse if a NoSAK is received (except after start header)
o The MAK/SAK sequence ensures that both the master and the slave remain synchronized.
o The sequence also reduces the chance of false writes due to unexpected operation of the MCU.
o The MCU can tell every 8 bits if the slave is still synchronized.
UNI/O® Device Address
The UNI/O® EEPROM is designed to allow multiple devices on the same bus
o Each device has an address
o 11XXXX0 address is 0xA0
o Device address precedes any command
o Future devices will have other addresses
o This will allow multiple devices on bus
Reading from the UNI/O® EEPROM
Once the bit period, data rate, and device address has been established, the EEPROM can be read up to “n” consecutive bytes at a time.
o The slave will send 8 bits of data at the current bus data rate
o The Master will need to determine the bit value during each bit period
o For sequential reads, the Master sends a MAK after the data byte
o The slave will send a SAK and another 8 bits.
o The address pointer will wrap around at the end of the array
o Sequential reads can be done forever
Writing to the UNI/O® EEPROM
Write Enable (WREN)
o Sets Write Enable Latch (WEL)
o Required before every write to array & status register
Byte Writes
Once the write enable latch is set, the user may proceed with issuing a WRITE instruction (including the header and device address bytes) followed by the MSB and LSB of the Word Address. Once the last Acknowledge sequence has been performed, the master transmits the data byte to be written. (Also allow for 5 ms write cycle time after instruction.)
Page Writes
o Write up to 16 bytes in one command
o Must stay within page boundary
o Must first set WEL with WREN command
UNI/O® EEPROM Status Register
The status register is an 8-bit register that provides write control and data protection.
The Write-In-Process (WIP) bit indicates whether the 11XX is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. This bit is set and cleared using the WREN and WRDI instructions, respectively. This bit is read-only for any other instruction.
Reading the Status Register (RDSR)
The RDSR instruction provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle.
o Reads the Status Register value
o Only command valid during write cycle
o Can repeatedly read value by sending MAK
o Useful for monitoring WIP
Write Status Register (WRSR)
The WRSR instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two, or all four of the segments of the array.
o Writes BP1, BP0 bits in Status Register
o Must first set WEL with WREN command
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