I'm using a 18F2455 with a 4MHz crystal. My configuration is the following:
#pragma config PLLDIV = 1, CPUDIV = OSC1_PLL2, USBDIV = 2
#pragma config FOSC = HSPLL_HS, FCMEN = OFF, IESO = OFF
#pragma config VREGEN = ON, PWRT = OFF, BOR = ON, BORV = 2
#pragma config WDT = OFF, WDTPS = 32768
#pragma config CCP2MX = ON, PBADEN = OFF, LPT1OSC = OFF, MCLRE = ON
#pragma config STVREN = ON, LVP = OFF, XINST = OFF
I'm expecting a processor frequency of 48MHz (am I right?). If I enter 48MHz in MPSIM debugger and I simulate this function with '1' as a parameter:
void delay_s(int r)
for(q = 0; q < r; ++q)
I get 1.00006s and that's good. However, on the real hardware, I measure 3.56s! I verified the crystal, it's oscillating at 4.00016MHz.
Can bad suited crystal capacitors cause this? I would think it would simply affect the 4MHz oscillation and not the PLL, but I can't find any logical answer for this 3.56s.
Thanks in advance,