ADC Sampling Frequency Selection

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Tom Myers
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2009/08/10 04:32:24 (permalink)
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ADC Sampling Frequency Selection

Hi,
 
I am using the dsPIC33FJ128MC804 (40MIPS) and I have configured the ADC to provide simultaneous sampling on two channels, I am using DMA to buffer the data and Timer 3 to determine the sample rate.
 
I am sampling a 100KHz sine wave at 670KHz. I am confident in the sampling frequency, because I have imported the captured signal into dsPIC works and peformed an FFT which shows the signal to be around 100KHz. If my samping frequency was incorrectly specified then the frequency bins would be inaccurate.
 
When I have:
 

 void initTmr3()
{
 TMR3 = 0x0000;
 PR3  = 5;               // Trigger ADC1 every 0.25uS
 IFS0bits.T3IF = 0;  // Clear Timer 3 interrupt
 IEC0bits.T3IE = 0;  // Disable Timer 3 interrupt
 T3CONbits.TON = 1;  // Start Timer 3
}

 
When PR3 = 5, I get 670KHz sampling rate at 40 MIPS. I have used trial and error to change the PR3 value and import the signal into dsPIC works and perform an FFT and vary the specified sampling rate to see which provides the most comparable frequency i.e. 100KHz.
 
When PR3 = 5 equivalent to 670KHz, when PR3 = 50 its equivalent to 350KHz?
 
This makes no sense to me? Could someone explain how to calculate the sampling frequency as a function of PR3?
 
Many Thanks,
Tom
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5 Replies Related Threads

    sbs136
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    RE: ADC Sampling Frequency Selection 2009/08/10 21:17:05 (permalink)
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    Tom,
     
    Some of the details of your ADC set up are not very clear. Assuming that you have opted of Automatic Sampling (ASAM=1), what is the Tad that has been chosen?
     
    For the sake of an example, let us assume that the required sampling rate is 200kHz to sample a 100kHz input. Now, in case you want to sample as well as convert the sampled values at 200kHz, then, each sample would require (1/200k) = 5us. So, if the trigger source is chosen as TMR3, then the triggers have to be atleast 5us spaced apart. Further, if the 10 bit ADC is being employed, 12Tad s are required for converting one channel.
     
    So, 12Tad=5us => 1Tad = 0.416us
                         => ADCS = 0.416us/25ns ~= 17
     
    Thus, the sampling and conversion depends on the Tad as well as the triggering rate.
     
    I hope this helps you.
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    Tom Myers
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    RE: ADC Sampling Frequency Selection 2009/08/12 12:23:05 (permalink)
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    Hi,
     
    This is the response that I get from Microchip Support:
     
     
    Answer:
    ------------
    I can tell you that you are violating the maximum allowed effective sample rate trigger with the PR3 values you indicated. Based on simultaneous 2 channel ADC configuration here are the formulas plus min and max values:

    10bit ADC mode with simultaneous 2-channel mode:
    ================================================
    Min TAD = 76ns
    Min Sample time = 2TAD
    TCY = 1/40MIPS
    = 25ns
    Min effective TAD in TCY
    TADtcy = (76ns / 25ns)
    = 3.04
    = 4 (must round up to next highest integer value if fractional)

    Min effective TAD in ns
    = (4 * 75ns)
    = 300ns
    if using two channels CH[1:0]
    Max effective Sample Rate = 1 / (Sample time + Conversion time)
    = 1 / (2TAD + (#channels * 12TAD)
    = 1 / (2TAD + 24TAD)
    = 1 / (2TAD + 24TAD)
    = 1 / (26TAD)
    = 1 / (26 * 300ns)
    = 128.21Khz

    PR3 minimum allowed value:
    = FCY / Max effective Sample Rate
    = 40Mhz/128.21Khz
    = 312


     
    Which means that the maximum sampling frequency is NOT 1.1MSPS but 128KSPS?!
     
    Thoughts?
     
    Regards,
    Tom
    #3
    Mike017
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    RE: ADC Sampling Frequency Selection 2009/08/14 17:10:38 (permalink)
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    Hi,
     
    Which means that the maximum sampling frequency is NOT 1.1MSPS but 128KSPS?!

    Check out Code Example CE101. This seems to illustrate how the 1.1 MSPS throughput rate is determined.... given a certain configuration. 
     
    Good Luck,
    Mike
     
     
    #4
    Tom Myers
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    RE: ADC Sampling Frequency Selection 2009/08/15 07:39:38 (permalink)
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    Hi,
     
    This is the latest reply from the guys at Microchip Support - the news is better!
     
     
    I am so sorry. I had a typo which I carried through in all my calculations.
    I originally had used:
     Min effective TAD in ns
              = (4 * 75ns)

    It should have been:
     Min effective TAD in ns
              = (4 * 25ns)

    The corrected calculation for the maximum sample rate using two channels with simulataneous sampling is 384.615Khz. At 40MIPS, TCY = 25ns. Since the minimum TAD time is 76ns, (3) TAD would be 75ns which is technically less than the min spec. The closest TAD possible with a a 25ns TCY cycle that is equal or greater than 76ns is 100ns or (4*TCY).
    Since you selected simultaneous mode all channels are sampled at the same time then converted sequentially as there is only one conversion unit. While a channel is converting no new samples on that channel is permitted. In the case of simultaneous sampling since all channels are sampled together you must wait for all channels to be converted before sampling again. Since the min sampling time is 2TAD and the conversion time is 12TAD and you are converting (2) channels, that yeilds:
      Max effective Sample Rate = 1 / (2TAD + (#channels * 12TAD)
                                                  = 1/ (26 * 100ns)

    There are faster modes than simultaneous sampling that I've listed at the bottom

    Corrected 2-channel simultaneous sampling mode equations:
    ================================================
    10bit ADC mode with simultaneous 2-channel mode:
    ---------------------------------------------------------------------------------
    Min TAD = 76ns
    Min Sample time = 2TAD
    TCY = 1/40MIPS
        = 25ns
    Min effective TAD in TCY
       TADtcy = (76ns / 25ns)
              = 3.04
              = 4 (must round up to next highest integer value if fractional)

    Min effective TAD in ns
              = (4 * 25ns)
              = 100ns
    if using two channels CH[1:0]
     Max effective Sample Rate/Channel = 1 / (Sample time + Conversion time)
                               = 1 / (2TAD + (#channels * 12TAD)
                               = 1 / (2TAD + 24TAD)
                               = 1 / (2TAD + 24TAD)
                               = 1 / (26TAD)
                               = 1 / (26 * 100ns)
                               = 384.615Khz

    PR3 minimum allowed value:
       = FCY / Max effective Sample Rate
       = 40Mhz/384.615Khz
       = 104


    One of the fastest modes is:
     ADxCON1<SIMSAM> = 0;  //Samples multiple channels individually in sequence
     ADxCON1<ASAM> = 1;    //Sampling begins immediately after last conversion.
     ADxCON2<CHPS> = 0x1;  //Converts CH0 and CH1

    This is faster than simultaneous mode because in this case the sampling time of one sample/hold amp is masked by the conversion time on the other. While one channel is converting the other channel, unlike simultaneous mode, is free to aquire the next sample and be waiting to convert immediately after the other S/H channel is finished converting, Since the conversion time is greater than the sample time in this mode you can ignore the 2TAD min sample time requirement. It would only figure back into the equation if the sample time exceeded 12TAD, (i.e. conversion time). The ADC module is capable of conversion rates in excess of 1million conversions per second. At 40MIPS this allows a continious conversion throughput in this configuration of 1/12TAD = 1/12*100ns = 833.34Khz without the wait for the sample time thats needed in simultaneous sampling mode. This translates to an effective per channel sample rate of:
     Max effective Sample Rate/analog input = (833.34Khz / #analog inputs)
                                               = (833.34Khz / 2)
                                               = 416.67Khz

    Ironicly at 38MIPS, TCY=26.31ns
       TADtcy = (76ns / 26.31ns)
              = 2.89
              = 3 (must round up to next highest integer value if fractional)
    Min effective TAD in ns
              = (3 * 26.31ns)
              = 78.93ns

    Effective Sample Rate/analog input = (833.34Khz / #analog inputs)
                                                            = 1/(12TAD * #analog inputs)
                                                            = 527.89Khz per analog input

    For a single analog input that would be in excess of 1.056Msps

    ===================================================

    Simultaneous sampleing mode w/2-channels at 38MIPS instead of 40MIPS would be:  

    TADtcy = (76ns / 26.31ns)
              = 2.89
              = 3 (must round up to next highest integer value if fractional)
    Min effective TAD in ns
              = (3 * 26.31ns)
              = 78.93ns

    Max effective Sample Rate/analog input = 1 / (Sample time + Conversion time)
                               = 1 / (2TAD + (#channels * 12TAD)
                               = 1 / (2TAD + 24TAD)
                               = 1 / (2TAD + 24TAD)
                               = 1 / (26TAD)
                               = 1 / (26 * 78.93ns)
                               = 487.29Khz

    At 38MIPS thats 102.67Khz per analog input faster sample rate than at 40MIPS. (i.e. 487.29Khz - 384.615Khz).



    #5
    Mike017
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    RE: ADC Sampling Frequency Selection 2009/08/15 13:34:43 (permalink)
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    Hi,
     
    OK, nice post. Plus it ties into CE101 re: maximizing throughput.
     
    Good Luck,
    Mike
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