dspic33FJ256MC710 SPI max clock rate

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sylpiette
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2008/08/13 06:48:34 (permalink)
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dspic33FJ256MC710 SPI max clock rate

Hi everyone,
 
In the 70206A.pdf, section 18.4, I can see that the prescaler 1:1 and 2:1 are invalid for a Fcy = 40Mhz.
 
There is also a note that indicates that not all clock rates are supported and the we have to refer to the specific device datasheet for further information.
 
Has anyone ever found the SPI maximum clock frequency that is supported for the dspic33FJ256MC710.
 
I know that the 1:1 prescaler is invalid when sampling at the middle of output time (see device's errata), but I can't find why the 2:1 prescaler is invalid (but it looks like it's valid for a Fcy = 5MHz).
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    BruceTElliott
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    RE: dspic33FJ256MC710 SPI max clock rate 2008/08/13 10:21:06 (permalink)
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    Look at the AC characteristics at the back of the data sheet. The mininimum clock period will be listed. I don't have the data sheet for MC710, but the ones I have specify 100nS as minimum clock period for master mode = 10MHz. Slave mode is somewhat higher. The rise and fall limits etc. are also listed.
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