openocd and mips_m4k

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sjo
Starting Member
2008/06/18 07:59:58
Hi all,

For anyone that is interested we have created a mips branch to the openocd project.
This is still in very early alpha state, basic debugging is possible (step/resume/halt etc)

No flash programming  is implemented yet, but this will follow in time.

For those who have not heard of openocd - it has been around for about 3 years supporting the onchip debug hardware of arm7/9/11 and cortex_m3.
It offers a gdbserver and telnet interface for connecting to your target.

The project homepage is here:
http://developer.berlios.de/projects/openocd
and the mips branch can be found here:
svn://svn.berlios.de/openocd/branches/mips

The current development of the mips branch was tested on a pic32mx (explorer16 board).
The code at the moment is really only intended for people able to debug any issues, so be warned.

Cheers
Spen
xiaofan
Super Member
RE: openocd and mips_m4k 2008/11/26 07:05:42
I still could not find any documentation specific to the PIC32 target. What is the debuggers supported? How to setup?
sjo
Starting Member
RE: openocd and mips_m4k 2008/11/26 10:25:47
Hi,

Documentation to openocd can be built from the source - an online version is also available here:
http://openocd.berlios.de/web/?page_id=54

openocd is a telnet/gdb server, so supports any debugger that uses the gdb server interface.
most people will be using gdb as the backend debugger and possible eclipse/insight as a gui.

As such there is no specific docs for the mips port, just a matter of configuring openocd.
openocd contains sample config files for various targets, including pic32.

for example to use the amontec jtag key with the pic32mx we would start openocd as follows:
openocd -f interface/jtagkey.cfg -f target/pic32mx.cfg -c init -c "reset halt"

this will reset the target and halt at the reset vector.

also the mips branch has been merged into the main trunk, so that is the place to get the latest source
svn://svn.berlios.de/openocd/trunk

Cheers
Spen
post edited by sjo - 2008/11/26 10:29:20
xiaofan
Super Member
RE: openocd and mips_m4k 2008/11/26 18:15:23
There are many good tutorials using Eclipse+GCC for ARM+openocd, however there are no documentations about how to set up a good toolchain with PIC32.

What is the compiler you are using? Do you use plain gdb or Eclipse? How do you connect the debugger to the Explorer 16 board? Any examples?

I highly appreciate your work. One of the main missing piece to get PIC32 to be popular is the lack of a cheap JTAG debugger. If openocd works, then that is great. The other missing piece is a truely free toolchain (mips gcc + newlib or similar).

sjo
Starting Member
RE: openocd and mips_m4k 2008/11/27 02:26:36
Most of the docs for arm will apply to mips.

regarding toolchains you could use one of the following:
1. microchips own, just a matter of getting gdb from a source below.
2. use mips SDE Lite - http://www.mips.com/products/software-tools/mips-sde-lite/
3. use codesourcery - http://www.codesourcery.com/gnu_toolchains/mips
4. build your own from source.

generally i build my own tools, just the way i have always done things - i use either use eclipse or insight to debug.
the initial work was done using the explorer16 and a pic32mx plugin.

as openocd only supports jtag this is the interface we connect to on the explorer16.
initially i used a parallel port wiggler with flying leads, some jtag interfaces such as amontec come with flying leads for non standard connections.
connections used were, arm 20way connector to explorer16 jtag connector (J13).
SRST (15) - J13.11
TDI (5) - J13.3
TDO (13) - J13.5
TMS (7) - J13.7
TCK (9) - J13.9

microchip have used the standard ejtag pinout on the explorer16 - details about the various pinouts  can be found here:
http://www.macraigor.com/downloads/pinouts.pdf

Hope this helps.
Spen
xiaofan
Super Member
RE: openocd and mips_m4k 2008/11/27 05:22:39
Thanks. That is a good start. I actually have a Olimex parallel based wiggler but my current desktop does not have a parallel port. [:@]

I use Jlink for ARM and openocd seems to work (tested under Linux with Olimex LPC-P2148 and IAR LPC2468 KS) even though I use IAR more often under Windows Vista. I was also trying to use openocd with LPC-Stick (modified from Comstick settings, tested under Linux and Windows) as the Hitex 5.2 GUI comes with the stick does not work under Vista.

Maybe Jlink can be used as well for PIC32. wink

Actually the toolchain for PIC32 is an interesting topic. How is the things going with SDE Lite and Code Sourcery MIPS compiler? How do you build from the source? Do you have a port of newlib for your own tools? How do you deal with the header files? Do you have a complete examples for Explorer 16?

Sorry for so much questions. This is really an interesting topics for me. And I believe there are many others who are also interested.
sjo
Starting Member
RE: openocd and mips_m4k 2008/11/27 07:17:46
you should be able to use the jlink no problems - just would have to make an adapter to the mips header.

The microchip compiler was used for initial testing, and the sde-gdb for testing the debugging side.
I have built a mips toolchain but have not tested it with the pic32 yet - the header files would need to be written or borrowed.
newlib was used, it is just not as optimized as the mips c lib used in the microchip toolchain.

codesourcery would probably be the best place to start as their arm toolchains work well.

I have only been testing at a core level (m4k) so pic32 specifics are not as issue at the moment.
The flash driver still needs writing but when i get some spare time will look inot it.

Cheers
Spen
xiaofan
Super Member
RE: openocd and mips_m4k 2008/11/27 07:31:24
Thanks. Now I got a clearer picture of your setup and the status of openocd for PIC32.
1. Currently it is still easier to use Microchip's C32 compiler (with MIPS C library). But in the future, maybe it is possible to use MIPS GCC+newlib. CodeSourcery may be an option as well. This is interesting. I am not a programmer myself but I could help testing if someone wants to embark on this.

2. sde-gdb can be used. Maybe we can also build gdb from Microchip provided source. Last time I did it but I have never tried to use it.

3. Currently flash loading is not working yet. How do you program the device then? Do you use other tools like PICkit 2 or ICD 2?

4. Once the work is finished, this will be very nice as other cheaper JTAG debugger can be used for debugging PIC32. Currently Microchip tools like ICD 2, ICD 3, Real ICE and PICkit 3 all do not use JTAG for PIC32.

Thanks for the nice work!
post edited by xiaofan - 2008/11/27 07:32:54
sjo
Starting Member
RE: openocd and mips_m4k 2008/11/27 07:44:18
1. For work then yes the microchip toolchain is the simplest option.
2. any mips gdb can be used, not just sde.
3. currently i use a realice

The uptake on the openocd mips target has been slow - certainly compared to the arm side of things.
we have a few users using other mips cores but only a couple using the pic32.

as ever more people are needed to get involved, and perhaps write a pic32 flash driver.

Cheers
Spen
xiaofan
Super Member
RE: openocd and mips_m4k 2009/05/21 20:12:21
Updated status thread from OpenOCD mailing list
http://www.mail-archive.com/openocd-development@lists.berlios.de/msg04334.html

Debugging:
http://www.mail-archive.com/openocd-development@lists.berlios.de/msg04445.html

With regards to pic32 debugging most of the work for the ejtag was based on the pic32.All basic functions within gdb should be working, including software/hardware breakpoints.


Programming

>From: John McCarthy
>Date: Mon, Jan 5, 2009 at 12:39 PM
>Subject: [Openocd-development] pic32mx flash fixups and speedups
>To: OpenOCD Development <Openocd-development@lists.berlios.de>
>
>I found my problems with writing boot flash and optimized single 32bit
>word read/writes to speed things up a bit. I also added support for
>writing flash using the pgm_row command to greatly speed up programming.
>
>So now all flash can be erased and/or programmed. Still no chip_erase
>command and data transfers to/from the target are still slow but it is
>usable.



xiaofan
Super Member
RE: openocd and mips_m4k 2009/05/21 20:14:37
Once this support is in place, debugging/programming with many common JTAG tools (like FT2232 based, parallel port wiggler, or Segger J-Link) will be possible for PIC32, under Windows, Linux and Mac OS X.
Samoht
New Member
RE: openocd and mips_m4k 2009/12/10 08:02:48
Hi,

I'm  interrested in openocd project.
Today, Is this project working well for pic32 as programming and debugging ?

I've got an Amontec Key and a pic32mx440f256h target.
The Jtag communication seems  to be OK. The probe recognize the target and I can connect with a telnet session.
Then I try to program flash memory with the flash write_image command but still have the message :


May be it's y pic32.cfg file. Is this correct :
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
I think that the pic32 has no MMU so shall we specify a working area virtual or not? and which address ans size

flash bank pic32mx 0x1d000000 0 0 0 $_TARGETNAME
flash bank pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
shall we specify the size of those banks and chip_width and bus width.

A last question. The dump file (even if my ┬ÁC is blank) seems to work but it's very long : 103 seconds for a 2048 bytes

Anyone has already try to read/write or debug  sucessfully a pic32 with the openocd project ?

Thank you for your help Smile
xiaofan
Super Member
RE: openocd and mips_m4k 2009/12/20 18:27:56
I myself have not tried it for the PIC32. The best place to ask questions is the Openocd-development mailing list.
https://lists.berlios.de/mailman/listinfo/openocd-development
Samoht
New Member
RE: openocd and mips_m4k 2010/01/08 08:18:39
Thank you xiaofan.
Already done but no answer.
I understand that some people succeed in the flash programming and debugging operations with pic32.
It seems that developpers are working to make a faster programming.
isza
New Member
Re: RE: openocd and mips_m4k 2010/08/20 09:25:27

Hi,

I've successfully built the C32 compiler on OSX. When I compile my led blinking test program, I get an ELF which has references to virtual memory addresses.

If I try to write it into the flash memory with OpenOCD, it seems to succeed, but it doesn't run. I'm using the following command: flash write_image test.elf .

If I convert it with pic32mx-bin2hex, it has references to the physical memory, and OpenOCD is not able to write it into the flash, even if I configure the physical flash banks properly in pic32.cfg.

What am I doing wrong? Do I have to erase the banks somehow before trying to write them?

OpenOCD says that every sector is protected. What does it mean?

> flash info 0              
#0 : pic32mx at 0x9d000000, size 0x00080000, buswidth 4, chipwidth 4
#  0: 0x00000000 (0x1000 4kB) protected
#  1: 0x00001000 (0x1000 4kB) protected


Thanks for your help


isza
New Member
Re: RE: openocd and mips_m4k 2010/08/20 13:13:32
They have lines like this in pic32mx.c:
target_write_u32(target, PIC32MX_NVMADDR,    KS1Virt2Phys(address));


So I guess I have to specify virtual addresses everywhere.


I tried to erase the flash with the erase option of write_flash, but then openocd complained about the configuration bits, which do not start at a segment boundary. The chip erase command returns without any error, but i don't know if it really works. I don't even know how I could check if it works. :/ I'm stuck.

isza
New Member
Re: RE: openocd and mips_m4k 2010/08/21 02:50:32
I managed to erase the appropriate segments in the flash, or at least openocd did something. I also seem to be able to program the flash, but the code doesn't run. 


I have a PIC32MX340F512H, with to bicolor leds connected like this:


RB0 -- LED -- 220R -- RB1
RB6 -- LED -- 220R -- RB7


I'm new to PIC32, and I can't decide if my test code is correct.


Should this code make them glow?

#include <p32xxxx.h>
#pragma config POSCMOD = OFF, FNOSC = FRC, FWDTEN = OFF

main()
{
    TRISB = 0b00111100;
    PORTB = 0b10000010;
    while(1);
}

When I halt the CPU with OpenOCD, PC=0xBFC00380, which is the exception handler. :/ The other registers have some random values instead of the ones they should be holding according to the assembly code GCC generates. :(

isza
New Member
Re: RE: openocd and mips_m4k 2010/08/21 12:12:19
I installed the GIT version of openocd, and I was happy to see that they improved the PIC32 support. :) The new version has a virtual memory driver, and the configuration file of PIC32 uses it. :)

Sadly, it doesn't work. I figured out how to read the memory with openocd. Everything is 0xFF everywhere. I can program words with the pic32mx pgm_word command successfully, but flash write_image just doesn't work. It says "wrote 17284 bytes from file main in 1.735783s (9.724 KiB/s)", but leaves 0xFF everywhere. :/

In the meantime I borrowed a pickit2, but it doesn't support PIC32MX340F512H.
isza
New Member
Re: RE: openocd and mips_m4k 2010/08/21 14:35:32
Writing smaller amounts of data to the flash works, but for more than 128 bytes, openocd has a separate function, which does not work:

static int pic32mx_write_row(struct flash_bank *bank, uint32_t address, uint32_t srcaddr)

Now I disabled it, and it seems to work. It became really slow, because it can only write one word each time. I hope it will survive the many write operations. :)



isza
New Member
Re: RE: openocd and mips_m4k 2010/08/22 02:00:29
Well, only using pic32mx_write_word is so slow, that it's literally unusable. It takes about a second to write 4 bytes.

I figured out that pic32mx_write_row works properly, it can write the content of the RAM to the flash, but filling the RAM doesn't work. Now I "only" need to correct the function that fills the working area in the RAM. 
isza
New Member
Re: RE: openocd and mips_m4k 2010/08/22 05:09:33
In the source of openocd, target.c has these lines:

/* use bulk writes above a certain limit. This may have to be changed */
if (aligned > 128)
{
if ((retval = target->type->bulk_write_memory(target, address, aligned / 4, buffer)) != ERROR_OK)
return retval;
}

This is what I had to disable to get it to work. For some mystical reason write_image still doesn't work, so I had to fill the flash banks separately. My led is finally glowing. :)


The writing is still slow, because openocd can only write 512 or 4 bytes at once, and if the remaining part is less than 512 bytes, it uses the 4 byte method. :/ I think this method sucks. It should preread the content of the flash, and use the 512 byte method every time. I'm just changing pic32mx_write_block to work like this. I'll tell you about it in my next post. 

sjo
Starting Member
Re: RE: openocd and mips_m4k 2010/08/23 01:30:59
Could you show the cmd's you are using?
The pic32 requires the init script to be called so rather than "reset halt" you need to call "reset init"

If you are still getting problems than post the openocd log file, eg. openocd -d3 -l openocd.log

Cheers
Spen
tcmichals
New Member
Re: RE: openocd and mips_m4k 2010/09/22 12:26:29
I'm getting the same issue, not being able to write to flash, I'm using the latest and greatest openocd 0.5.0 
Plus I'm not able to single step. 
here is the issue with single step...
I've got a valid image in flash. Start openocd -f interface/jtagkey.cfg -f board/pic-p32mx-uwb32.cfg 0f /usr/local/share/openocd/httpd/ --debug 3 -c init -c "reset halt"

then start ./mips-sde-elf-gd
.gdbinit contains
target remote localhost:3333
monitor reset halt

at the gdb prompt I do the following:
JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
target state: halted
target halted in MIPS32 mode due to debug-request, pc: 0xbfc00000
(gdb) stepi
stepi ignored. GDB will now fetch the register state from the target.

Program received signal SIGINT, Interrupt.
0x0000c0b

but I can telnet into openocd and do a step and it works...
tcmichals@tcmichals-desktop:~/CodeSourcery/Sourcery_G++_Lite/bin$ telnet localhost 4444
Trying ::1...
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> step
target state: halted
target halted in MIPS32 mode due to single-step, pc: 0xbfc00004


Any clues? it seems that gdb is not working but the telnet seems to work..
sjo
Starting Member
Re: RE: openocd and mips_m4k 2010/09/23 12:59:44
Like i mentioned before you need to call reset init rather than reset halt.
You also need to make sure your config script is using target/pic32mx.cfg, this script is required to configure the pic32 for flash programming. Look at board/pic-p32mx.cfg for an example.

With gdb the first single step is ignored, this is so openocd can sync with gdb.

Other than that it all looks fine.

Cheers
Spen
tcmichals
New Member
Re: RE: openocd and mips_m4k 2010/09/26 09:43:25
I'm trying to program flash and having issues, used the reset init command.

Ok here is my pic-p32mx-ubw32.cfg
# The UBW32  has a PIC32MX460F512L

set CPUTAPID 0x50978053
source [find target/pic32mx.cfg]

I'm trying to program flash using a hex file.  Open a telnet session and do the following
> reset init
JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
target state: halted
target halted in MIPS32 mode due to debug-request, pc: 0xbfc00000
>
 flash write_image erase ./tmp/hello.hex 0 ihex
auto erase enabled
couldn't open ./tmp/hello.hex
Command handler execution failed
in procedure 'flash'
> flash write_image erase /tmp/hello.hex 0 ihex
auto erase enabled
device id = 0x50978053 (manuf 0x029 dev 0x78, ver 0x05)
flash size = 12kbytes
mini program did not return to start
Error reading unexpected address 0xff200000
wrote 4096 bytes from file /tmp/hello.hex in 5.636088s (0.710 KiB/s)
>

The output from openocd..

ser : 375 10199 target.c:1298 target_arch_state(): target state: halted
User : 376 10199 mips32.c:259 mips32_arch_state(): target halted in MIPS32 mode due to debug-request, pc: 0xbfc00000
Debug: 377 10199 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu curstate
Debug: 378 10199 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu curstate
Debug: 379 10199 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu cget -chain-position
Debug: 380 10199 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu cget -chain-position
Debug: 381 10199 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled pic32mx.cpu
Debug: 382 10199 command.c:156 script_debug(): command - ocd_jtag ocd_jtag tapisenabled pic32mx.cpu
Debug: 383 10199 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu arp_waitstate halted 5000
Debug: 384 10199 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu arp_waitstate halted 5000
Debug: 385 10202 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu invoke-event reset-init
Debug: 386 10202 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu invoke-event reset-init
Debug: 387 10202 target.c:3631 target_handle_event(): target: (0) pic32mx.cpu (mips_m4k) event: 19 (reset-init) action:
    #
    # from reset the pic32 cannot execute code in ram - enable ram execution
    # minimum offset from start of ram is 2k
    #

    global _PIC32MX_DATASIZE
    global _PIC32MX_PROGSIZE

    # BMXCON
    mww 0xbf882000 0x001f0040
    # BMXDKPBA: 2k kernel data @ 0xa0000800
    mww 0xbf882010 $_PIC32MX_DATASIZE
    # BMXDUDBA: 16k kernel program @ 0xa0000800
    mww 0xbf882020 $_PIC32MX_PROGSIZE
    # BMXDUPBA: 0k user program
    mww 0xbf882030 $_PIC32MX_PROGSIZE

Debug: 388 10202 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_mww 0xbf882000 0x001f0040
Debug: 389 10202 command.c:156 script_debug(): command - mww ocd_mww 0xbf882000 0x001f0040
Debug: 391 10202 target.c:1315 target_write_buffer(): writing buffer of 4 byte at 0xbf882000
Debug: 392 10202 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf882000, size: 0x00000004, count: 0x00000001
Debug: 394 10452 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_mww 0xbf882010 0x800
Debug: 395 10452 command.c:156 script_debug(): command - mww ocd_mww 0xbf882010 0x800
Debug: 397 10452 target.c:1315 target_write_buffer(): writing buffer of 4 byte at 0xbf882010
Debug: 398 10452 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf882010, size: 0x00000004, count: 0x00000001
Debug: 399 10660 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_mww 0xbf882020 14336
Debug: 400 10660 command.c:156 script_debug(): command - mww ocd_mww 0xbf882020 14336
Debug: 402 10660 target.c:1315 target_write_buffer(): writing buffer of 4 byte at 0xbf882020
Debug: 403 10660 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf882020, size: 0x00000004, count: 0x00000001
Debug: 405 10876 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_mww 0xbf882030 14336
Debug: 406 10876 command.c:156 script_debug(): command - mww ocd_mww 0xbf882030 14336
Debug: 408 10876 target.c:1315 target_write_buffer(): writing buffer of 4 byte at 0xbf882030
Debug: 409 10876 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf882030, size: 0x00000004, count: 0x00000001
Debug: 410 11125 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu invoke-event reset-end
Debug: 411 11125 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu invoke-event reset-end
Debug: 412 110419 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_flash write_image erase ./tmp/hello.hex 0 ihex
Debug: 413 110419 command.c:156 script_debug(): command - ocd_flash ocd_flash write_image erase ./tmp/hello.hex 0 ihex
User : 415 110424 command.c:566 command_print(): auto erase enabled
Error: 416 110424 fileio.c:70 fileio_open_local(): couldn't open ./tmp/hello.hex
Debug: 417 110424 command.c:647 run_command(): Command failed with error code -1202
User : 418 110424 command.c:851 openocd_jim_vfprintf(): Command handler execution failed
User : 419 110424 command.c:851 openocd_jim_vfprintf(): in procedure 'flash' User : 420 110424 command.c:851 openocd_jim_vfprintf():
Debug: 421 117549 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_flash write_image erase /tmp/hello.hex 0 ihex
Debug: 422 117549 command.c:156 script_debug(): command - ocd_flash ocd_flash write_image erase /tmp/hello.hex 0 ihex
User : 424 117553 command.c:566 command_print(): auto erase enabled
Debug: 425 117553 configuration.c:87 find_file(): found /tmp/hello.hex
Info : 426 117553 pic32mx.c:527 pic32mx_probe(): device id = 0x50978053 (manuf 0x029 dev 0x78, ver 0x05)
Info : 427 117553 pic32mx.c:561 pic32mx_probe(): flash size = 12kbytes
Debug: 428 117553 core.c:703 flash_write_unlock(): image_read_section: section = 0, t_section_num = 0, section_offset = 0, buffer_size = 0, size_read = 2176
Debug: 429 117554 target.c:1629 target_write_u32(): address: 0xbf80f420, value: 0x1fc00000
Debug: 430 117554 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf80f420, size: 0x00000004, count: 0x00000001
Debug: 431 117759 target.c:1629 target_write_u32(): address: 0xbf80f400, value: 0x00004004
Debug: 432 117759 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf80f400, size: 0x00000004, count: 0x00000001
Debug: 433 117943 target.c:1629 target_write_u32(): address: 0xbf80f410, value: 0xaa996655
Debug: 434 117943 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf80f410, size: 0x00000004, count: 0x00000001
Debug: 436 118127 target.c:1629 target_write_u32(): address: 0xbf80f410, value: 0x556699aa
Debug: 437 118127 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf80f410, size: 0x00000004, count: 0x00000001
Debug: 438 118312 target.c:1629 target_write_u32(): address: 0xbf80f408, value: 0x00008000
Debug: 439 118312 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf80f408, size: 0x00000004, count: 0x00000001
Debug: 440 118495 mips_m4k.c:843 mips_m4k_read_memory(): address: 0xbf80f400, size: 0x00000004, count: 0x00000001
Debug: 442 118639 target.c:1552 target_read_u32(): address: 0xbf80f400, value: 0x00004004
Debug: 443 118639 target.c:1629 target_write_u32(): address: 0xbf80f404, value: 0x00004000
Debug: 444 118639 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf80f404, size: 0x00000004, count: 0x00000001
Debug: 445 118823 pic32mx.c:428 pic32mx_write(): writing to flash at address 0x1fc00000 at offset 0x00000000 count: 0x00001000
Debug: 446 118823 target.c:1125 target_alloc_working_area_try(): MMU disabled, using physical address for working memory 0xa0000800
Debug: 447 118823 target.c:1185 target_alloc_working_area_try(): allocated new working area at address 0xa0000800
Debug: 448 118823 target.c:1315 target_write_buffer(): writing buffer of 216 byte at 0xa0000800
Debug: 449 118823 mips_m4k.c:971 mips_m4k_bulk_write_memory(): address: 0xa0000800, count: 0x00000036
Debug: 450 118823 target.c:1185 target_alloc_working_area_try(): allocated new working area at address 0xa00008d8
Debug: 454 120320 mips32_pracc.c:990 mips32_pracc_fastdata_xfer(): mips32_pracc_fastdata_xfer using 0xa00008d8 for write handler
Error: 455 120360 mips32_pracc.c:1051 mips32_pracc_fastdata_xfer(): mini program did not return to start
Debug: 456 120360 target.c:1185 target_alloc_working_area_try(): allocated new working area at address 0xa0000958
Debug: 457 120360 target.c:1315 target_write_buffer(): writing buffer of 4096 byte at 0xa0000958
Debug: 458 120360 mips_m4k.c:971 mips_m4k_bulk_write_memory(): address: 0xa0000958, count: 0x00000400
Error: 459 120364 mips32_pracc.c:165 mips32_pracc_exec_read(): Error reading unexpected address 0xff200000
Debug: 460 120364 mips32_pracc.c:990 mips32_pracc_fastdata_xfer(): mips32_pracc_fastdata_xfer using 0xa00008d8 for write handler
Debug: 461 120446 mips32.c:373 mips32_run_algorithm(): Running algorithm
Debug: 462 120446 mips32.c:177 mips32_write_core_reg(): write core reg 4 value 0x958
Debug: 463 120446 mips32.c:177 mips32_write_core_reg(): write core reg 5 value 0x1fc00000
Debug: 464 120446 mips32.c:177 mips32_write_core_reg(): write core reg 6 value 0x400
Debug: 465 120446 mips32.c:177 mips32_write_core_reg(): write core reg 37 value 0xa0000800
Debug: 468 121372 mips_m4k.c:843 mips_m4k_read_memory(): address: 0xff300000, size: 0x00000004, count: 0x00000001
Debug: 469 121514 target.c:1552 target_read_u32(): address: 0xff300000, value: 0x0003c41b
Debug: 470 121514 target.c:1629 target_write_u32(): address: 0xff300000, value: 0x0003c40b
Debug: 471 121514 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xff300000, size: 0x00000004, count: 0x00000001
Debug: 473 121707 target.c:1021 target_call_event_callbacks(): target event 22 (debug-resumed)
Debug: 474 121707 mips_m4k.c:402 mips_m4k_resume(): target debug resumed at 0xa0000800
Debug: 475 121892 mips_m4k.c:843 mips_m4k_read_memory(): address: 0xff301000, size: 0x00000004, count: 0x00000001
Debug: 476 122034 target.c:1552 target_read_u32(): address: 0xff301000, value: 0x06000000
Debug: 477 122034 mips_m4k.c:843 mips_m4k_read_memory(): address: 0xff302000, size: 0x00000004, count: 0x00000001
Debug: 479 122178 target.c:1552 target_read_u32(): address: 0xff302000, value: 0x02000000
Debug: 482 123189 mips_m4k.c:109 mips_m4k_debug_entry(): entered debug state at PC 0xa0000848, target->state: halted
Debug: 483 123189 target.c:1021 target_call_event_callbacks(): target event 21 (debug-halted)
Debug: 484 123189 mips32.c:476 mips32_run_algorithm(): restoring register pc with value 0xbfc00000
User : 485 123189 command.c:566 command_print(): wrote 4096 bytes from file /tmp/hello.hex in 5.636088s (0.710 KiB/s)





tcmichals
New Member
Re: RE: openocd and mips_m4k 2010/09/26 09:56:54
I download the default HIDboot.hex using PIC2kit and I'm trying to single step from reset.

start openocd using..
openocd -f interface/jtagkey.cfg -f board/pic-p32mx-uwb32.cfg 0f /usr/local/share/openocd/httpd/ --debug 3 -c init -c "reset halt"

the defualt .gdbinit is
target remote localhost:3333
monitor reset init

start gdb
tcmichals@tcmichals-desktop:~/CodeSourcery/Sourcery_G++_Lite/bin$ ./mips-sde-elf-gdb
GNU gdb (Sourcery G++ Lite 4.4-191) 7.0.50.20100218-cvs
Copyright (C) 2010 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=i686-pc-linux-gnu --target=mips-sde-elf".
For bug reporting instructions, please see:
<https://support.codesourc.y.com/GNUToolchain/>.
0x0000c0bf in ?? ()
JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
target state: halted
target halted in MIPS32 mode due to debug-request, pc: 0xbfc00000
(gdb) stepi
stepi ignored. GDB will now fetch the register state from the target.

Program received signal SIGINT, Interrupt.
0x0000c0bf in ?? ()
(gdb)
ug: 348 13288 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu invoke-event reset-start
Debug: 349 13288 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_jtag arp_init-reset
Debug: 350 13288 command.c:156 script_debug(): command - ocd_jtag ocd_jtag arp_init-reset
Debug: 351 13288 core.c:1509 jtag_init_reset(): Initializing with hard TRST+SRST reset
Debug: 352 13288 core.c:727 jtag_add_reset(): JTAG reset with TLR instead of TRST
Debug: 353 13288 core.c:330 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 354 13289 core.c:1414 jtag_init_inner(): Init JTAG chain
Debug: 355 13289 core.c:330 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 356 13290 core.c:1049 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 357 13290 core.c:330 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 358 13293 core.c:949 jtag_examine_chain_display(): JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
Debug: 359 13293 core.c:1213 jtag_validate_ircapture(): IR capture validation scan
Debug: 360 13295 core.c:1274 jtag_validate_ircapture(): pic32mx.cpu: IR capture 0x01
Debug: 361 13295 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu cget -chain-position
Debug: 362 13295 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu cget -chain-position
Debug: 363 13295 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled pic32mx.cpu
Debug: 364 13295 command.c:156 script_debug(): command - ocd_jtag ocd_jtag tapisenabled pic32mx.cpu
Debug: 365 13295 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu arp_examine
Debug: 366 13295 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu arp_examine
Debug: 367 13297 mips_ejtag.c:266 mips_ejtag_init(): impcode: 0x61014000
Debug: 368 13297 mips_ejtag.c:283 mips_ejtag_init(): EJTAG: Version 3.1 Detected
Debug: 369 13297 mips_ejtag.c:296 mips_ejtag_init(): EJTAG: features: R4k DINT MIPS16 noDMA MIPS32
Debug: 370 13297 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu invoke-event reset-assert-pre
Debug: 371 13297 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu invoke-event reset-assert-pre
Debug: 372 13297 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu cget -chain-position
Debug: 373 13297 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu cget -chain-position
Debug: 374 13297 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled pic32mx.cpu
Debug: 375 13297 command.c:156 script_debug(): command - ocd_jtag ocd_jtag tapisenabled pic32mx.cpu
Debug: 376 13297 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu arp_reset assert 1
Debug: 377 13297 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu arp_reset assert 1
Debug: 378 13297 mips_m4k.c:224 mips_m4k_assert_reset(): target->state: halted
Debug: 379 13297 mips_m4k.c:259 mips_m4k_assert_reset(): Using MTAP reset to reset processor...
Debug: 380 13301 mips_m4k.c:178 mips_m4k_halt(): target->state: reset
Debug: 381 13301 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu invoke-event reset-assert-post
Debug: 382 13301 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu invoke-event reset-assert-post
Debug: 383 13301 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu invoke-event reset-deassert-pre
Debug: 384 13301 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu invoke-event reset-deassert-pre
Debug: 385 13301 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu cget -chain-position
Debug: 386 13301 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu cget -chain-position
Debug: 387 13301 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled pic32mx.cpu
Debug: 388 13301 command.c:156 script_debug(): command - ocd_jtag ocd_jtag tapisenabled pic32mx.cpu
Debug: 389 13301 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu arp_reset deassert 1
Debug: 390 13301 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu arp_reset deassert 1
Debug: 391 13301 mips_m4k.c:299 mips_m4k_deassert_reset(): target->state: reset
Debug: 392 13301 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu invoke-event reset-deassert-post
Debug: 393 13301 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu invoke-event reset-deassert-post
Debug: 394 13302 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu cget -chain-position
Debug: 395 13302 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu cget -chain-position
Debug: 396 13302 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled pic32mx.cpu
Debug: 397 13302 command.c:156 script_debug(): command - ocd_jtag ocd_jtag tapisenabled pic32mx.cpu
Debug: 398 13302 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu arp_waitstate halted 1000
Debug: 399 13302 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu arp_waitstate halted 1000
Debug: 400 13368 mips_m4k.c:135 mips_m4k_poll(): Reset Detected
Debug: 403 14676 mips_m4k.c:109 mips_m4k_debug_entry(): entered debug state at PC 0xbfc00000, target->state: halted
Debug: 404 14676 target.c:1021 target_call_event_callbacks(): target event 2 (gdb-halt)
Debug: 405 14676 target.c:1021 target_call_event_callbacks(): target event 3 (halted)
User : 406 14676 target.c:1298 target_arch_state(): target state: halted
User : 407 14676 mips32.c:259 mips32_arch_state(): target halted in MIPS32 mode due to debug-request, pc: 0xbfc00000
Debug: 408 14676 target.c:1021 target_call_event_callbacks(): target event 8 (gdb-end)
Debug: 409 14676 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu curstate
Debug: 410 14676 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu curstate
Debug: 411 14676 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu cget -chain-position
Debug: 412 14676 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu cget -chain-position
Debug: 413 14676 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled pic32mx.cpu
Debug: 414 14676 command.c:156 script_debug(): command - ocd_jtag ocd_jtag tapisenabled pic32mx.cpu
Debug: 415 14676 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu arp_waitstate halted 5000
Debug: 416 14676 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu arp_waitstate halted 5000
Debug: 417 14678 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu invoke-event reset-init
Debug: 418 14678 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu invoke-event reset-init
Debug: 419 14678 target.c:3631 target_handle_event(): target: (0) pic32mx.cpu (mips_m4k) event: 19 (reset-init) action:
    #
    # from reset the pic32 cannot execute code in ram - enable ram execution
    # minimum offset from start of ram is 2k
    #

    global _PIC32MX_DATASIZE
    global _PIC32MX_PROGSIZE

    # BMXCON
    mww 0xbf882000 0x001f0040
    # BMXDKPBA: 2k kernel data @ 0xa0000800
    mww 0xbf882010 $_PIC32MX_DATASIZE
    # BMXDUDBA: 16k kernel program @ 0xa0000800
    mww 0xbf882020 $_PIC32MX_PROGSIZE
    # BMXDUPBA: 0k user program
    mww 0xbf882030 $_PIC32MX_PROGSIZE

Debug: 420 14678 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_mww 0xbf882000 0x001f0040
Debug: 421 14678 command.c:156 script_debug(): command - mww ocd_mww 0xbf882000 0x001f0040
Debug: 423 14678 target.c:1315 target_write_buffer(): writing buffer of 4 byte at 0xbf882000
Debug: 424 14678 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf882000, size: 0x00000004, count: 0x00000001
Debug: 425 14912 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_mww 0xbf882010 0x800
Debug: 426 14912 command.c:156 script_debug(): command - mww ocd_mww 0xbf882010 0x800
Debug: 428 14912 target.c:1315 target_write_buffer(): writing buffer of 4 byte at 0xbf882010
Debug: 429 14912 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf882010, size: 0x00000004, count: 0x00000001
Debug: 430 15120 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_mww 0xbf882020 14336
Debug: 431 15120 command.c:156 script_debug(): command - mww ocd_mww 0xbf882020 14336
Debug: 433 15120 target.c:1315 target_write_buffer(): writing buffer of 4 byte at 0xbf882020
Debug: 434 15120 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf882020, size: 0x00000004, count: 0x00000001
Debug: 435 15336 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_mww 0xbf882030 14336
Debug: 436 15336 command.c:156 script_debug(): command - mww ocd_mww 0xbf882030 14336
Debug: 438 15336 target.c:1315 target_write_buffer(): writing buffer of 4 byte at 0xbf882030
Debug: 439 15336 mips_m4k.c:877 mips_m4k_write_memory(): address: 0xbf882030, size: 0x00000004, count: 0x00000001
Debug: 440 15556 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_pic32mx.cpu invoke-event reset-end
Debug: 441 15556 command.c:156 script_debug(): command - ocd_pic32mx.cpu ocd_pic32mx.cpu invoke-event reset-end
Debug: 442 34450 gdb_server.c:2189 gdb_input_inner(): received packet: 'mc0be,2'
Debug: 443 34450 gdb_server.c:1266 gdb_read_memory_packet(): addr: 0x0000c0be, len: 0x00000002
Debug: 444 34450 target.c:1397 target_read_buffer(): reading buffer of 2 byte at 0x0000c0be
Debug: 445 34450 mips_m4k.c:843 mips_m4k_read_memory(): address: 0x0000c0be, size: 0x00000002, count: 0x00000001
Debug: 447 34943 gdb_server.c:2189 gdb_input_inner(): received packet: 'vCont?'
Debug: 448 34943 gdb_server.c:2189 gdb_input_inner(): received packet: 'Hc0'
Debug: 449 34943 gdb_server.c:2189 gdb_input_inner(): received packet: 's'
Warn : 450 34943 gdb_server.c:2280 gdb_input_inner(): stepi ignored. GDB will now fetch the register state from the target.
Debug: 451 34943 gdb_server.c:2189 gdb_input_inner(): received packet: 'g'
Debug: 452 34944 gdb_server.c:2189 gdb_input_inner(): received packet: 'mc0bf,4'
Debug: 453 34944 gdb_server.c:1266 gdb_read_memory_packet(): addr: 0x0000c0bf, len: 0x00000004
Debug: 454 34944 target.c:1397 target_read_buffer(): reading buffer of 4 byte at 0x0000c0bf
Debug: 455 34944 mips_m4k.c:843 mips_m4k_read_memory(): address: 0x0000c0bf, size: 0x00000001, count: 0x00000001
Debug: 456 35428 mips_m4k.c:843 mips_m4k_read_memory(): address: 0x0000c0c0, size: 0x00000002, count: 0x00000001
Debug: 458 35885 mips_m4k.c:843 mips_m4k_read_memory(): address: 0x0000c0c2, size: 0x00000001, count: 0x00000001



tcmichals
New Member
Re: RE: openocd and mips_m4k 2010/09/26 10:01:22
If I just do telnet and step it works fine
> continue
> reset run
JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
> reset init
JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
target state: halted
target halted in MIPS32 mode due to debug-request, pc: 0xbfc00000
> step
target state: halted
target halted in MIPS32 mode due to single-step, pc: 0xbfc00004
> step
target state: halted
target halted in MIPS32 mode due to single-step, pc: 0xbf

sjo
Starting Member
Re: RE: openocd and mips_m4k 2010/09/30 03:49:12
As i mentioned before quite often the first step is ignored when using gdb, this is so we sync openocd and gdb.
Just perform another step and all will work.

Cheers
Spen

tcmichals

If I just do telnet and step it works fine
> continue
> reset run
JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
> reset init
JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
target state: halted
target halted in MIPS32 mode due to debug-request, pc: 0xbfc00000
> step
target state: halted
target halted in MIPS32 mode due to single-step, pc: 0xbfc00004
> step
target state: halted
target halted in MIPS32 mode due to single-step, pc: 0xbf



sjo
Starting Member
Re: RE: openocd and mips_m4k 2010/09/30 04:02:31
As i mentioned before quite often the first step is ignored when using gdb, this is so we sync openocd and gdb.
Just perform another step and all will work.

Cheers
Spen

tcmichals

If I just do telnet and step it works fine
> continue
> reset run
JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
> reset init
JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
target state: halted
target halted in MIPS32 mode due to debug-request, pc: 0xbfc00000
> step
target state: halted
target halted in MIPS32 mode due to single-step, pc: 0xbfc00004
> step
target state: halted
target halted in MIPS32 mode due to single-step, pc: 0xbf



tcmichals
New Member
Re: RE: openocd and mips_m4k 2010/09/30 20:48:23
Ok, I have code loaded at 0xbfc0_000.
0his is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=i686-pc-linux-gnu --target=mips-sde-elf".
For bug reporting instructions, please see:
<https://support.codesourc...m/GNUToolchain/>...
Reading symbols from /tmp/hello.elf...done.
0x00000000 in ?? ()
JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
target state: halted
target halted in MIPS32 mode due to debug-request, pc: 0xbfc00000
(gdb) stepi
stepi ignored. GDB will now fetch the register state from the target.

Program received signal SIGINT, Interrupt.
0xbfc00000 in reset_vector ()
(gdb) stepi
Cannot access memory at address 0xbfc00000
(gdb) stepi
Cannot access memory at address 0xbfc00000
(gdb) stepi
Cannot access memory at address 0xbfc00000
(gdb)

from telnet
ips-sde-elf-objcopy -O ihex hello.elf hello.hex --change-address -0xA0000000
tcmichals@tcmichals-desktop:/media/UWB32/ubw32/fromScratch$ cp hello.elf /tmp
tcmichals@tcmichals-desktop:/media/UWB32/ubw32/fromScratch$ !tel
telnet localhost 4444
Trying ::1...
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> reset init
JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
target state: halted
target halted in MIPS32 mode due to debug-request, pc: 0xbfc00000
> step
target state: halted
target halted in MIPS32 mode due to single-step, pc: 0xbfc00004
> step
target state: halted
target halted in MIPS32 mode due to single-step, pc: 0xbfc00008
>



tcmichals
New Member
Re: RE: openocd and mips_m4k 2010/09/30 21:16:52
I cannot see any code? ie assembly

JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
target state: halted
target halted in MIPS32 mode due to debug-request, pc: 0xbfc00000
(gdb) load
Loading section .reset, size 0x10 lma 0xbfc00000
Load failed
(gdb) stepi
stepi ignored. GDB will now fetch the register state from the target.

Program received signal SIGINT, Interrupt.
0xbfc00000 in reset_vector ()
(gdb) stepi
Cannot access memory at address 0xbfc00000
(gdb) stepi
Cannot access memory at address 0xbfc00000
(gdb)


I telnet in
Escape character is '^]'.
Open On-Chip Debugger
> mdw 0x1fc00000 2
0x1fc00000: 3c1abfc0 275a0380
> mdw 0x1fc00000 2
0x1fc00000: 3c1abfc0 275a0380
> mdw 0xbfc00000 2
0xbfc00000: 3c1abfc0 275a0380



(gdb) disassemble *0x1fc00000
No function contains specified address.
(gdb) disassemble 0x1fc00000
No function contains specified address.
(gdb) disassemble *0xbfc00000
Cannot access memory at address 0xbfc00000
(gdb)


tcmichals
New Member
Re: RE: openocd and mips_m4k 2010/09/30 21:26:14
Ok... I tried this, still cannot single step
Copyright (C) 2010 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=i686-pc-linux-gnu --target=mips-sde-elf".
For bug reporting instructions, please see:
<https://support.codesourc...m/GNUToolchain/>...
Reading symbols from /tmp/hello.elf...done.
0x00000000 in ?? ()
JTAG tap: pic32mx.cpu tap/device found: 0x50978053 (mfg: 0x029, part: 0x0978, ver: 0x5)
target state: halted
target halted in MIPS32 mode due to debug-request, pc: 0xbfc00000
(gdb) stepi
stepi ignored. GDB will now fetch the register state from the target.

Program received signal SIGINT, Interrupt.
0xbfc00000 in reset_vector ()
(gdb) stepi
Cannot access memory at address 0xbfc00000
(gdb) stepi
Cannot access memory at address 0xbfc00000
(gdb) disassemble /r 0x1fc00000, 0x1fc00010
Dump of assembler code from 0x1fc00000 to 0x1fc00010:
   0x1fc00000:     c0 bf 1a 3c    lui    k0,0xbfc0
   0x1fc00004:     80 03 5a 27    addiu    k0,k0,896
   0x1fc00008:     08 00 40 03    jr    k0
   0x1fc0000c:     00 00 00 00    nop
End of assembler dump.
(gdb)

sjo
Starting Member
Re: RE: openocd and mips_m4k 2010/10/01 01:09:30
It may be your memory map that is causing the trouble.
try running 'set mem inaccessible-by-default off' in your gdb startup.

To see what the memory map is run info mem

Cheers
Spen
tcmichals
New Member
Re: RE: openocd and mips_m4k 2010/10/01 18:48:29
Ok...  yes, that works here is the memory map
0xbfc00380 in __register_exitproc ()
1: x/4i $pc
=> 0xbfc00380 <__register_exitproc+123>:    bteqz    0xbfc00383 <__register_exitproc+126>
   0xbfc00382 <__register_exitproc+125>:    daddiu    s0,s0,-6
   0xbfc00384 <__register_exitproc+127>:    addiu    a0,sp,768
   0xbfc00386 <__register_exitproc+129>:    sd    v0,208(a3)
(gdb) info mem
Using memory regions provided by the target.
Num Enb Low Addr   High Addr  Attrs
0   y      0x00000000 0x1d000000 rw nocache
1   y      0x1d000000 0x1d080000 flash blocksize 0x1000 nocache
2   y      0x1d080000 0x1fc00000 rw nocache
3   y      0x1fc00000 0x1fc03000 flash blocksize 0x1000 nocache
4   y      0x1fc03000 0x9d000000 rw nocache
5   y      0x9d000000 0x9d080000 flash blocksize 0x1000 nocache
6   y      0x9d080000 0x9fc00000 rw nocache
7   y      0x9fc00000 0x9fc03000 flash blocksize 0x1000 nocache
8   y      0x9fc03000 0xbd000000 rw nocache
9   y      0xbd000000 0xbd080000 flash blocksize 0x1000 nocache
10  y      0xbd080000 0xbfc00000 rw nocache
11  y      0xbfc00000 0xbfc03000 flash blocksize 0x1000 nocache
12  y      0xbfc03000 0x00000000 rw nocache


my next question why does flash write_image work?  Is this a problem for you? (Thank you for the help)
Re: RE: openocd and mips_m4k 2010/10/05 08:49:36
Hello,

how can I dowload the MIPS branch. The link
svn://svn.berlios.de/openocd/branches/mips does not work anymore.

Thanks.
Jan
sjo
Starting Member
Re: RE: openocd and mips_m4k 2010/10/05 08:57:28
the mips branch as it was has now been merged into the main openocd codebase.

Openocd now uses git rather than svn for versioning and the git server can be found here:
http://sourceforge.net/projects/openocd/develop
or using a http mirror
http://repo.or.cz/r/openocd.git

Cheers
Spen
Re: RE: openocd and mips_m4k 2010/10/05 09:09:18
OK, I've used this branch yesterday and tried to debug PIC32MX with it, but so far without success. I have a plain PIC with minimal setup (just a home made PCB with programming and JTAG connections). Do you know whether it's possible to use the latest git version to debug PIC32MX via JTAG??

Jan
sjo
Starting Member
Re: RE: openocd and mips_m4k 2010/10/05 09:19:53
latest git head is working fine here.
If you are getting problems it may be worth posting your config/debug log

Cheers
Spen
tcmichals
New Member
Re: RE: openocd and mips_m4k 2010/10/05 10:40:06
Ok... I guess I will do that...  I have a start on a new microbit library all open source.. Bootloader etc..
tcmichals
New Member
Re: RE: openocd and mips_m4k 2010/10/05 10:40:19
sorry microchip..
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