Hot!PIC16F690 - SPI issues

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2018/02/10 19:45:33 (permalink)
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PIC16F690 - SPI issues

Hi Forum,
 
Trying to learn about SPI. At the moment I have connected a PIC16F690 acting as master and a PIC16F887 acting as slave. The connection between the two on the breadboard seems ok as I have managed to get some data transfer going. But there seems to be a lot of issues and the code is not really working as expected. Would really appriciate a few pointers in the right direction
 
My code is based on: http://ww1.microchip.com/...s/en/devicedoc/spi.pdf
 
Unfortunately i don't have access to an oscilloscope for proper troubleshooting
Master:

 LIST p=16F690

 include "P16F690.inc"

;

 

        __CONFIG  _INTRC_OSC_NOCLKOUT & _FOSC_HS & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_ON & _IESO_ON & _FCMEN_ON

 

 

        cblock 020f

                ctrl

                send_data

                count1

                d1

                d2

                d3

        endc

 

Reset_Vector    CODE    0x000

        goto start

 

start

 

; - SPI-Master mode

        banksel PORTA

        clrf    PORTA           ; Init PORTA

        clrf    PORTC           ; Init PORTC

        clrf    PORTB           ; Init PORTB

        banksel ANSEL

        clrf    ANSEL           ; All digital

        banksel CM1CON0

        bcf     CM1CON0,7       ;

        bcf     CM2CON0,7       ; No comparatprs

        banksel TRISC

        movlw   b'00000000'     ; SDO Out

        movwf   TRISC           ; 

        movlw   b'00000000'     ;  

        movwf   TRISA           ; all output

        movwf   b'00010000'     ; SCK Out, SDI in 

        movwf   TRISB

        banksel SSPSTAT

        movlw   b'01000000'     ; Rising edge of SCK

        movwf   SSPSTAT

        banksel SSPCON

        movlw   b'00110001'     ; enable as master

        movwf   SSPCON

        movlw   b'00000000'

        movwf   count1

        goto    loop

 
 

loop

        call    dly

        banksel PORTA

        bcf     PORTA,2         ; slave select on

        movf    count1,w        ; 

        banksel SSPBUF

        movwf   SSPBUF          ; load SSPBUF

        banksel SSPSTAT

char1   btfss   SSPSTAT,BF      ; Check buffer full flag

        goto    char1

        BANKSEL SSPBUF

        movf    SSPBUF,w        ; get recived data

        call    dly             ; wait

        banksel PORTA

        bsf     PORTA,2         ; chip select off

        incf    count1,f

        goto    loop

 

dly

                        ;199993 cycles

        movlw   0x3E

        movwf   d1

        movlw   0x9D

        movwf   d2

Delay_0

        decfsz  d1, f

        goto    $+2

        decfsz  d2, f

        goto    Delay_0

 

                        ;3 cycles

        goto    $+1

        nop

 

                        ;4 cycles (including call)

        return

 

        END


Slave:

 LIST p=16F887

 include "P16F887.inc"

;

 

 __CONFIG _CONFIG1, _FOSC_INTRC_NOCLKOUT & _FOSC_HS & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_ON & _IESO_ON & _FCMEN_ON & _LVP_OFF

 __CONFIG _CONFIG2, _BOR4V_BOR40V & _WRT_OFF

 

 

Reset_Vector    CODE    0x000

        goto start

 

 

start

 

; - init SPI

        banksel PORTA

        clrf    PORTA           ; Init PORTA

        clrf    PORTC           ; init PORTC

        banksel CM1CON0

        bcf     CM1CON0,7       ; Comparator 1 off

        bcf     CM2CON0,7       ; Comparator 2 off

        banksel TRISC           ;

        movlw   b'00011000'     ; SCK,SDA IN. SDO out

        movwf   TRISC           ; 

        movlw   b'00100000'     ; SS - in 

        movwf   TRISA

        banksel SSPSTAT         ;

        movlw   b'01000000'     ; Rising edge of SCK

        movwf   SSPSTAT

        banksel SSPCON

        movlw   b'00110100'     ; SSP enable, CCP, Slave mode SS pin control

        movwf   SSPCON

        goto    loop

 

loop    banksel SSPSTAT

        movlw   SSPSTAT

        movwf   FSR

        btfss   INDF,0          ; Check id BF (Buffer full) is set

        goto    loop            ; Wait until buffer full is set

        banksel SSPBUF

        movf    SSPBUF,w

        banksel PORTA

        movwf   PORTA

        movlw   d'10'

        movwf   SSPBUF

send    banksel SSPSTAT

        btfss   SSPSTAT,BF

        goto    send

        goto    loop

 

        END


#1

24 Replies Related Threads

    qɥb
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    Re: PIC16F690 - SPI issues 2018/02/11 12:22:47 (permalink)
    0
    You don't mention what you expected to happen, and what DID happen when you tested.
     
    At first glance, the Master code looks ok, but the Slave code looks very suspicious.
    The Slave will copy the first byte received to PORTA, but return garbage to the Master.
    On the second transfer, it will discard the byte received, while returning a value of 10.
    It will then go back to outputting the next byte received to PORTA, while returning garbage.
     
     
    Why are you faffing around with FSR in this code, when it would be simpler to just access SSPSTAT directly?

    loop    banksel SSPSTAT

            movlw   SSPSTAT

            movwf   FSR

            btfss   INDF,0          ; Check id BF (Buffer full) is set


     

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    #2
    x909x
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    Re: PIC16F690 - SPI issues 2018/02/11 12:59:01 (permalink)
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    Hi,
     
    Thanks for taking the time to check the code. 
     
    What i expected to happen is that whatever is stored in count1 is sent over to the slave and output to PORTA. As count1 is incremented I should be able to see the PORTA pins go high and low.What is sent back to master is indeed garbage now as this is some sort of proof-of-concept application for just learning about SPI. What is happening currently is that all PORTA (Except for PORTA,5 which is set as input as it's SSS) goes high, which I assume could mean that the slave misinterprets that data, or gets stuck. A bit tricky to see the actual behaviour without a scope. 
     
    Regarding FSR. I simply used that approach since the used that in the code example i linked to above. 
     
    I encouraging at least that the master code looks ok. I will keep troubleshooting the slave code.
      
     
     
    #3
    qɥb
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    Re: PIC16F690 - SPI issues 2018/02/11 19:06:05 (permalink)
    0
    I just noticed this line
            cblock 020f

    I think "020f" should have been "020h"
     
    You don't set the radix, so it will default to hex.
    020f will be 020fh, which is an invalid address.
    You only have 200h RAM addresses available. If it wraps back to 00Fh, that's putting your scratch RAM right on top of the Special Function Registers.
     

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    #4
    Aussie Susan
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    Re: PIC16F690 - SPI issues 2018/02/11 19:15:13 (permalink)
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    qɥb
    020f will be 020fh, which is an invalid address.

    Actually the leading '0' will made the compiler try to interpret the number as octal until it comes to the 'f' in which case I would expect it to throw a syntax error.
    Perhaps this value means something different in assembler-land!
    Susan
    #5
    qɥb
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    Re: PIC16F690 - SPI issues 2018/02/11 19:29:02 (permalink)
    0
    Leading '0' to octal is a C convention.
    MPASM wants O'###' for octal.
     
    I was sure ##h was valid for hex, but the MPASM manual just says X'##'
      or 0x##
    (plus of course, no prefix/suffix at all if the hex is the default radix)
     
    [the odd looking line break above is to sidestep the stupid forum firewall]
     

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    #6
    x909x
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    Re: PIC16F690 - SPI issues 2018/02/12 02:59:41 (permalink)
    0
    qɥb
    I just noticed this line
            cblock 020f

    I think "020f" should have been "020h"
     
    You don't set the radix, so it will default to hex.
    020f will be 020fh, which is an invalid address.
    You only have 200h RAM addresses available. If it wraps back to 00Fh, that's putting your scratch RAM right on top of the Special Function Registers.
     




    Thanks! Embarrassing that i missed typo, even after the all the times i went through the code. Fixing this did the trick.
    #7
    x909x
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    Re: PIC16F690 - SPI issues 2018/02/12 13:52:18 (permalink)
    0
    Still struggling with SPI-concepts it seems. Using the same, but corrected, as above i now can send data from master to slave. The byte coming back however is always 0x00. Tried adding some minor delay incase the chip select line needs some time for switching. Also tried a few different combinations of pullup-resistors but no luck. The code passes the SSPSTAT,BF checks on both sides so SSPBUF is getting loaded and read. 
     
    Can anyone see any hints in the code above why the data returned from the slave would be 0x00 ?
     
     
     
    #8
    qɥb
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    Re: PIC16F690 - SPI issues 2018/02/12 14:25:18 (permalink)
    0
    "Data always zero" in a PIC nearly always points to an analog pin not switched to digital mode.
    In your case, your Master is correctly clearing ANSEL to switch AN0-AN7 to digital mode, but you're not touching ANSELH, so AN8-AN11 are still in analog mode.
    On a PIC16F690, SDI is shared with AN10, so it will always read as zero.
     
    The SSP pins are not shared with analog pins in a 16F887, so you didn't strike that problem in your slave.

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    #9
    jack@kksound
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    Re: PIC16F690 - SPI issues 2018/02/12 15:02:08 (permalink)
    0
    Since the data to be trasnmitted from the SLAVE to the MASTER must be placed in the SSPBUF register BEFORE the MASTER initiates the transfer (full duplex) the first time through the loop the data sent to the MASTER will probably NOt be the d'10' that you are later loading into SSPBUF. Don't know if that makes a difference in this case.
    #10
    x909x
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    Re: PIC16F690 - SPI issues 2018/02/12 15:23:28 (permalink)
    0
    qɥb
    "Data always zero" in a PIC nearly always points to an analog pin not switched to digital mode.
    In your case, your Master is correctly clearing ANSEL to switch AN0-AN7 to digital mode, but you're not touching ANSELH, so AN8-AN11 are still in analog mode.
    On a PIC16F690, SDI is shared with AN10, so it will always read as zero.
     
    The SSP pins are not shared with analog pins in a 16F887, so you didn't strike that problem in your slave.


    Thanks! I didn't know this. It did not solve the issue, so it seems I made more mistakes but this is a powerful tool for troubleshooting.
     
    jack@kksound
    Since the data to be trasnmitted from the SLAVE to the MASTER must be placed in the SSPBUF register BEFORE the MASTER initiates the transfer (full duplex) the first time through the loop the data sent to the MASTER will probably NOt be the d'10' that you are later loading into SSPBUF. Don't know if that makes a difference in this case.



    Interesting! Do you have any tips on how to sync up the two ? 
     
    EDIT: removed some crap code
     
     
    post edited by x909x - 2018/02/12 15:26:17
    #11
    qɥb
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    Re: PIC16F690 - SPI issues 2018/02/12 15:27:58 (permalink)
    0
    I think you are still misunderstanding the whole transfer.
    They are always locked in synch, controlled by the Master.
    Every SPI transfer is a simultaneous transfer of data Master to Slave and Slave to Master.
    It is triggered when the Master writes to its own SSPBUF register.
    The Slave must have written something to its own SSPBUF register before then.
    When the Slave sees BF full, it knows that a transfer has taken place, and should read SSPBUF and write the next byte to send.
     

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    #12
    jack@kksound
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    Re: PIC16F690 - SPI issues 2018/02/12 15:38:56 (permalink)
    0
            banksel SSPSTAT

    char1   btfss   SSPSTAT,BF      ; Check buffer full flag

            goto    char1

    rec     banksel SSPSTAT

            btfss   SSPSTAT,BF

            goto    rec
     


    You have added a redundent check of the BF flag, why?
     
    In the MASTER the BF flag indicates when the transmission is complete and therefore the receive also (full duplex operation) (the interrupt flags are actually better to use - IMHO). In the SLAVE the BF flag indicates that the receive is complete and therefore the transmit as well (still full duplex operation). Remember that the data goes in both directions at the same time, by definition when the transmit is complete so is the receive (and vice versa in the SLAVE). The SS signal syncs the SLAVE to the MASTER, falling edge of SS resets the clock counter in the slave so that it is ready to receive the first bit on the next clock from the MASTER.
    Generally:
    in the MASTER:
    SS pin LOW
    load transmit data to SSPBUF
    wait for transmit complete (BF or interrupt flag)
    Read received data from SSPBUF
    SS pin HIGH
    (do something with the data or not)
    loop around to so it again.
     
    in the SLAVE:
    load transmit data to SSPBUF
    wait for receive complete (BF or interrupt flag)
    read receive data from SSPBUF
    (do something with the data or not)
    loop around to do it again
     
     
     
     
    #13
    Gort2015
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    Re: PIC16F690 - SPI issues 2018/02/12 15:51:38 (permalink)
    0
    You don't need to sync, put data in the master spi buffer to start the exchange between master and slave.  Slave is already loaded up in preporation.
     
    What you really need is a protocol the slave can understand so that the slave can wait for commands.
    It can also return errors.
     
    Say you wanted to read memory from the slave.  You would send SLAVE_GET_MEM.
    The following data from the slave would be the memory, a cancel command would cancel it.
     
    M:send SLAVE_GET_MEM, Address, size_t
    M:for x = 0 to 10 read sp
     
    S: switch(Command) etc...
     
    That is how you do it.
     

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
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    #14
    x909x
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    Re: PIC16F690 - SPI issues 2018/02/12 16:11:33 (permalink)
    0
    Thank you all. I had missed the simultaneous transfer part of SPI. Think I grasp it now after your explanation.
     
    Still having the issue that I only manage to read the data going from master to slave. It's still something/somethings i'm misunderstanding about  this implementation.
     
    Master - Using USART to midi for troubleshooting. (I have check that this is not source of the issues. It transfers fine when loading TXREG with literal values)

     LIST p=16F690

     include "P16F690.inc"

    ;

     

            __CONFIG  _INTRC_OSC_NOCLKOUT & _FOSC_HS & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_ON & _IESO_ON & _FCMEN_ON

     

     

            cblock 0x20

                    ctrl

                    CC_data

                    count1

            endc

     

    Reset_Vector    CODE    0x000

            goto start

     

    start

     

    ;---    Initilize UARTfor MIDI Data Transfer

     

            banksel BAUDCTL

            bcf     BAUDCTL,3       ; clearing BRG16 bit

            banksel PIE1

            bcf     PIE1, 4         ; Clearing TXIE of the inerupt registers

            bcf     TXSTA, 2        ; Clearing BRGH bit

            clrf    SPBRGH          ; 

            movlw   b'00000001'     ; 

            movwf   SPBRG           ; Approx 31500 Baud

            bcf     TXSTA, 4        ; Clearing sync

            banksel RCSTA

            bsf     RCSTA, 7        ; Setting Spen bit (serial transfer eanabled)

            banksel TXSTA

            bcf     TXSTA, 6        ; clearing TX9, only 8bit transer needed

            bsf     TXSTA, 5        ; setting TXEN, same bank

    ;---

     

    ; - SPI-Master mode

            banksel PORTA

            clrf    PORTA           ; Init PORTA

            clrf    PORTC           ; Init PORTC

            clrf    PORTB           ; Init PORTB

            banksel ANSEL

            clrf    ANSEL           ; All digital

            banksel ANSELH

            clrf    ANSELH          ; All digital

            banksel CM1CON0

            bcf     CM1CON0,7       ;

            bcf     CM2CON0,7       ; No comparatprs

            banksel TRISC

            movlw   b'00000000'     ; SDO Out

            movwf   TRISC           ; 

            movlw   b'00000000'     ;  

            movwf   TRISA           ; all output

            movwf   b'00010000'     ; SCK Out, SDI in 

            movwf   TRISB

            banksel PORTA

            bsf     PORTA,2

            banksel SSPSTAT

            movlw   b'01000000'     ; Rising edge of SCK

            movwf   SSPSTAT

            banksel SSPCON

            movlw   b'00110001'     ; enable as master

            movwf   SSPCON

            movlw   b'11111111'

            movwf   count1

            goto    loop
     

    loop

            banksel PORTA

            bcf     PORTA,2         ; slave select on

            movf    count1,w        ; 

            banksel SSPBUF

            movwf   SSPBUF          ; load SSPBUF

            banksel SSPSTAT

    char1   btfss   SSPSTAT,BF      ; Check buffer full flag

            goto    char1

            banksel SSPBUF

            movf    SSPBUF,w        ; get recived data

            movwf   ctrl

            banksel PORTA

            bsf     PORTA,2         ; slave select off

            incf    count1,f

            movlw   d'10'

            movwf   CC_data

            call    sendCC

            goto    loop

     

     

    sendCC  movlw   b'10111001'

            banksel TXREG

            movwf   TXREG   ; send character from W

            call    txchar

     

            movf    ctrl,W

            andlw   07Fh

            banksel TXREG

            movwf   TXREG   ; send character from W

            call    txchar

     

            movf    CC_data,W

            andlw   07Fh

            banksel TXREG

            movwf   TXREG   ; send character from W

            call    txchar

            return

     

    txchar  bsf     STATUS,RP0

            banksel TXSTA

            btfss   TXSTA,1   ; test for end of transmission

            goto    $-1

            bcf   STATUS,RP0

            return

     

     

     

            END


     
    Slave

     

     LIST p=16F887

     include "P16F887.inc"

    ;

     

     __CONFIG _CONFIG1, _FOSC_INTRC_NOCLKOUT & _FOSC_HS & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_ON & _IESO_ON & _FCMEN_ON & _LVP_OFF

     __CONFIG _CONFIG2, _BOR4V_BOR40V & _WRT_OFF

     

     

    Reset_Vector    CODE    0x000

            goto start

     

     

    start

     

    ; - init SPI

            banksel PORTA

            clrf    PORTA           ; Init PORTA

            clrf    PORTC           ; init PORTCi

            clrf    PORTB

            banksel CM1CON0

            bcf     CM1CON0,7       ; Comparator 1 off

            bcf     CM2CON0,7       ; Comparator 2 off

            banksel TRISC           ;

            movlw   b'00011000'     ; SCK,SDA IN. SDO out

            movwf   TRISC           ; 

            movlw   b'00100000'     ; SS - in 

            movwf   TRISA

            movlw   b'00000000'     ; all out

            movwf   PORTB

            banksel SSPSTAT         ;

            movlw   b'01000000'     ; Rising edge of SCK

            movwf   SSPSTAT

            banksel SSPCON

            movlw   b'00110100'     ; SSP enable, CCP, Slave mode SS pin control

            movwf   SSPCON

            goto    loop

     

    loop    banksel SSPBUF

            movlw   d'10'

            movwf   SSPBUF

    char1   banksel SSPSTAT

            btfss   SSPSTAT,BF      ; Check id BF (Buffer full) is set

            goto    char1           ; Wait until buffer full is set

            banksel SSPBUF

            movf    SSPBUF,w

            banksel PORTB

            movwf   PORTB

            goto    loop

     

            END


    #15
    jack@kksound
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    Re: PIC16F690 - SPI issues 2018/02/12 16:59:30 (permalink)
    0
    You don't need to sync

    Not sure what you are saying here, if the MASTER and SLAVE do not use SS then there is a possibility that the MASTER and SLAVE can be "out of sync" ( lost clocks, etc) and the received bytes will not be correct (they will be shifted one or more bits). In a perfect world the two will always stay in sync, there is no perfect world.
    #16
    jack@kksound
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    Re: PIC16F690 - SPI issues 2018/02/12 17:01:04 (permalink)
    0
    Still having the issue that I only manage to read the data going from master to slave.

    What does this mean? Do you not receive in the MASTER what you expect from the SLAVE? What do you receive?
    #17
    x909x
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    Re: PIC16F690 - SPI issues 2018/02/13 02:11:28 (permalink)
    0
    jack@kksound
    What does this mean? Do you not receive in the MASTER what you expect from the SLAVE? What do you receive?

     
    It seems I receive 0 from the slave regardless of the value I use to load SPBUF. Any ideas as to what I'm misunderstanding ?  
    #18
    qɥb
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    Re: PIC16F690 - SPI issues 2018/02/13 02:16:40 (permalink)
    0
    Lets get back to basics.
    Can you see anything arriving on pin-13/SDI on your Master?
    If you connect that pin to 5V, do you still only get 0x00?
     

    This forum is mis-configured so it only works correctly if you access it via https protocol.
    The Microchip website links to it using http protocol. Will they ever catch on?
    PicForum "it just works"
    #19
    x909x
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    Re: PIC16F690 - SPI issues 2018/02/14 02:59:49 (permalink)
    0
    qɥb
    Lets get back to basics.
    Can you see anything arriving on pin-13/SDI on your Master?
    If you connect that pin to 5V, do you still only get 0x00?
     


    Thanks! Great suggestion. After testing it turned out at the SDI pin actually had connection problems to the solderless breadboard. After moving the 16f690 to a new location I now get 0xFF in the master SSPBUF if I apply 5V to the pin, but I still can't get any value i load into the slave SSPBUF to transfer. I put a multimeter on the 16f690 SDI pin and there is a lot of activity, so it does seem like some data is being transferred. 
     
    I suspect I'm doing something wrong when initializing SPI or loading SSPBUF in the slave, but I can't see what. Any ideas what I can check ? I'm using the same code for the slave. 
     

     LIST p=16F887

     include "P16F887.inc"

    ;

     

     __CONFIG _CONFIG1, _FOSC_INTRC_NOCLKOUT & _FOSC_HS & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _CPD_OFF & _BOREN_ON & _IESO_ON & _FCMEN_ON & _LVP_OFF

     __CONFIG _CONFIG2, _BOR4V_BOR40V & _WRT_OFF

     

     

    Reset_Vector    CODE    0x000

            goto start

     

     

    start

     

    ; - init SPI

            banksel PORTA

            clrf    PORTA           ; Init PORTA

            clrf    PORTC           ; init PORTCi

            clrf    PORTB

            banksel CM1CON0

            bcf     CM1CON0,7       ; Comparator 1 off

            bcf     CM2CON0,7       ; Comparator 2 off

            banksel TRISC           ;

            movlw   b'00011000'     ; SCK,SDA IN. SDO out

            movwf   TRISC           ; 

            movlw   b'00100000'     ; SS - in 

            movwf   TRISA

            movlw   b'00000000'     ; all out

            movwf   PORTB

            banksel SSPSTAT         ;

            movlw   b'01000000'     ; Rising edge of SCK

            movwf   SSPSTAT

            banksel SSPCON

            movlw   b'00110100'     ; SSP enable, CCP, Slave mode SS pin control

            movwf   SSPCON

            goto    loop

     

    loop    banksel SSPBUF

            movlw   0x7F

            movwf   SSPBUF

    char1   banksel SSPSTAT

            btfss   SSPSTAT,BF      ; Check id BF (Buffer full) is set

            goto    char1           ; Wait until buffer full is set

            banksel SSPBUF

            movf    SSPBUF,w

            banksel PORTB

            movwf   PORTB

            goto    loop

     

            END


    #20
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