AnsweredHot![worked around]Microchips PIC SPI is non-complient wrt slave select, makes it useless

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fourtytwo
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2017/11/10 09:03:08 (permalink)
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[worked around]Microchips PIC SPI is non-complient wrt slave select, makes it useless

I have just started to use the PIC24EP256MC202 an important part of the selection criteria being this had a 16 bit capable SPI interface for driving external DAC's.  If you check both the accepted industry standard (e.g. Wiki) or the data sheet for a common SPI DAC (e.g. MICROCHIP MCP4921) you will discover slave select should be active during the entire SPI transfer.
 
It seems however Microchip are non-compliant as there slave select in master mode is only active for a single clock period!
 
On what basis are you selling these chips as containing an SPI interface when it is dysfunctional ?
What work-around do you have for this problem that does not require wait loops in software ?
Why is this issue not dealt with in the silicon errata ?
 
The attached scope shot shows slave select with a 16 bit data frame 0x200F, clock speed is 1.25Mhz
 
EDIT, WORK AROUND......
Never use framed mode (SPIxCON2, FRMEN) in an attempt to get an SS signal as this causes the clock to run continuously! When FRMEN is cleared the clock is only output for the duration of the transaction.  This allows the slave select line to be driven by software using an ordinary io pin, setting it true prior to writing data to the spi buffer and returning it to false some suitable time later if at all.
post edited by fourtytwo - 2017/11/10 10:21:33

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#1
DarioG
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:12:22 (permalink)
5 (2)
Hmmm, unlikely - that thing usually works.
 
What do you mean exactly? Pic is a Master and CS is not kept low for the whole transaction?
CS is driven by the user code, when a Master

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fourtytwo
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:15:59 (permalink)
1 (1)
That is exactly correct if you check the data sheet for a typical SPI slave such as the MCP4921 DAC you will see it is supposed to be low for the entire transaction. IN master mode the PIC DOES DRIVE SS just not in a compliant manner. It is not possible to resolve this in software as slave select needs to be EXACTLY aligned with the SPI clock.
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DarioG
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:19:17 (permalink)
5 (1)
I see, and understand.
Which software are you referring to?
 
Like I said, the SS line, in Master Mode, is driven in software - so there could be some simple bug going on.
Also, it's not usually needed that SS is aligned with Clock.

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fourtytwo
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:30:08 (permalink)
1 (3)
"Also, it's not usually needed that SS is aligned with Clock."
I am sorry but you have failed to read and understand the MPC4921 data sheet correctly, perhaps you are not familiar with SPI or hardware in general. Firstly as soon as SS goes active it will shift in data until SS goes inactive. Given the PIC generates a continuous clock (as does any other normal SPI master) it is entirely down to the timing of SS to control the transaction correctly.
 
The software I am referring to is that running on the PIC processor, I cannot see why you think any other software might be involved.
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DarioG
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:33:57 (permalink)
5 (3)
fourtytwo
 perhaps you are not familiar with SPI or hardware in general.



I assure you I am Smile
 
I did use that DAC, by the way: and no, you can lower SS any time, then start sending data - and ONLY in this moment the SPI module will generate Clock pulses, as needed.
 
Post your code, possibly.

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vjasinski
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:38:13 (permalink)
4.67 (3)
It's my understanding that the PIC SS is only used in slave mode. Your PIC is the master, talking to the slave DAC, which does indeed need a 'CS' active during the SPI transfer. Your code should provide an output 'CS' to the DAC.
 Activate before transmit, de-activate when SPI complete. Under your control, not the SPI module.
Vince
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fourtytwo
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:40:49 (permalink)
2 (2)
I think your probably using some C library code! I program these devices in assembly only.
I can assure you in master mode the clock runs continuously assuming the device remains enabled. Here is my initialization code
    mov        #(1<<MODE16)|(1<<CKE)|(1<<MSTEN)|(6<<SPRE0)|(1<<PPRE0),w0 ; 16 bit,
    mov        w0,SPI1CON1            ; dx clkneg, master, sec pscale 2:1, pri 16:1
    mov        #(1<<FRMEN),w0        ; framed mode
    mov        w0,SPI1CON2
    bset    SPI1STAT,#SPIEN




 
 
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DarioG
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:42:34 (permalink) ☼ Best Answerby fourtytwo 2017/11/10 09:43:34
5 (2)
Ah, framed mode! I did not use it, so far: can you try "normal mode"? Usually that makes life easier...
 
(C or assembler makes no difference)

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fourtytwo
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:42:59 (permalink)
1 (2)
vjasinski
 Activate before transmit, de-activate when SPI complete. Under your control, not the SPI module.

Sorry but could you please read and understand the thread and MCP4921 data sheet before replying here
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fourtytwo
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:45:15 (permalink)
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DarioG
Ah, framed mode! I did not use it, so far: can you try "normal mode"? Usually that makes life easier...
(C or assembler makes no difference)

In normal mode there would be no SS signal at all so I don't see how that would help ?
C might make a difference if using library code
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crosland
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:46:25 (permalink)
4.75 (4)
No, it is you who has failed to understand the PIC24 datasheet.
 
Look at The SPI chapter of the PIC24 Family reference Manual DS70005185A page 14 "In Master mode, the SPIx module does not control the SSx pin. This pin should be configured as a General Purpose I/O (GPIO) by clearing the SSEN bit (SPIxCON1<7>) = 0."
 
The Slave select function of the SS/FSYNC is only used in slave mode. What you are looking at is the frame sync pulse output on the SS/FSYNC pin in master mode.
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DarioG
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:46:45 (permalink) ☄ Helpfulby fourtytwo 2017/11/10 10:11:36
5 (2)
Took a look at Framed mode, in FRM document DS70005185:
Definitely the "framed mode" creates a single pulse at SS pin, generated in hardware: I don't know which devices may want or need it, but definitely MCP4921 is not among them :)
So, remove the Framed mode and drive manually CS like vjasinski suggested (and me too!)

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vjasinski
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:47:15 (permalink) ☄ Helpfulby fourtytwo 2017/11/10 10:11:52
4.67 (3)
The FRM for SPI indicates that the SS sync pulse in framed mode does not encapsulate the entire message. The Data sheet for the MCP4921 refers to a CS. Does not look like you can use the framed mode and SS.
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DarioG
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:47:50 (permalink)
5 (1)
(Framed mode resembles somehow I2S or alike audio protocols...)
 

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fourtytwo
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:51:12 (permalink)
1 (1)
crosland
No, it is you who has failed to understand the PIC24 datasheet.
 
Look at The SPI chapter of the PIC24 Family reference Manual DS70005185A page 14 "In Master mode, the SPIx module does not control the SSx pin. This pin should be configured as a General Purpose I/O (GPIO) by clearing the SSEN bit (SPIxCON1<7>) = 0."
 
The Slave select function of the SS/FSYNC is only used in slave mode. What you are looking at is the frame sync pulse output on the SS/FSYNC pin in master mode.


And so as you correctly point out it is non-compliant because it is apparently unable to generate a compliant slave select signal in master mode!
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fourtytwo
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:52:39 (permalink)
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DarioG
Took a look at Framed mode, in FRM document DS70005185:
Definitely the "framed mode" creates a single pulse at SS pin, generated in hardware: I don't know which devices may want or need it, but definitely MCP4921 is not among them :)
So, remove the Framed mode and drive manually CS like vjasinski suggested (and me too!)


Once again how to do that synchronously with a presently 1.25Mhz clock that I was hoping to raise to 5Mhz.  I wonder what is that fastest you have driven a DAC from the PIC SPI port ?
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DarioG
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:54:17 (permalink)
5 (1)
You lower SS pin writing to a LAT register, then you write to SSPBUF etc and check for busy flag, repeat for as many bytes are needed to send, then raise SS.
Perfectly working up to many megahertz, you only need to add a single Write to a pin before and after.

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DavidBLit
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:54:31 (permalink)
5 (6)
fourtytwo
... <directed at Dario>
perhaps you are not familiar with SPI or hardware in general.
...

I had to laugh at that one!  Where do they find these arrogant clowns?

Yeah, "//Code and stuff".
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vjasinski
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Re: MIcrochips PIC SPI is non-complient wrt slave select, makes it useless 2017/11/10 09:56:27 (permalink)
4.5 (2)
I currently run several projects with multiple slaves on SPI running at up to 12MHz. No problem as Dario indicates. Use interrupts , set/clear the output bit, continue. takes all of 1 instructions cycle.
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