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Measurement AFEs Technology

Delta-Sigma Analog-to-Digital Converter

A Delta-Sigma ADC is an oversampling converter that incorporates a built-in modulator, which is digitizing the quantity of charge integrated by the modulator loop. The quantizer is the block that is performing the Analog-to-Digital conversion. Multi-bit quantizers help to lower the quantization error without changing the order of the modulator or the over-sampling rate (OSR), which leads to better SNR figures. Typically, however, the linearity of such architectures is more difficult to achieve since the DAC non-linearity limits the THD of such ADCs. Our architecture utilizes a Flash ADC for the multi-level quantizer and a proprietary multi-level DAC architecture that is inherently linear for improved SNR and THD figures.

885x365_DeltaSigmaAnalogtoDigitalConverter

Dithering

Dithering can be applied to a Delta-Sigma ADC to suppress the tones and improve THD, which is crucial for power metering applications. Dithering is the process of adding an error to the ADC feedback loop in order to “decorrelate” the outputs and “break” the Idle tones behavior. This error is filtered by the feedback loop and typically has a zero average value so that the converter static transfer function is not disturbed by the dithering process. However, the dithering process slightly increases the noise floor while reducing its tonal behavior, and thus, improving SFDR and THD. The dithering process scrambles the Idle tones into baseband white noise and ensures that dynamic specs (SNR, SINAD, THD, SFDR) are less signal dependent. The performance of the MCP3911 illustrated in the graphs below show the advantages of Microchip Technology’s proprietary dithering algorithm which allows for industry leading accuracy.

SINAD vs. OSR

885x365_SINADvsOSR

THD vs. OSR

885x365_THDvsOSR

Integrated Non-Linearity vs. Input Voltage

885x365_Integrated_non_linearity

Metering Video Channel